Processeur 16 Instructions : NOP, ADD, SUB, MUL, DIV, INF, SUP, EQU, AFC, CPY, LOAD, JMP, JMZ, STORE, CALL, RET (ordre non garanti)
This commit is contained in:
parent
aa545cd03a
commit
24bb67c7e3
29 changed files with 7317 additions and 212 deletions
|
|
@ -0,0 +1,299 @@
|
|||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## Switches
|
||||
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
## LEDs
|
||||
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
|
||||
set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
|
||||
set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
|
||||
|
||||
|
||||
##7 segment display
|
||||
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
#set_property PACKAGE_PIN V7 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
|
||||
|
||||
##Buttons
|
||||
set_property PACKAGE_PIN U18 [get_ports btnC]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
#set_property PACKAGE_PIN T18 [get_ports btnU]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
set_property PACKAGE_PIN W19 [get_ports btnL]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
set_property PACKAGE_PIN T17 [get_ports btnR]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
#set_property PACKAGE_PIN U17 [get_ports btnD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Sch name = JA1
|
||||
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Sch name = JA2
|
||||
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Sch name = JA3
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Sch name = JA4
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Sch name = JA7
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Sch name = JA8
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Sch name = JA9
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Sch name = JA10
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Sch name = JB1
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Sch name = JB2
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Sch name = JB3
|
||||
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Sch name = JB4
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Sch name = JB7
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Sch name = JB8
|
||||
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Sch name = JB9
|
||||
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Sch name = JB10
|
||||
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Sch name = JC1
|
||||
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Sch name = JC2
|
||||
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Sch name = JC3
|
||||
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Sch name = JC4
|
||||
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Sch name = JC7
|
||||
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Sch name = JC8
|
||||
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Sch name = JC9
|
||||
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Sch name = JC10
|
||||
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Sch name = XA1_P
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Sch name = XA2_P
|
||||
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Sch name = XA3_P
|
||||
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Sch name = XA4_P
|
||||
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Sch name = XA1_N
|
||||
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Sch name = XA2_N
|
||||
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Sch name = XA3_N
|
||||
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Sch name = XA4_N
|
||||
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
#set_property PACKAGE_PIN P19 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
#set_property PACKAGE_PIN R19 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property PACKAGE_PIN B18 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
#set_property PACKAGE_PIN A18 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
84
Processeur.srcs/sim_1/new/TestALU.vhd
Normal file
84
Processeur.srcs/sim_1/new/TestALU.vhd
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 21:25:53
|
||||
-- Design Name:
|
||||
-- Module Name: TestALU - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity TestALU is
|
||||
-- Port ( );
|
||||
end TestALU;
|
||||
|
||||
architecture Behavioral of TestALU is
|
||||
component ALU is
|
||||
Generic (Nb_bits : Natural);
|
||||
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
OP : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
|
||||
signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
|
||||
signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
|
||||
signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
|
||||
signal my_N : STD_LOGIC := '0';
|
||||
signal my_O : STD_LOGIC := '0';
|
||||
signal my_Z : STD_LOGIC := '0';
|
||||
signal my_C : STD_LOGIC := '0';
|
||||
|
||||
begin
|
||||
|
||||
instance : ALU
|
||||
generic map (Nb_bits => 16)
|
||||
port map (
|
||||
A => my_A,
|
||||
B => my_B,
|
||||
OP => my_OP,
|
||||
S => my_S,
|
||||
N => my_N,
|
||||
O => my_O,
|
||||
Z => my_Z,
|
||||
C => my_C
|
||||
);
|
||||
|
||||
process
|
||||
begin
|
||||
my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
|
||||
my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
|
||||
my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
||||
104
Processeur.srcs/sim_1/new/TestBancRegistres.vhd
Normal file
104
Processeur.srcs/sim_1/new/TestBancRegistres.vhd
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 12:58:02
|
||||
-- Design Name:
|
||||
-- Module Name: TestBancRegistres - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity TestBancRegistres is
|
||||
-- Port ( );
|
||||
end TestBancRegistres;
|
||||
|
||||
architecture Behavioral of TestBancRegistres is
|
||||
component BancRegistres
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Nb_regs : Natural);
|
||||
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
W : in STD_LOGIC;
|
||||
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_AddrA : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
|
||||
signal my_AddrB : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
|
||||
signal my_AddrW : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
|
||||
signal my_W : STD_LOGIC := '0';
|
||||
signal my_DATA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_RST : STD_LOGIC := '0';
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_QA : STD_LOGIC_VECTOR (7 downto 0);
|
||||
signal my_QB : STD_LOGIC_VECTOR (7 downto 0);
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
|
||||
instance : BancRegistres
|
||||
generic map (Nb_bits => 8,
|
||||
Addr_size => 2,
|
||||
Nb_regs => 4
|
||||
)
|
||||
port map (
|
||||
AddrA => my_AddrA,
|
||||
AddrB => my_AddrB,
|
||||
AddrW => my_AddrW,
|
||||
W => my_W,
|
||||
DATA => my_DATA,
|
||||
RST => my_RST,
|
||||
CLK => my_CLK,
|
||||
QA => my_QA,
|
||||
QB => my_QB
|
||||
);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
my_RST <= '1' after 0 ns, '0' after 100 ns;
|
||||
my_AddrA <= "11" after 20 ns, "00" after 50 ns;
|
||||
my_AddrB <= "11" after 30 ns;
|
||||
my_AddrW <= "11" after 10 ns, "00" after 50 ns;
|
||||
my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 60 ns, '1' after 110 ns;
|
||||
my_DATA <= "01010101" after 10 ns, "11111111" after 50 ns;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
99
Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd
Normal file
99
Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 12:58:02
|
||||
-- Design Name:
|
||||
-- Module Name: TestMemoireAdressesRetour - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity TestMemoireAdressesRetour is
|
||||
-- Port ( );
|
||||
end TestMemoireAdressesRetour;
|
||||
|
||||
architecture Behavioral of TestMemoireAdressesRetour is
|
||||
component MemoireAdressesRetour is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( R : in STD_LOGIC;
|
||||
W : in STD_LOGIC;
|
||||
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
E : out STD_LOGIC;
|
||||
F : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal my_R : STD_LOGIC := '0';
|
||||
signal my_W : STD_LOGIC := '0';
|
||||
signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_RST : STD_LOGIC := '0';
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
|
||||
signal my_E : STD_LOGIC;
|
||||
signal my_F : STD_LOGIC;
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
|
||||
instance : MemoireAdressesRetour
|
||||
generic map (Nb_bits => 8,
|
||||
Addr_size => 2,
|
||||
Mem_size => 4
|
||||
)
|
||||
port map (
|
||||
R => my_R,
|
||||
W => my_W,
|
||||
D_IN => my_D_IN,
|
||||
RST => my_RST,
|
||||
CLK => my_CLK,
|
||||
D_OUT => my_D_OUT,
|
||||
E => my_E,
|
||||
F => my_F
|
||||
);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
my_RST <= '1' after 0 ns, '0' after 100 ns;
|
||||
my_R <= '1' after 20 ns, '0' after 30 ns;
|
||||
my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 90 ns, '0' after 110 ns;
|
||||
my_D_IN <= "01010101" after 10 ns, "11100111" after 30 ns, "11111111" after 50 ns, "11111110" after 60 ns, "11111101" after 70 ns, "11111100" after 80 ns;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
93
Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd
Normal file
93
Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 12:58:02
|
||||
-- Design Name:
|
||||
-- Module Name: TestMemoireDonnees - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity TestMemoireDonnees is
|
||||
-- Port ( );
|
||||
end TestMemoireDonnees;
|
||||
|
||||
architecture Behavioral of TestMemoireDonnees is
|
||||
component MemoireDonnees is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
RW : in STD_LOGIC;
|
||||
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_Addr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
|
||||
signal my_RW : STD_LOGIC := '1';
|
||||
signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_RST : STD_LOGIC := '0';
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
|
||||
instance : MemoireDonnees
|
||||
generic map (Nb_bits => 8,
|
||||
Addr_size => 2,
|
||||
Mem_size => 4
|
||||
)
|
||||
port map (
|
||||
Addr => my_Addr,
|
||||
RW => my_RW,
|
||||
D_IN => my_D_IN,
|
||||
RST => my_RST,
|
||||
CLK => my_CLK,
|
||||
D_OUT => my_D_OUT
|
||||
);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
my_RST <= '1' after 0 ns, '0' after 100 ns;
|
||||
my_RW <= '1' after 0 ns, '0' after 10 ns, '1' after 30 ns;
|
||||
my_Addr <= "01" after 10 ns, "10" after 20 ns, "11" after 40 ns, "01" after 70 ns;
|
||||
my_D_IN <= "01010101" after 10 ns, "11100111" after 20 ns, "11111111" after 50 ns;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
67
Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd
Normal file
67
Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 12:58:02
|
||||
-- Design Name:
|
||||
-- Module Name: TestMemoireInstructions - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity TestMemoireInstructions is
|
||||
-- Port ( );
|
||||
end TestMemoireInstructions;
|
||||
|
||||
architecture Behavioral of TestMemoireInstructions is
|
||||
component MemoireInstructions is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_Addr : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
|
||||
signal my_D_OUT : STD_LOGIC_VECTOR (27 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
instance : MemoireInstructions
|
||||
generic map (Nb_bits => 28,
|
||||
Addr_size => 4,
|
||||
Mem_size => 16
|
||||
)
|
||||
port map (
|
||||
Addr => my_Addr,
|
||||
D_OUT => my_D_OUT
|
||||
);
|
||||
|
||||
process
|
||||
begin
|
||||
my_Addr <= "0001" after 10 ns, "0010" after 20 ns, "0011" after 30 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
121
Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
Normal file
121
Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19.04.2021 14:31:37
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Etage2_5_Registres - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_Etage2_5_Registres is
|
||||
-- Port ( );
|
||||
end Test_Etage2_5_Registres;
|
||||
|
||||
architecture Behavioral of Test_Etage2_5_Registres is
|
||||
component Etage2_5_Registres is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Nb_registres : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_RST : STD_LOGIC := '1';
|
||||
signal my_IN_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal my_OUT_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal my_IN_5_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_5_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_5_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
|
||||
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (7 downto 0) := "01111110";
|
||||
constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (7 downto 0) := "01100001";
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
|
||||
instance : Etage2_5_Registres
|
||||
generic map( Nb_bits => 8,
|
||||
Nb_Registres => 16,
|
||||
Instruction_bus_size => 3,
|
||||
Bits_Controle_LC_5 => Bits_Controle_LC_5,
|
||||
Bits_Controle_MUX_2 => Bits_Controle_MUX_2)
|
||||
port map( CLK => my_CLK,
|
||||
RST => my_RST,
|
||||
IN_2_A => my_IN_2_A,
|
||||
IN_2_B => my_IN_2_B,
|
||||
IN_2_C => my_IN_2_C,
|
||||
IN_2_Instruction => my_IN_2_Instruction,
|
||||
OUT_2_A => my_OUT_2_A,
|
||||
OUT_2_B => my_OUT_2_B,
|
||||
OUT_2_C => my_OUT_2_C,
|
||||
OUT_2_Instruction => my_OUT_2_Instruction,
|
||||
IN_5_A => my_IN_5_A,
|
||||
IN_5_B => my_IN_5_B,
|
||||
IN_5_Instruction => my_IN_5_Instruction);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
my_RST <= '0' after 33 ns;
|
||||
my_IN_2_A <= "01011111" after 0 ns;
|
||||
my_IN_2_B <= "00000011" after 0 ns, "00000100" after 40 ns;
|
||||
my_IN_2_C <= "00000001" after 0 ns, "00000000" after 40 ns;
|
||||
my_IN_2_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
|
||||
my_IN_5_A <= "00000010" after 0 ns, "00000000" after 10 ns, "00000011" after 20 ns, "00000010" after 30 ns;
|
||||
my_IN_5_B <= "11111111" after 0 ns, "11111110" after 10 ns, "11111101" after 20 ns, "11111100" after 30 ns;
|
||||
my_IN_5_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
105
Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
Normal file
105
Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19.04.2021 11:26:48
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Etage3_Calcul - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_Etage3_Calcul is
|
||||
-- Port ( );
|
||||
end Test_Etage3_Calcul;
|
||||
|
||||
architecture Behavioral of Test_Etage3_Calcul is
|
||||
component Etage3_Calcul is
|
||||
Generic ( Nb_bits : Natural;
|
||||
OP_vector_size : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX : STD_LOGIC_VECTOR);
|
||||
Port ( RST : STD_LOGIC;
|
||||
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal my_RST : STD_LOGIC := '1';
|
||||
signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal my_N : STD_LOGIC;
|
||||
signal my_O : STD_LOGIC;
|
||||
signal my_Z : STD_LOGIC;
|
||||
signal my_C : STD_LOGIC;
|
||||
|
||||
constant Bits_Controle_LC : STD_LOGIC_VECTOR (15 downto 0) := x"00b4";
|
||||
constant Bits_Controle_MUX : STD_LOGIC_VECTOR (7 downto 0) := "11110001";
|
||||
|
||||
begin
|
||||
|
||||
instance : Etage3_Calcul
|
||||
generic map( Nb_bits => 8,
|
||||
OP_vector_size => 2,
|
||||
Instruction_bus_size => 3,
|
||||
Bits_Controle_LC => Bits_Controle_LC,
|
||||
Bits_Controle_MUX => Bits_Controle_MUX)
|
||||
port map( RST => my_RST,
|
||||
IN_A => my_IN_A,
|
||||
IN_B => my_IN_B,
|
||||
IN_C => my_IN_C,
|
||||
IN_Instruction => my_IN_Instruction,
|
||||
OUT_A => my_OUT_A,
|
||||
OUT_B => my_OUT_B,
|
||||
OUT_Instruction => my_OUT_Instruction,
|
||||
N => my_N,
|
||||
O => my_O,
|
||||
Z => my_Z,
|
||||
C => my_C);
|
||||
|
||||
process
|
||||
begin
|
||||
my_IN_A <= "01011111";
|
||||
my_IN_B <= "10100110";
|
||||
my_IN_C <= "01101101";
|
||||
my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
|
||||
my_RST <= '0' after 45 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
105
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
Normal file
105
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19.04.2021 13:37:04
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Etage4_Memoire - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_Etage4_Memoire is
|
||||
-- Port ( );
|
||||
end Test_Etage4_Memoire;
|
||||
|
||||
architecture Behavioral of Test_Etage4_Memoire is
|
||||
component Etage4_Memoire is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Mem_size : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_RST : STD_LOGIC := '1';
|
||||
signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
|
||||
constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
|
||||
constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
|
||||
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
|
||||
instance : Etage4_Memoire
|
||||
generic map( Nb_bits => 8,
|
||||
Mem_size => 256,
|
||||
Instruction_bus_size => 3,
|
||||
Bits_Controle_LC => Bits_Controle_LC,
|
||||
Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
|
||||
Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
|
||||
port map( CLK => my_CLK,
|
||||
RST => my_RST,
|
||||
IN_A => my_IN_A,
|
||||
IN_B => my_IN_B,
|
||||
IN_Instruction => my_IN_Instruction,
|
||||
OUT_A => my_OUT_A,
|
||||
OUT_B => my_OUT_B,
|
||||
OUT_Instruction => my_OUT_Instruction);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
|
||||
my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
|
||||
my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
|
||||
my_RST <= '0' after 125 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
118
Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd
Normal file
118
Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18.04.2021 22:28:40
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Etape1_LectureInstruction - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_Etape1_LectureInstruction is
|
||||
-- Port ( );
|
||||
end Test_Etape1_LectureInstruction;
|
||||
|
||||
architecture Behavioral of Test_Etape1_LectureInstruction is
|
||||
component Etage1_LectureInstruction is
|
||||
Generic (Instruction_size_in_memory : Natural;
|
||||
Addr_size_mem_instruction : Natural;
|
||||
Mem_instruction_size : Natural;
|
||||
Nb_bits : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Nb_registres : Natural;
|
||||
Mem_adresse_retour_size : Natural;
|
||||
Adresse_size_mem_adresse_retour : Natural;
|
||||
Instructions_critiques_lecture : STD_LOGIC_VECTOR;
|
||||
Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
|
||||
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_JMP : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_CALL : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_RET : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
Z : in STD_LOGIC;
|
||||
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_RST : STD_LOGIC := '1';
|
||||
signal my_Z : STD_LOGIC := '1';
|
||||
|
||||
constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
|
||||
constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
|
||||
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
instance : Etage1_LectureInstruction
|
||||
generic map (Instruction_size_in_memory => 28,
|
||||
Addr_size_mem_instruction => 4,
|
||||
Mem_instruction_size => 16,
|
||||
Nb_bits => 8,
|
||||
Instruction_bus_size => 4,
|
||||
Nb_registres => 16,
|
||||
Mem_adresse_retour_size => 4,
|
||||
Adresse_size_mem_adresse_retour => 2,
|
||||
Instructions_critiques_lecture => Instructions_critiques_lecture,
|
||||
Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
|
||||
Instructions_critiques_ecriture => Instructions_critiques_ecriture,
|
||||
Code_Instruction_JMP => "1100",
|
||||
Code_Instruction_JMZ => "1101",
|
||||
Code_Instruction_CALL => "1110",
|
||||
Code_Instruction_RET => "1111"
|
||||
)
|
||||
port map (
|
||||
CLK => my_CLK,
|
||||
RST => my_RST,
|
||||
z => my_Z,
|
||||
A => my_A,
|
||||
B => my_B,
|
||||
C => my_C,
|
||||
Instruction => my_Instruction
|
||||
);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
66
Processeur.srcs/sim_1/new/Test_LC.vhd
Normal file
66
Processeur.srcs/sim_1/new/Test_LC.vhd
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17.04.2021 22:43:43
|
||||
-- Design Name:
|
||||
-- Module Name: Test_LC - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_LC is
|
||||
-- Port ( );
|
||||
end Test_LC;
|
||||
|
||||
architecture Behavioral of Test_LC is
|
||||
component LC is
|
||||
Generic (Instruction_Vector_Size : Natural;
|
||||
Command_size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal my_Commande : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
|
||||
constant Bits_Controle : STD_LOGIC_VECTOR (15 downto 0) := x"c138";
|
||||
begin
|
||||
|
||||
instance : LC
|
||||
generic map (Instruction_Vector_Size => 3,
|
||||
Command_size => 2,
|
||||
Bits_Controle => Bits_Controle)
|
||||
port map (
|
||||
Instruction => my_Instruction,
|
||||
Commande => my_Commande
|
||||
);
|
||||
|
||||
process
|
||||
begin
|
||||
my_Instruction <= "000" after 1 ns, "001" after 2 ns, "010" after 3 ns, "011" after 4 ns, "100" after 5 ns, "101" after 6 ns, "110" after 7 ns, "111" after 8 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
74
Processeur.srcs/sim_1/new/Test_MUX.vhd
Normal file
74
Processeur.srcs/sim_1/new/Test_MUX.vhd
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17.04.2021 22:43:43
|
||||
-- Design Name:
|
||||
-- Module Name: Test_MUX - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_MUX is
|
||||
-- Port ( );
|
||||
end Test_MUX;
|
||||
|
||||
architecture Behavioral of Test_MUX is
|
||||
component MUX is
|
||||
Generic (Nb_bits : Natural;
|
||||
Instruction_Vector_Size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
|
||||
signal my_IN1 : STD_LOGIC_VECTOR (15 downto 0);
|
||||
signal my_IN2 : STD_LOGIC_VECTOR (15 downto 0);
|
||||
signal my_OUTPUT : STD_LOGIC_VECTOR (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
instance : MUX
|
||||
generic map (Nb_bits => 16,
|
||||
Instruction_Vector_Size => 4,
|
||||
Bits_Controle => x"aaaa")
|
||||
port map (
|
||||
Instruction => my_Instruction,
|
||||
IN1 => my_IN1,
|
||||
IN2 => my_IN2,
|
||||
OUTPUT => my_OUTPUT
|
||||
);
|
||||
|
||||
process
|
||||
begin
|
||||
my_IN1 <= x"abcd";
|
||||
my_IN2 <= x"1234";
|
||||
my_Instruction <= "0000" after 1 ns, "0001" after 2 ns, "0010" after 3 ns, "0011" after 4 ns, "0100" after 5 ns, "0101" after 6 ns, "0110" after 7 ns, "0111" after 8 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
80
Processeur.srcs/sim_1/new/Test_Pipeline.vhd
Normal file
80
Processeur.srcs/sim_1/new/Test_Pipeline.vhd
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19.04.2021 17:35:57
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_Pipeline is
|
||||
-- Port ( );
|
||||
end Test_Pipeline;
|
||||
|
||||
architecture Behavioral of Test_Pipeline is
|
||||
|
||||
component Pipeline is
|
||||
Generic (Nb_bits : Natural := 8;
|
||||
Instruction_En_Memoire_Size : Natural := 28;
|
||||
Addr_Memoire_Instruction_Size : Natural := 3;
|
||||
Memoire_Instruction_Size : Natural := 8;
|
||||
Instruction_Bus_Size : Natural := 4;
|
||||
Nb_Instructions : Natural := 16;
|
||||
Nb_Registres : Natural := 16;
|
||||
Memoire_Size : Natural := 8;
|
||||
Memoire_Adresses_Retour_Size : Natural := 16;
|
||||
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
|
||||
Port (CLK : STD_LOGIC;
|
||||
RST : STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal my_CLK : STD_LOGIC := '0';
|
||||
signal my_RST : STD_LOGIC := '1';
|
||||
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
begin
|
||||
instance : Pipeline
|
||||
generic map (Addr_Memoire_Instruction_Size => 4,
|
||||
Memoire_Instruction_Size => 16)
|
||||
port map (CLK => my_CLK,
|
||||
RST => my_RST);
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
my_CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
my_CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
my_RST <= '0' after 34 ns, '1' after 57 ns;
|
||||
wait;
|
||||
end process;
|
||||
end Behavioral;
|
||||
85
Processeur.srcs/sources_1/new/ALU.vhd
Normal file
85
Processeur.srcs/sources_1/new/ALU.vhd
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13.04.2021 10:07:41
|
||||
-- Design Name:
|
||||
-- Module Name: ALU - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity ALU is
|
||||
Generic (Nb_bits : Natural);
|
||||
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
OP : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end ALU;
|
||||
|
||||
architecture Behavioral of ALU is
|
||||
signal A9 : STD_LOGIC_VECTOR (Nb_bits downto 0);
|
||||
signal B9 : STD_LOGIC_VECTOR (Nb_bits downto 0);
|
||||
signal ADD : STD_LOGIC_VECTOR (Nb_bits downto 0);
|
||||
signal SUB : STD_LOGIC_VECTOR (Nb_bits downto 0);
|
||||
signal MUL : STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0);
|
||||
signal intern_N : STD_LOGIC;
|
||||
signal intern_Z : STD_LOGIC;
|
||||
constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
|
||||
constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
A9 <= '0' & A;
|
||||
B9 <= '0' & B;
|
||||
ADD <= A9 + B9;
|
||||
SUB <= A9 - B9;
|
||||
MUL <= A * B;
|
||||
|
||||
S <= ADD (Nb_bits-1 downto 0) when OP = "001" else
|
||||
SUB (Nb_bits-1 downto 0) when OP = "010" else
|
||||
MUL (Nb_bits-1 downto 0) when OP = "011" else
|
||||
-- Add division
|
||||
(0 => intern_N, others => '0') when OP = "101" else
|
||||
(0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else
|
||||
(0 => intern_Z, others => '0') when OP = "111" else
|
||||
(others => '0');
|
||||
|
||||
|
||||
intern_N <= SUB (Nb_bits);
|
||||
intern_Z <= '1' when (SUB = ZERO_N1) else
|
||||
'0';
|
||||
|
||||
N <= intern_N;
|
||||
O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
|
||||
'1';
|
||||
Z <= intern_Z;
|
||||
C <= ADD (Nb_bits);
|
||||
end Behavioral;
|
||||
68
Processeur.srcs/sources_1/new/BancRegistres.vhd
Normal file
68
Processeur.srcs/sources_1/new/BancRegistres.vhd
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.04.2021 08:23:48
|
||||
-- Design Name:
|
||||
-- Module Name: BancRegistres - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity BancRegistres is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Nb_regs : Natural);
|
||||
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
W : in STD_LOGIC;
|
||||
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
|
||||
end BancRegistres;
|
||||
|
||||
-- ASK MEILLEURE IDEE UN TABLEAU
|
||||
architecture Behavioral of BancRegistres is
|
||||
signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0');
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until CLK'event and CLK = '1';
|
||||
if (RST = '0') then
|
||||
REGISTRES <= (others => '0');
|
||||
else
|
||||
if (W = '1') then
|
||||
REGISTRES (((to_integer(unsigned(AddrW)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(AddrW))) <= DATA;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
|
||||
QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
|
||||
end Behavioral;
|
||||
196
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd
Normal file
196
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18.04.2021 21:19:41
|
||||
-- Design Name:
|
||||
-- Module Name: Etage1_LectureInstruction - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Etage1_LectureInstruction is
|
||||
Generic (Instruction_size_in_memory : Natural;
|
||||
Addr_size_mem_instruction : Natural;
|
||||
Mem_instruction_size : Natural;
|
||||
Nb_bits : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Nb_registres : Natural;
|
||||
Mem_adresse_retour_size : Natural;
|
||||
Adresse_size_mem_adresse_retour : Natural;
|
||||
Instructions_critiques_lecture : STD_LOGIC_VECTOR;
|
||||
Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
|
||||
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_JMP : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_CALL : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_RET : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
Z : in STD_LOGIC;
|
||||
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end Etage1_LectureInstruction;
|
||||
|
||||
architecture Behavioral of Etage1_LectureInstruction is
|
||||
component MemoireInstructions is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
|
||||
end component;
|
||||
|
||||
component MemoireAdressesRetour is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( R : in STD_LOGIC;
|
||||
W : in STD_LOGIC;
|
||||
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
|
||||
E : out STD_LOGIC;
|
||||
F : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
|
||||
signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
|
||||
signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
|
||||
|
||||
subtype Registre is integer range -1 to Nb_registres - 1;
|
||||
type Tab_registres is array (1 to 4) of Registre;
|
||||
signal Tableau : Tab_registres := (others => - 1);
|
||||
|
||||
signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
|
||||
signal Nul : STD_LOGIC := '0';
|
||||
signal R_Aux : STD_LOGIC := '0';
|
||||
signal W_Aux : STD_LOGIC := '0';
|
||||
|
||||
constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
|
||||
constant Argument_nul : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
|
||||
signal bulles : boolean := false;
|
||||
|
||||
signal compteur : integer := 0;
|
||||
|
||||
begin
|
||||
instance : MemoireInstructions
|
||||
generic map (Nb_bits => Instruction_size_in_memory,
|
||||
Addr_size => Addr_size_mem_instruction,
|
||||
Mem_size => Mem_instruction_size)
|
||||
port map (Addr => Pointeur_Instruction,
|
||||
D_OUT => Instruction_courante);
|
||||
|
||||
instance_MemoireAdressesRetour : MemoireAdressesRetour
|
||||
generic map (Nb_bits => Addr_size_mem_instruction,
|
||||
Addr_size => Adresse_size_mem_adresse_retour,
|
||||
Mem_size => Mem_adresse_retour_size
|
||||
)
|
||||
port map ( R => R_Aux,
|
||||
W => W_Aux,
|
||||
D_IN => Pointeur_instruction_next,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
D_OUT => Adresse_Retour,
|
||||
E => Nul,
|
||||
F => Nul
|
||||
);
|
||||
|
||||
|
||||
process
|
||||
begin
|
||||
wait until CLK'event and CLK = '1';
|
||||
if (RST = '0') then
|
||||
Tableau <= (others => -1);
|
||||
Pointeur_Instruction <= (others => '0');
|
||||
C <= Argument_nul;
|
||||
B <= Argument_nul;
|
||||
A <= Argument_nul;
|
||||
Instruction <= Instruction_nulle;
|
||||
else
|
||||
Tableau(4) <= Tableau(3);
|
||||
Tableau(3) <= Tableau(2);
|
||||
Tableau(2) <= Tableau(1);
|
||||
Tableau(1) <= -1;
|
||||
if (not bulles) then
|
||||
if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
|
||||
C <= Argument_nul;
|
||||
B <= Argument_nul;
|
||||
A <= Argument_nul;
|
||||
Instruction <= Instruction_nulle;
|
||||
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
|
||||
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
|
||||
C <= Argument_nul;
|
||||
B <= Argument_nul;
|
||||
A <= Argument_nul;
|
||||
Instruction <= Instruction_nulle;
|
||||
Pointeur_Instruction <= Adresse_Retour;
|
||||
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
|
||||
compteur <= compteur + 1;
|
||||
C <= Argument_nul;
|
||||
B <= Argument_nul;
|
||||
A <= Argument_nul;
|
||||
Instruction <= Instruction_nulle;
|
||||
if (compteur = 2) then
|
||||
if (Z = '1') then
|
||||
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
|
||||
else
|
||||
Pointeur_Instruction <= Pointeur_Instruction + 1;
|
||||
end if;
|
||||
compteur <= 0;
|
||||
end if;
|
||||
else
|
||||
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
|
||||
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
|
||||
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
|
||||
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
|
||||
if (Instructions_critiques_ecriture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') then
|
||||
Tableau(1) <= to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)));
|
||||
end if;
|
||||
Pointeur_Instruction <= Pointeur_Instruction + 1;
|
||||
end if;
|
||||
else
|
||||
C <= Argument_nul;
|
||||
B <= Argument_nul;
|
||||
A <= Argument_nul;
|
||||
Instruction <= Instruction_nulle;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Condition degueu -> Instruction qui lit dans B et B dans tableau ou instruction qui lit dans C et C dans tableau
|
||||
bulles <= ((Instructions_critiques_lecture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3)))) or ((Instructions_critiques_lecture_double(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))));
|
||||
R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
|
||||
'0';
|
||||
W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
|
||||
'0';
|
||||
Pointeur_instruction_next <= Pointeur_instruction + 1;
|
||||
end Behavioral;
|
||||
134
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd
Normal file
134
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18.04.2021 21:19:41
|
||||
-- Design Name:
|
||||
-- Module Name: Etage2_5_Registres - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Etage2_5_Registres is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Nb_registres : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end Etage2_5_Registres;
|
||||
|
||||
architecture Behavioral of Etage2_5_Registres is
|
||||
component BancRegistres is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Nb_regs : Natural);
|
||||
Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
W : in STD_LOGIC;
|
||||
DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
|
||||
end component;
|
||||
|
||||
component LC is
|
||||
Generic (Instruction_Vector_Size : Natural;
|
||||
Command_size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component MUX is
|
||||
Generic (Nb_bits : Natural;
|
||||
Instruction_Vector_Size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0";
|
||||
signal Sortie_BancRegistres : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
instance_LC : LC
|
||||
generic map (Instruction_Vector_Size => Instruction_bus_size,
|
||||
Command_size => 1,
|
||||
Bits_Controle => Bits_Controle_LC_5)
|
||||
port map ( Instruction => IN_5_Instruction,
|
||||
Commande => Commande_BancRegistres);
|
||||
|
||||
instance_MUX : MUX
|
||||
generic map (Nb_bits => Nb_bits,
|
||||
Instruction_Vector_Size => Instruction_bus_size,
|
||||
Bits_Controle => Bits_Controle_MUX_2)
|
||||
port map ( Instruction => IN_2_Instruction,
|
||||
IN1 => IN_2_B,
|
||||
IN2 => Sortie_BancRegistres,
|
||||
OUTPUT => intern_OUT_2_B);
|
||||
|
||||
instance_BancRegistres : BancRegistres
|
||||
generic map (Nb_bits => Nb_bits,
|
||||
Addr_size => Nb_bits,
|
||||
Nb_regs => Nb_registres)
|
||||
port map ( AddrA => IN_2_B,
|
||||
AddrB => IN_2_C,
|
||||
AddrW => IN_5_A,
|
||||
W => Commande_BancRegistres(0),
|
||||
DATA => IN_5_B,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
QA => Sortie_BancRegistres,
|
||||
QB => intern_OUT_2_C);
|
||||
|
||||
OUT_2_A <= (others => '0') when RST = '0' else
|
||||
IN_2_A;
|
||||
OUT_2_B <= (others => '0') when RST = '0' else
|
||||
intern_OUT_2_B;
|
||||
OUT_2_C <= (others => '0') when RST = '0' else
|
||||
intern_OUT_2_C;
|
||||
OUT_2_Instruction <= (others => '0') when RST = '0' else
|
||||
IN_2_Instruction;
|
||||
|
||||
end Behavioral;
|
||||
136
Processeur.srcs/sources_1/new/Etage3_Calcul.vhd
Normal file
136
Processeur.srcs/sources_1/new/Etage3_Calcul.vhd
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18.04.2021 21:19:41
|
||||
-- Design Name:
|
||||
-- Module Name: Etage3_Calcul - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Etage3_Calcul is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX : STD_LOGIC_VECTOR);
|
||||
Port ( RST : in STD_LOGIC;
|
||||
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end Etage3_Calcul;
|
||||
|
||||
architecture Structural of Etage3_Calcul is
|
||||
component ALU is
|
||||
Generic (Nb_bits : Natural);
|
||||
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
OP : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
component LC is
|
||||
Generic (Instruction_Vector_Size : Natural;
|
||||
Command_size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component MUX is
|
||||
Generic (Nb_bits : Natural;
|
||||
Instruction_Vector_Size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal OP_ALU : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
signal Sortie_ALU : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
|
||||
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal intern_N : STD_LOGIC := '0';
|
||||
signal intern_O : STD_LOGIC := '0';
|
||||
signal intern_Z : STD_LOGIC := '0';
|
||||
signal intern_C : STD_LOGIC := '0';
|
||||
|
||||
|
||||
begin
|
||||
instance_LC : LC
|
||||
generic map (Instruction_Vector_Size => Instruction_bus_size,
|
||||
Command_size => 3,
|
||||
Bits_Controle => Bits_Controle_LC)
|
||||
port map ( Instruction => IN_Instruction,
|
||||
Commande => OP_ALU);
|
||||
|
||||
instance_MUX : MUX
|
||||
generic map (Nb_bits => Nb_bits,
|
||||
Instruction_Vector_Size => Instruction_bus_size,
|
||||
Bits_Controle => Bits_Controle_MUX)
|
||||
port map ( Instruction => IN_Instruction,
|
||||
IN1 => IN_B,
|
||||
IN2 => Sortie_ALU,
|
||||
OUTPUT => intern_OUT_B);
|
||||
|
||||
instance_ALU : ALU
|
||||
generic map (Nb_bits => Nb_bits)
|
||||
port map (A => IN_B,
|
||||
B => IN_C,
|
||||
OP => OP_ALU,
|
||||
S => Sortie_ALU,
|
||||
N => intern_N,
|
||||
O => intern_O,
|
||||
Z => intern_Z,
|
||||
C => intern_C);
|
||||
|
||||
OUT_A <= (others => '0') when RST = '0' else
|
||||
IN_A;
|
||||
OUT_B <= (others => '0') when RST = '0' else
|
||||
intern_OUT_B;
|
||||
OUT_Instruction <= (others => '0') when RST = '0' else
|
||||
IN_Instruction;
|
||||
N <= '0' when RST = '0' else
|
||||
intern_N;
|
||||
O <= '0' when RST = '0' else
|
||||
intern_O;
|
||||
Z <= '0' when RST = '0' else
|
||||
intern_Z;
|
||||
C <= '0' when RST = '0' else
|
||||
intern_C;
|
||||
end Structural;
|
||||
131
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
Normal file
131
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18.04.2021 21:19:41
|
||||
-- Design Name:
|
||||
-- Module Name: Etage4_Memoire - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Etage4_Memoire is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Mem_size : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end Etage4_Memoire;
|
||||
|
||||
architecture Structural of Etage4_Memoire is
|
||||
component MemoireDonnees is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
RW : in STD_LOGIC;
|
||||
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
|
||||
end component;
|
||||
|
||||
component LC is
|
||||
Generic (Instruction_Vector_Size : Natural;
|
||||
Command_size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component MUX is
|
||||
Generic (Nb_bits : Natural;
|
||||
Instruction_Vector_Size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
|
||||
signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
instance_LC : LC
|
||||
generic map (Instruction_Vector_Size => Instruction_bus_size,
|
||||
Command_size => 1,
|
||||
Bits_Controle => Bits_Controle_LC)
|
||||
port map ( Instruction => IN_Instruction,
|
||||
Commande => Commande_MemoireDonnees);
|
||||
|
||||
instance_MUX_IN : MUX
|
||||
generic map (Nb_bits => Nb_bits,
|
||||
Instruction_Vector_Size => Instruction_bus_size,
|
||||
Bits_Controle => Bits_Controle_MUX_IN)
|
||||
port map ( Instruction => IN_Instruction,
|
||||
IN1 => IN_A,
|
||||
IN2 => IN_B,
|
||||
OUTPUT => Addr_MemoireDonnees);
|
||||
|
||||
instance_MUX_OUT : MUX
|
||||
generic map (Nb_bits => Nb_bits,
|
||||
Instruction_Vector_Size => Instruction_bus_size,
|
||||
Bits_Controle => Bits_Controle_MUX_OUT)
|
||||
port map ( Instruction => IN_Instruction,
|
||||
IN1 => Sortie_MemoireDonnees,
|
||||
IN2 => IN_B,
|
||||
OUTPUT => intern_OUT_B);
|
||||
|
||||
instance_MemoireDonnees : MemoireDonnees
|
||||
generic map (Nb_bits => Nb_bits,
|
||||
Addr_size => Nb_bits,
|
||||
Mem_size => Mem_size)
|
||||
port map ( Addr => Addr_MemoireDonnees,
|
||||
RW => Commande_MemoireDonnees(0),
|
||||
D_IN => IN_B,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
D_OUT => Sortie_MemoireDonnees);
|
||||
|
||||
OUT_A <= (others => '0') when RST = '0' else
|
||||
IN_A;
|
||||
OUT_B <= (others => '0') when RST = '0' else
|
||||
intern_OUT_B;
|
||||
OUT_Instruction <= (others => '0') when RST = '0' else
|
||||
IN_Instruction;
|
||||
|
||||
end Structural;
|
||||
45
Processeur.srcs/sources_1/new/LC.vhd
Normal file
45
Processeur.srcs/sources_1/new/LC.vhd
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17.04.2021 21:49:57
|
||||
-- Design Name:
|
||||
-- Module Name: LC - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity LC is
|
||||
Generic (Instruction_Vector_Size : Natural;
|
||||
Command_size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
|
||||
end LC;
|
||||
|
||||
architecture Behavioral of LC is
|
||||
begin
|
||||
Commande <= Bits_Controle (((1 + to_integer(unsigned(Instruction))) * Command_size - 1) downto (Command_size * to_integer(unsigned(Instruction))));
|
||||
end Behavioral;
|
||||
48
Processeur.srcs/sources_1/new/MUX.vhd
Normal file
48
Processeur.srcs/sources_1/new/MUX.vhd
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17.04.2021 21:49:57
|
||||
-- Design Name:
|
||||
-- Module Name: MUX - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity MUX is
|
||||
Generic (Nb_bits : Natural;
|
||||
Instruction_Vector_Size : Natural;
|
||||
Bits_Controle : STD_LOGIC_VECTOR);
|
||||
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
|
||||
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
|
||||
end MUX;
|
||||
|
||||
architecture Behavioral of MUX is
|
||||
begin
|
||||
OUTPUT <= IN1 when (Bits_Controle(to_integer(unsigned(Instruction))) = '1') else
|
||||
IN2;
|
||||
end Behavioral;
|
||||
77
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
Normal file
77
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 14:35:04
|
||||
-- Design Name:
|
||||
-- Module Name: MemoireAdressesRetour - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity MemoireAdressesRetour is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( R : in STD_LOGIC;
|
||||
W : in STD_LOGIC;
|
||||
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
|
||||
E : out STD_LOGIC;
|
||||
F : out STD_LOGIC);
|
||||
end MemoireAdressesRetour;
|
||||
|
||||
architecture Behavioral of MemoireAdressesRetour is
|
||||
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
|
||||
signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
|
||||
constant EMPTY : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
|
||||
constant FULL : STD_LOGIC_VECTOR (Addr_size downto 0) := (Addr_size => '1', others => '0');
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until CLK'event and CLK = '1';
|
||||
if (RST = '0' ) then
|
||||
MEMORY <= (others => '0');
|
||||
Addr <= (others => '0');
|
||||
else
|
||||
if (W = '1') then
|
||||
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
|
||||
Addr <= Addr + 1;
|
||||
elsif (R = '1') then
|
||||
Addr <= Addr - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
E <= '1' when Addr = EMPTY else
|
||||
'0';
|
||||
F <= '1' when Addr = FULL else
|
||||
'0';
|
||||
|
||||
D_OUT <= (others => '0') when Addr = EMPTY else
|
||||
MEMORY (to_integer(unsigned(Addr)) * Nb_bits - 1 downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
|
||||
end Behavioral;
|
||||
62
Processeur.srcs/sources_1/new/MemoireDonnees.vhd
Normal file
62
Processeur.srcs/sources_1/new/MemoireDonnees.vhd
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 14:35:04
|
||||
-- Design Name:
|
||||
-- Module Name: MemoireDonnees - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity MemoireDonnees is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
RW : in STD_LOGIC;
|
||||
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
RST : in STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
|
||||
end MemoireDonnees;
|
||||
|
||||
architecture Behavioral of MemoireDonnees is
|
||||
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until CLK'event and CLK = '1';
|
||||
if (RST = '0') then
|
||||
MEMORY <= (others => '0');
|
||||
else
|
||||
if (RW = '0') then
|
||||
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
|
||||
else
|
||||
D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
46
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
Normal file
46
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16.04.2021 14:35:04
|
||||
-- Design Name:
|
||||
-- Module Name: MemoireInstructions - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity MemoireInstructions is
|
||||
Generic (Nb_bits : Natural;
|
||||
Addr_size : Natural;
|
||||
Mem_size : Natural);
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
|
||||
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
|
||||
end MemoireInstructions;
|
||||
|
||||
architecture Behavioral of MemoireInstructions is
|
||||
signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"f000000"&x"7040001"&x"6030001"&x"5020001"&x"9010500"&x"9000300"&x"d010000"&x"2000000"&x"e030000";
|
||||
begin
|
||||
D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
|
||||
end Behavioral;
|
||||
290
Processeur.srcs/sources_1/new/Pipeline.vhd
Normal file
290
Processeur.srcs/sources_1/new/Pipeline.vhd
Normal file
|
|
@ -0,0 +1,290 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19.04.2021 16:57:41
|
||||
-- Design Name:
|
||||
-- Module Name: Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Pipeline is
|
||||
Generic (Nb_bits : Natural := 8;
|
||||
Instruction_En_Memoire_Size : Natural := 28;
|
||||
Addr_Memoire_Instruction_Size : Natural := 3;
|
||||
Memoire_Instruction_Size : Natural := 8;
|
||||
Instruction_Bus_Size : Natural := 4;
|
||||
Nb_Instructions : Natural := 16;
|
||||
Nb_Registres : Natural := 16;
|
||||
Memoire_Size : Natural := 8;
|
||||
Memoire_Adresses_Retour_Size : Natural := 16;
|
||||
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
|
||||
Port (CLK : STD_LOGIC;
|
||||
RST : STD_LOGIC);
|
||||
end Pipeline;
|
||||
|
||||
architecture Behavioral of Pipeline is
|
||||
|
||||
component Etage1_LectureInstruction is
|
||||
Generic (Instruction_size_in_memory : Natural;
|
||||
Addr_size_mem_instruction : Natural;
|
||||
Mem_instruction_size : Natural;
|
||||
Nb_bits : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Nb_registres : Natural;
|
||||
Mem_adresse_retour_size : Natural;
|
||||
Adresse_size_mem_adresse_retour : Natural;
|
||||
Instructions_critiques_lecture : STD_LOGIC_VECTOR;
|
||||
Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
|
||||
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_JMP : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_CALL : STD_LOGIC_VECTOR;
|
||||
Code_Instruction_RET : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
Z : in STD_LOGIC;
|
||||
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component Etage2_5_Registres is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Nb_registres : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
component Etage3_Calcul is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX : STD_LOGIC_VECTOR);
|
||||
Port ( RST : in STD_LOGIC;
|
||||
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
component Etage4_Memoire is
|
||||
Generic ( Nb_bits : Natural;
|
||||
Mem_size : Natural;
|
||||
Instruction_bus_size : Natural;
|
||||
Bits_Controle_LC : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
|
||||
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
|
||||
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
|
||||
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
|
||||
end component;
|
||||
|
||||
signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
|
||||
signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
|
||||
signal N : STD_LOGIC := '0';
|
||||
signal Z : STD_LOGIC := '0';
|
||||
signal O : STD_LOGIC := '0';
|
||||
signal C : STD_LOGIC := '0';
|
||||
|
||||
constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1101011000000001";
|
||||
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
|
||||
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111100000001";
|
||||
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111011111111111";
|
||||
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111101111111111";
|
||||
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000010000000000";
|
||||
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
|
||||
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1100";
|
||||
constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1101";
|
||||
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1110";
|
||||
constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1111";
|
||||
|
||||
constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000100111111110";
|
||||
constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000000011111110";
|
||||
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
|
||||
begin
|
||||
instance_Etage1 : Etage1_LectureInstruction
|
||||
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
|
||||
Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
|
||||
Mem_instruction_size => Memoire_Instruction_Size,
|
||||
Nb_bits => Nb_bits,
|
||||
Instruction_bus_size => Instruction_Bus_Size,
|
||||
Nb_registres => Nb_Registres,
|
||||
Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
|
||||
Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
|
||||
Instructions_critiques_lecture => Instructions_critiques_lecture,
|
||||
Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
|
||||
Instructions_critiques_ecriture => Instructions_critiques_ecriture,
|
||||
Code_Instruction_JMP => Code_Instruction_JMP,
|
||||
Code_Instruction_JMZ => Code_Instruction_JMZ,
|
||||
Code_Instruction_CALL => Code_Instruction_CALL,
|
||||
Code_Instruction_RET => Code_Instruction_RET
|
||||
)
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
Z => Z,
|
||||
A => A_from_1,
|
||||
B => B_from_1,
|
||||
C => C_from_1,
|
||||
Instruction => Instruction_from_1
|
||||
);
|
||||
|
||||
instance_Etage2_5 : Etage2_5_Registres
|
||||
generic map( Nb_bits => Nb_bits,
|
||||
Nb_Registres => Nb_Registres,
|
||||
Instruction_bus_size => Instruction_Bus_Size,
|
||||
Bits_Controle_LC_5 => Bits_Controle_LC_5,
|
||||
Bits_Controle_MUX_2 => Bits_Controle_MUX_2
|
||||
)
|
||||
port map( CLK => CLK,
|
||||
RST => RST,
|
||||
IN_2_A => A_to_2,
|
||||
IN_2_B => B_to_2,
|
||||
IN_2_C => C_to_2,
|
||||
IN_2_Instruction => Instruction_to_2,
|
||||
OUT_2_A => A_from_2,
|
||||
OUT_2_B => B_from_2,
|
||||
OUT_2_C => C_from_2,
|
||||
OUT_2_Instruction => Instruction_from_2,
|
||||
IN_5_A => A_to_5,
|
||||
IN_5_B => B_to_5,
|
||||
IN_5_Instruction => Instruction_to_5
|
||||
);
|
||||
|
||||
instance_Etage3 : Etage3_Calcul
|
||||
generic map( Nb_bits => Nb_bits,
|
||||
Instruction_bus_size => Instruction_Bus_Size,
|
||||
Bits_Controle_LC => Bits_Controle_LC_3,
|
||||
Bits_Controle_MUX => Bits_Controle_MUX_3
|
||||
)
|
||||
port map( RST => RST,
|
||||
IN_A => A_to_3,
|
||||
IN_B => B_to_3,
|
||||
IN_C => C_to_3,
|
||||
IN_Instruction => Instruction_to_3,
|
||||
OUT_A => A_from_3,
|
||||
OUT_B => B_from_3,
|
||||
OUT_Instruction => Instruction_from_3,
|
||||
N => N,
|
||||
O => O,
|
||||
Z => Z,
|
||||
C => C
|
||||
);
|
||||
|
||||
instance_Etage4 : Etage4_Memoire
|
||||
generic map( Nb_bits => Nb_bits,
|
||||
Mem_size => Memoire_Size,
|
||||
Instruction_bus_size => Instruction_Bus_Size,
|
||||
Bits_Controle_LC => Bits_Controle_LC_4,
|
||||
Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
|
||||
Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT
|
||||
)
|
||||
port map( CLK => CLK,
|
||||
RST => RST,
|
||||
IN_A => A_to_4,
|
||||
IN_B => B_to_4,
|
||||
IN_Instruction => Instruction_to_4,
|
||||
OUT_A => A_from_4,
|
||||
OUT_B => B_from_4,
|
||||
OUT_Instruction => Instruction_from_4
|
||||
);
|
||||
|
||||
process
|
||||
begin
|
||||
wait until CLK'event and CLK = '1';
|
||||
A_to_2 <= A_from_1;
|
||||
B_to_2 <= B_from_1;
|
||||
C_to_2 <= C_from_1;
|
||||
Instruction_to_2 <= Instruction_from_1;
|
||||
|
||||
A_to_3 <= A_from_2;
|
||||
B_to_3 <= B_from_2;
|
||||
C_to_3 <= C_from_2;
|
||||
Instruction_to_3 <= Instruction_from_2;
|
||||
|
||||
A_to_4 <= A_from_3;
|
||||
B_to_4 <= B_from_3;
|
||||
Instruction_to_4 <= Instruction_from_3;
|
||||
|
||||
A_to_5 <= A_from_4;
|
||||
B_to_5 <= B_from_4;
|
||||
Instruction_to_5 <= Instruction_from_4;
|
||||
end process;
|
||||
end Behavioral;
|
||||
67
Processeur.srcs/sources_1/new/System.vhd
Normal file
67
Processeur.srcs/sources_1/new/System.vhd
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13.04.2021 10:19:15
|
||||
-- Design Name:
|
||||
-- Module Name: System - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity System is
|
||||
Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
flag : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
sw : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
btnC : in STD_LOGIC;
|
||||
btnL : in STD_LOGIC;
|
||||
btnR : in STD_LOGIC);
|
||||
end System;
|
||||
|
||||
architecture Structural of System is
|
||||
component ALU
|
||||
Generic (Nb_bits : Natural);
|
||||
Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
OP : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
signal aux: STD_LOGIC_VECTOR (1 downto 0);
|
||||
signal aux4: STD_LOGIC;
|
||||
signal aux5: STD_LOGIC;
|
||||
signal aux6: STD_LOGIC;
|
||||
signal aux7: STD_LOGIC;
|
||||
begin
|
||||
aux <= "01" when btnC = '1' else
|
||||
"10" when btnR = '1' else
|
||||
"11" when btnL = '1' else
|
||||
"00";
|
||||
flag <= aux4 & aux5 & aux6 & aux7;
|
||||
My_ALU: ALU generic map (Nb_bits => 8) port map(sw (15 downto 8), sw (7 downto 0), aux, led, aux4, aux5, aux6, aux7);
|
||||
end Structural;
|
||||
295
Processeur.xpr
Normal file
295
Processeur.xpr
Normal file
|
|
@ -0,0 +1,295 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2016.4 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Processeur/Processeur.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PPRDIR/Processeur.ip_user_files"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PPRDIR/Processeur.ip_user_files/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="DSANumComputeUnits" Val="16"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="145"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="64"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/System.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/MemoireAdressesRetour.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/MemoireInstructions.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/MemoireDonnees.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/MUX.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/LC.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="System"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1614979917"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sim_1/new/TestMemoireDonnees.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/TestMemoireAdressesRetour.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/TestBancRegistres.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/TestALU.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/TestMemoireInstructions.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_LC.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_MUX.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_Etape1_LectureInstruction.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_Etage3_Calcul.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_Etage4_Memoire.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_Etage2_5_Registres.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/Test_Pipeline.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Test_Pipeline"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
</Project>
|
||||
222
vivado.jou
222
vivado.jou
|
|
@ -2,73 +2,159 @@
|
|||
# Vivado v2016.4 (64-bit)
|
||||
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
|
||||
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
|
||||
# Start of session at: Wed Apr 14 08:09:08 2021
|
||||
# Process ID: 4032
|
||||
# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6828 C:\Users\Hp\Documents\Compteur8BitsBasys3\Compteur8BitsBasys3.xpr
|
||||
# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
|
||||
# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
|
||||
# Start of session at: Mon Apr 19 10:14:33 2021
|
||||
# Process ID: 6416
|
||||
# Current directory: C:/Users/Hp/Documents/Processeur
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16404 C:\Users\Hp\Documents\Processeur\Processeur.xpr
|
||||
# Log file: C:/Users/Hp/Documents/Processeur/vivado.log
|
||||
# Journal file: C:/Users/Hp/Documents/Processeur\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
remove_files -fileset sim_1 C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
|
||||
file delete -force C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
|
||||
reset_run impl_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 2
|
||||
wait_on_run impl_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 2
|
||||
wait_on_run impl_1
|
||||
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 2
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 2
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 2
|
||||
wait_on_run impl_1
|
||||
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
||||
open_project C:/Users/Hp/Documents/Processeur/Processeur.xpr
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
add_bp {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} 44
|
||||
remove_bps -file {C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/LC.vhd} -line 44
|
||||
close_sim
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_LC.tcl
|
||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||||
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd w ]
|
||||
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
|
||||
set_property top Test_Etage3_Calcul [get_filesets sim_1]
|
||||
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
source Test_Etage3_Calcul.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage3_Calcul.tcl
|
||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||||
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd w ]
|
||||
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
|
||||
set_property top Test_Etage4_Memoire [get_filesets sim_1]
|
||||
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
source Test_Etage4_Memoire.tcl
|
||||
set_property top Test_Etage3_Calcul [get_filesets sim_1]
|
||||
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||
current_sim simulation_10
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage3_Calcul.tcl
|
||||
set_property top Test_Etage4_Memoire [get_filesets sim_1]
|
||||
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||
current_sim simulation_11
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage4_Memoire.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage4_Memoire.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage4_Memoire.tcl
|
||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||||
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd w ]
|
||||
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
|
||||
set_property top Test_Etage2_5_Registres [get_filesets sim_1]
|
||||
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||
launch_simulation
|
||||
source Test_Etage2_5_Registres.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage2_5_Registres.tcl
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Etage2_5_Registres.tcl
|
||||
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd w ]
|
||||
add_files C:/Users/Hp/Documents/Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd
|
||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||||
close [ open C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd w ]
|
||||
add_files -fileset sim_1 C:/Users/Hp/Documents/Processeur/Processeur.srcs/sim_1/new/Test_Pipeline.vhd
|
||||
set_property top Test_Pipeline [get_filesets sim_1]
|
||||
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
add_wave {{/Test_Pipeline/instance/Instruction_1_to_2}} {{/Test_Pipeline/instance/Instruction_2_to_3}} {{/Test_Pipeline/instance/Instruction_3_to_4}} {{/Test_Pipeline/instance/Instruction_4_to_5}}
|
||||
run all
|
||||
run 10 us
|
||||
run 10 us
|
||||
restart
|
||||
run 10 us
|
||||
restart
|
||||
run 10 us
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
close_sim
|
||||
launch_simulation
|
||||
current_sim simulation_18
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
save_wave_config {C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg}
|
||||
add_files -fileset sim_1 -norecurse C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
|
||||
set_property xsim.view C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg [get_filesets sim_1]
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
restart
|
||||
run 10 us
|
||||
restart
|
||||
run 10 us
|
||||
close_sim
|
||||
launch_simulation
|
||||
current_sim simulation_18
|
||||
launch_simulation
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
close_sim
|
||||
launch_simulation
|
||||
source Test_Pipeline.tcl
|
||||
restart
|
||||
run 10 us
|
||||
|
|
|
|||
4212
vivado.log
4212
vivado.log
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue