Browse Source

Processeur 16 Instructions : NOP, ADD, SUB, MUL, DIV, INF, SUP, EQU, AFC, CPY, LOAD, JMP, JMZ, STORE, CALL, RET (ordre non garanti)

Paul Faure 4 months ago
parent
commit
24bb67c7e3
29 changed files with 7321 additions and 216 deletions
  1. 299
    0
      Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
  2. 84
    0
      Processeur.srcs/sim_1/new/TestALU.vhd
  3. 104
    0
      Processeur.srcs/sim_1/new/TestBancRegistres.vhd
  4. 99
    0
      Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd
  5. 93
    0
      Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd
  6. 67
    0
      Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd
  7. 121
    0
      Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd
  8. 105
    0
      Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd
  9. 105
    0
      Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
  10. 118
    0
      Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd
  11. 66
    0
      Processeur.srcs/sim_1/new/Test_LC.vhd
  12. 74
    0
      Processeur.srcs/sim_1/new/Test_MUX.vhd
  13. 80
    0
      Processeur.srcs/sim_1/new/Test_Pipeline.vhd
  14. 85
    0
      Processeur.srcs/sources_1/new/ALU.vhd
  15. 68
    0
      Processeur.srcs/sources_1/new/BancRegistres.vhd
  16. 196
    0
      Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd
  17. 134
    0
      Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd
  18. 136
    0
      Processeur.srcs/sources_1/new/Etage3_Calcul.vhd
  19. 131
    0
      Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
  20. 45
    0
      Processeur.srcs/sources_1/new/LC.vhd
  21. 48
    0
      Processeur.srcs/sources_1/new/MUX.vhd
  22. 77
    0
      Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
  23. 62
    0
      Processeur.srcs/sources_1/new/MemoireDonnees.vhd
  24. 46
    0
      Processeur.srcs/sources_1/new/MemoireInstructions.vhd
  25. 290
    0
      Processeur.srcs/sources_1/new/Pipeline.vhd
  26. 67
    0
      Processeur.srcs/sources_1/new/System.vhd
  27. 295
    0
      Processeur.xpr
  28. 154
    68
      vivado.jou
  29. 4072
    148
      vivado.log

+ 299
- 0
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -0,0 +1,299 @@
1
+## This file is a general .xdc for the Basys3 rev B board
2
+## To use it in a project:
3
+## - uncomment the lines corresponding to used pins
4
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
5
+
6
+## Clock signal
7
+#set_property PACKAGE_PIN W5 [get_ports clk]
8
+	#set_property IOSTANDARD LVCMOS33 [get_ports clk]
9
+	#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
10
+
11
+## Switches
12
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
13
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
14
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
15
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
16
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
17
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
18
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
19
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
20
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
21
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
22
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
23
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
24
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
25
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
26
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
27
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
28
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
31
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
32
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
33
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
34
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
35
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
36
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
37
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
38
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
39
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
40
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
41
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
42
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
43
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
44
+
45
+
46
+## LEDs
47
+set_property PACKAGE_PIN U16 [get_ports {led[0]}]
48
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
49
+set_property PACKAGE_PIN E19 [get_ports {led[1]}]
50
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
51
+set_property PACKAGE_PIN U19 [get_ports {led[2]}]
52
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
53
+set_property PACKAGE_PIN V19 [get_ports {led[3]}]
54
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
55
+set_property PACKAGE_PIN W18 [get_ports {led[4]}]
56
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
57
+set_property PACKAGE_PIN U15 [get_ports {led[5]}]
58
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
59
+set_property PACKAGE_PIN U14 [get_ports {led[6]}]
60
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
61
+set_property PACKAGE_PIN V14 [get_ports {led[7]}]
62
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
63
+#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
64
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
65
+#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
66
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
67
+#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
68
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69
+#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
70
+	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
71
+set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
72
+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[0]}]
73
+set_property PACKAGE_PIN N3 [get_ports {flag[1]}]
74
+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[1]}]
75
+set_property PACKAGE_PIN P1 [get_ports {flag[2]}]
76
+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[2]}]
77
+set_property PACKAGE_PIN L1 [get_ports {flag[3]}]
78
+	set_property IOSTANDARD LVCMOS33 [get_ports {flag[3]}]
79
+
80
+
81
+##7 segment display
82
+#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
83
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
84
+#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
85
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
86
+#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
87
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
88
+#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
89
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
90
+#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
91
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
92
+#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
93
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
94
+#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
95
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
96
+
97
+#set_property PACKAGE_PIN V7 [get_ports dp]
98
+	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
99
+
100
+#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
101
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
102
+#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
103
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
104
+#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
105
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
106
+#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
107
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
108
+
109
+
110
+##Buttons
111
+set_property PACKAGE_PIN U18 [get_ports btnC]
112
+	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
113
+#set_property PACKAGE_PIN T18 [get_ports btnU]
114
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115
+set_property PACKAGE_PIN W19 [get_ports btnL]
116
+	set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
+set_property PACKAGE_PIN T17 [get_ports btnR]
118
+	set_property IOSTANDARD LVCMOS33 [get_ports btnR]
119
+#set_property PACKAGE_PIN U17 [get_ports btnD]
120
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
121
+
122
+
123
+
124
+##Pmod Header JA
125
+##Sch name = JA1
126
+#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
127
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
128
+##Sch name = JA2
129
+#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
130
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
131
+##Sch name = JA3
132
+#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
133
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
134
+##Sch name = JA4
135
+#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
136
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
137
+##Sch name = JA7
138
+#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
139
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
140
+##Sch name = JA8
141
+#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
142
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
143
+##Sch name = JA9
144
+#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
145
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
146
+##Sch name = JA10
147
+#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
148
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
149
+
150
+
151
+
152
+##Pmod Header JB
153
+##Sch name = JB1
154
+#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
155
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
156
+##Sch name = JB2
157
+#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
158
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
159
+##Sch name = JB3
160
+#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
161
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
162
+##Sch name = JB4
163
+#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
164
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
165
+##Sch name = JB7
166
+#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
167
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
168
+##Sch name = JB8
169
+#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
170
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
171
+##Sch name = JB9
172
+#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
173
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
174
+##Sch name = JB10
175
+#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
176
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
177
+
178
+
179
+
180
+##Pmod Header JC
181
+##Sch name = JC1
182
+#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
183
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
184
+##Sch name = JC2
185
+#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
186
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
187
+##Sch name = JC3
188
+#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
189
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
190
+##Sch name = JC4
191
+#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
192
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
193
+##Sch name = JC7
194
+#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
195
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
196
+##Sch name = JC8
197
+#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
198
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
199
+##Sch name = JC9
200
+#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
201
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
202
+##Sch name = JC10
203
+#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
204
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
205
+
206
+
207
+##Pmod Header JXADC
208
+##Sch name = XA1_P
209
+#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
210
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
211
+##Sch name = XA2_P
212
+#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
213
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
214
+##Sch name = XA3_P
215
+#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
216
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
217
+##Sch name = XA4_P
218
+#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
219
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
220
+##Sch name = XA1_N
221
+#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
222
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
223
+##Sch name = XA2_N
224
+#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
225
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
226
+##Sch name = XA3_N
227
+#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
228
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
229
+##Sch name = XA4_N
230
+#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
231
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
232
+
233
+
234
+
235
+##VGA Connector
236
+#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
237
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
238
+#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
239
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
240
+#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
241
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
242
+#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
243
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
244
+#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
245
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
246
+#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
247
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
248
+#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
249
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
250
+#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
251
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
252
+#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
253
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
254
+#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
255
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
256
+#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
257
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
258
+#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
259
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
260
+#set_property PACKAGE_PIN P19 [get_ports Hsync]
261
+	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
262
+#set_property PACKAGE_PIN R19 [get_ports Vsync]
263
+	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
264
+
265
+
266
+##USB-RS232 Interface
267
+#set_property PACKAGE_PIN B18 [get_ports RsRx]
268
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
269
+#set_property PACKAGE_PIN A18 [get_ports RsTx]
270
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
271
+
272
+
273
+##USB HID (PS/2)
274
+#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
275
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
276
+	#set_property PULLUP true [get_ports PS2Clk]
277
+#set_property PACKAGE_PIN B17 [get_ports PS2Data]
278
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
279
+	#set_property PULLUP true [get_ports PS2Data]
280
+
281
+
282
+##Quad SPI Flash
283
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
284
+##STARTUPE2 primitive.
285
+#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
286
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
287
+#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
288
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
289
+#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
290
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
291
+#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
292
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
293
+#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
294
+	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
295
+
296
+
297
+## Configuration options, can be used for all designs
298
+set_property CONFIG_VOLTAGE 3.3 [current_design]
299
+set_property CFGBVS VCCO [current_design]

+ 84
- 0
Processeur.srcs/sim_1/new/TestALU.vhd View File

@@ -0,0 +1,84 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 21:25:53
6
+-- Design Name: 
7
+-- Module Name: TestALU - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestALU is
35
+--  Port ( );
36
+end TestALU;
37
+
38
+architecture Behavioral of TestALU is
39
+    component   ALU is
40
+        Generic (Nb_bits : Natural);
41
+        Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
42
+              B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
43
+              OP : in STD_LOGIC_VECTOR (1 downto 0);
44
+              S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
45
+              N : out STD_LOGIC;
46
+              O : out STD_LOGIC;
47
+              Z : out STD_LOGIC;
48
+              C : out STD_LOGIC);
49
+    end component;
50
+    
51
+    signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
52
+    signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
53
+    signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
54
+    signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
55
+    signal my_N : STD_LOGIC := '0';
56
+    signal my_O : STD_LOGIC := '0';
57
+    signal my_Z : STD_LOGIC := '0';
58
+    signal my_C : STD_LOGIC := '0';
59
+    
60
+begin
61
+
62
+    instance : ALU
63
+    generic map (Nb_bits => 16)
64
+    port map (
65
+        A => my_A,
66
+        B => my_B,
67
+        OP => my_OP,
68
+        S => my_S,
69
+        N => my_N,
70
+        O => my_O,
71
+        Z => my_Z,
72
+        C => my_C
73
+    );
74
+    
75
+    process 
76
+    begin
77
+        my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
78
+        my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
79
+        my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
80
+        
81
+        wait;
82
+    end process;    
83
+end Behavioral;
84
+

+ 104
- 0
Processeur.srcs/sim_1/new/TestBancRegistres.vhd View File

@@ -0,0 +1,104 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestBancRegistres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestBancRegistres is
35
+--  Port ( );
36
+end TestBancRegistres;
37
+
38
+architecture Behavioral of TestBancRegistres is
39
+    component BancRegistres
40
+        Generic (Nb_bits : Natural;
41
+                 Addr_size : Natural;
42
+                 Nb_regs : Natural);
43
+        Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
44
+               AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
45
+               AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
46
+               W : in STD_LOGIC;
47
+               DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
+               RST : in STD_LOGIC;
49
+               CLK : in STD_LOGIC;
50
+               QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
51
+               QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
52
+    end component;
53
+    
54
+    signal my_AddrA : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
55
+    signal my_AddrB : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
56
+    signal my_AddrW : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
57
+    signal my_W : STD_LOGIC := '0';
58
+    signal my_DATA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
59
+    signal my_RST : STD_LOGIC := '0';
60
+    signal my_CLK : STD_LOGIC := '0';
61
+    signal my_QA : STD_LOGIC_VECTOR (7 downto 0);
62
+    signal my_QB : STD_LOGIC_VECTOR (7 downto 0);
63
+    
64
+    constant CLK_period : time := 10 ns;
65
+    
66
+begin
67
+
68
+    instance : BancRegistres
69
+    generic map (Nb_bits => 8,
70
+                 Addr_size => 2,
71
+                 Nb_regs => 4
72
+    )
73
+    port map (
74
+        AddrA => my_AddrA,
75
+        AddrB => my_AddrB,
76
+        AddrW => my_AddrW,
77
+        W => my_W,
78
+        DATA => my_DATA,
79
+        RST => my_RST,
80
+        CLK => my_CLK,
81
+        QA => my_QA,
82
+        QB => my_QB
83
+    );
84
+			
85
+    CLK_process :process
86
+    begin
87
+        my_CLK <= '0';
88
+        wait for CLK_period/2;
89
+        my_CLK <= '1';
90
+        wait for CLK_period/2;
91
+    end process;
92
+    
93
+    process 
94
+    begin
95
+        my_RST <= '1' after 0 ns, '0' after 100 ns;
96
+        my_AddrA <= "11" after 20 ns, "00" after 50 ns;
97
+        my_AddrB <= "11" after 30 ns;
98
+        my_AddrW <= "11" after 10 ns, "00" after 50 ns;
99
+        my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 60 ns, '1' after 110 ns;
100
+        my_DATA <= "01010101" after 10 ns, "11111111" after 50 ns;
101
+        
102
+        wait;
103
+    end process;    
104
+end Behavioral;

+ 99
- 0
Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd View File

@@ -0,0 +1,99 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestMemoireAdressesRetour - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestMemoireAdressesRetour is
35
+--  Port ( );
36
+end TestMemoireAdressesRetour;
37
+
38
+architecture Behavioral of TestMemoireAdressesRetour is
39
+    component MemoireAdressesRetour is
40
+    Generic (Nb_bits : Natural;
41
+             Addr_size : Natural;
42
+             Mem_size : Natural);
43
+    Port ( R : in STD_LOGIC;
44
+           W : in STD_LOGIC;
45
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
46
+           RST : in STD_LOGIC;
47
+           CLK : in STD_LOGIC;
48
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
49
+           E : out STD_LOGIC;
50
+           F : out STD_LOGIC);
51
+    end component;
52
+    
53
+    signal my_R : STD_LOGIC := '0';
54
+    signal my_W : STD_LOGIC := '0';
55
+    signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
56
+    signal my_RST : STD_LOGIC := '0';
57
+    signal my_CLK : STD_LOGIC := '0';
58
+    signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
59
+    signal my_E : STD_LOGIC;
60
+    signal my_F : STD_LOGIC;
61
+    
62
+    constant CLK_period : time := 10 ns;
63
+    
64
+begin
65
+
66
+    instance : MemoireAdressesRetour
67
+    generic map (Nb_bits => 8,
68
+                 Addr_size => 2,
69
+                 Mem_size => 4
70
+    )
71
+    port map (
72
+        R => my_R,
73
+        W => my_W,
74
+        D_IN => my_D_IN,
75
+        RST => my_RST,
76
+        CLK => my_CLK,
77
+        D_OUT => my_D_OUT,
78
+        E => my_E,
79
+        F => my_F
80
+    );
81
+			
82
+    CLK_process :process
83
+    begin
84
+        my_CLK <= '0';
85
+        wait for CLK_period/2;
86
+        my_CLK <= '1';
87
+        wait for CLK_period/2;
88
+    end process;
89
+    
90
+    process 
91
+    begin
92
+        my_RST <= '1' after 0 ns, '0' after 100 ns;
93
+        my_R <= '1' after 20 ns, '0' after 30 ns;
94
+        my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 90 ns, '0' after 110 ns;
95
+        my_D_IN <= "01010101" after 10 ns, "11100111" after 30 ns, "11111111" after 50 ns, "11111110" after 60 ns, "11111101" after 70 ns, "11111100" after 80 ns;
96
+        
97
+        wait;
98
+    end process;    
99
+end Behavioral;

+ 93
- 0
Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd View File

@@ -0,0 +1,93 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestMemoireDonnees - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestMemoireDonnees is
35
+--  Port ( );
36
+end TestMemoireDonnees;
37
+
38
+architecture Behavioral of TestMemoireDonnees is
39
+    component  MemoireDonnees is
40
+       Generic (Nb_bits : Natural;
41
+                Addr_size : Natural;
42
+                Mem_size : Natural);
43
+       Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
44
+              RW : in STD_LOGIC;
45
+              D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
46
+              RST : in STD_LOGIC;
47
+              CLK : in STD_LOGIC;
48
+              D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
49
+    end component;
50
+    
51
+    signal my_Addr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
52
+    signal my_RW : STD_LOGIC := '1';
53
+    signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
54
+    signal my_RST : STD_LOGIC := '0';
55
+    signal my_CLK : STD_LOGIC := '0';
56
+    signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
57
+    
58
+    constant CLK_period : time := 10 ns;
59
+    
60
+begin
61
+
62
+    instance : MemoireDonnees
63
+    generic map (Nb_bits => 8,
64
+                 Addr_size => 2,
65
+                 Mem_size => 4
66
+    )
67
+    port map (
68
+        Addr => my_Addr,
69
+        RW => my_RW,
70
+        D_IN => my_D_IN,
71
+        RST => my_RST,
72
+        CLK => my_CLK,
73
+        D_OUT => my_D_OUT
74
+    );
75
+			
76
+    CLK_process :process
77
+    begin
78
+        my_CLK <= '0';
79
+        wait for CLK_period/2;
80
+        my_CLK <= '1';
81
+        wait for CLK_period/2;
82
+    end process;
83
+    
84
+    process 
85
+    begin
86
+        my_RST <= '1' after 0 ns, '0' after 100 ns;
87
+        my_RW <= '1' after 0 ns, '0' after 10 ns, '1' after 30 ns;
88
+        my_Addr <= "01" after 10 ns, "10" after 20 ns, "11" after 40 ns, "01" after 70 ns;
89
+        my_D_IN <= "01010101" after 10 ns, "11100111" after 20 ns, "11111111" after 50 ns;
90
+        
91
+        wait;
92
+    end process;    
93
+end Behavioral;

+ 67
- 0
Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd View File

@@ -0,0 +1,67 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 12:58:02
6
+-- Design Name: 
7
+-- Module Name: TestMemoireInstructions - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity TestMemoireInstructions is
35
+--  Port ( );
36
+end TestMemoireInstructions;
37
+
38
+architecture Behavioral of TestMemoireInstructions is
39
+    component MemoireInstructions is
40
+    Generic (Nb_bits : Natural;
41
+             Addr_size : Natural;
42
+             Mem_size : Natural);
43
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
44
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
45
+    end component;
46
+    
47
+    signal my_Addr : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
48
+    signal my_D_OUT : STD_LOGIC_VECTOR (27 downto 0);
49
+    
50
+begin
51
+
52
+    instance : MemoireInstructions
53
+    generic map (Nb_bits => 28,
54
+                 Addr_size => 4,
55
+                 Mem_size => 16
56
+    )
57
+    port map (
58
+        Addr => my_Addr,
59
+        D_OUT => my_D_OUT
60
+    );
61
+    
62
+    process 
63
+    begin
64
+        my_Addr <= "0001" after 10 ns, "0010" after 20 ns, "0011" after 30 ns;        
65
+        wait;
66
+    end process;    
67
+end Behavioral;

+ 121
- 0
Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd View File

@@ -0,0 +1,121 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 14:31:37
6
+-- Design Name: 
7
+-- Module Name: Test_Etage2_5_Registres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etage2_5_Registres is
35
+--  Port ( );
36
+end Test_Etage2_5_Registres;
37
+
38
+architecture Behavioral of Test_Etage2_5_Registres is
39
+    component Etage2_5_Registres is
40
+    Generic ( Nb_bits : Natural;
41
+              Nb_registres : Natural;
42
+              Instruction_bus_size : Natural;
43
+              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
44
+              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
45
+    Port ( CLK : in STD_LOGIC;
46
+           RST : in STD_LOGIC;
47
+           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50
+           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
51
+           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
53
+           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
54
+           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
55
+           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
56
+           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
57
+           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
58
+    end component;
59
+    
60
+    signal my_CLK : STD_LOGIC := '0';
61
+    signal my_RST : STD_LOGIC := '1';
62
+    signal my_IN_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63
+    signal my_IN_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
64
+    signal my_IN_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
65
+    signal my_IN_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
66
+    signal my_OUT_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
67
+    signal my_OUT_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
68
+    signal my_OUT_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
69
+    signal my_OUT_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
70
+    signal my_IN_5_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
71
+    signal my_IN_5_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
72
+    signal my_IN_5_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
73
+    
74
+    constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (7 downto 0) := "01111110";
75
+    constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (7 downto 0) := "01100001";
76
+    
77
+    constant CLK_period : time := 10 ns;
78
+    
79
+begin
80
+
81
+    instance : Etage2_5_Registres
82
+    generic map( Nb_bits => 8,
83
+                 Nb_Registres => 16,
84
+                 Instruction_bus_size => 3,
85
+                 Bits_Controle_LC_5 => Bits_Controle_LC_5,
86
+                 Bits_Controle_MUX_2 => Bits_Controle_MUX_2)
87
+    port map(    CLK => my_CLK,
88
+                 RST => my_RST,
89
+                 IN_2_A => my_IN_2_A,
90
+                 IN_2_B => my_IN_2_B,
91
+                 IN_2_C => my_IN_2_C,
92
+                 IN_2_Instruction => my_IN_2_Instruction,
93
+                 OUT_2_A => my_OUT_2_A,
94
+                 OUT_2_B => my_OUT_2_B,
95
+                 OUT_2_C => my_OUT_2_C,
96
+                 OUT_2_Instruction => my_OUT_2_Instruction,
97
+                 IN_5_A => my_IN_5_A,
98
+                 IN_5_B => my_IN_5_B,
99
+                 IN_5_Instruction => my_IN_5_Instruction);
100
+    
101
+    CLK_process :process
102
+    begin
103
+        my_CLK <= '1';
104
+        wait for CLK_period/2;
105
+        my_CLK <= '0';
106
+        wait for CLK_period/2;
107
+    end process;
108
+    
109
+    process 
110
+    begin     
111
+        my_RST <= '0' after 33 ns;
112
+        my_IN_2_A <= "01011111" after 0 ns;
113
+        my_IN_2_B <= "00000011" after 0 ns, "00000100" after 40 ns;
114
+        my_IN_2_C <= "00000001" after 0 ns, "00000000" after 40 ns;
115
+        my_IN_2_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
116
+        my_IN_5_A <= "00000010" after 0 ns, "00000000" after 10 ns, "00000011" after 20 ns, "00000010" after 30 ns;
117
+        my_IN_5_B <= "11111111" after 0 ns, "11111110" after 10 ns, "11111101" after 20 ns, "11111100" after 30 ns;
118
+        my_IN_5_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
119
+        wait;
120
+    end process;    
121
+end Behavioral;

+ 105
- 0
Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd View File

@@ -0,0 +1,105 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 11:26:48
6
+-- Design Name: 
7
+-- Module Name: Test_Etage3_Calcul - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etage3_Calcul is
35
+--  Port ( );
36
+end Test_Etage3_Calcul;
37
+
38
+architecture Behavioral of Test_Etage3_Calcul is
39
+    component Etage3_Calcul is
40
+        Generic ( Nb_bits : Natural;
41
+                  OP_vector_size : Natural;
42
+                  Instruction_bus_size : Natural;
43
+                  Bits_Controle_LC : STD_LOGIC_VECTOR;
44
+                  Bits_Controle_MUX : STD_LOGIC_VECTOR);
45
+        Port ( RST : STD_LOGIC;
46
+               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
47
+               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+               IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
50
+               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
51
+               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
53
+               N : out STD_LOGIC;
54
+               O : out STD_LOGIC;
55
+               Z : out STD_LOGIC;
56
+               C : out STD_LOGIC);
57
+    end component;
58
+    
59
+    signal my_RST : STD_LOGIC := '1';
60
+    signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
61
+    signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
62
+    signal my_IN_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63
+    signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
64
+    signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
65
+    signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
66
+    signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
67
+    signal my_N : STD_LOGIC;
68
+    signal my_O : STD_LOGIC;
69
+    signal my_Z : STD_LOGIC;
70
+    signal my_C : STD_LOGIC;
71
+    
72
+    constant Bits_Controle_LC : STD_LOGIC_VECTOR (15 downto 0) := x"00b4";
73
+    constant Bits_Controle_MUX : STD_LOGIC_VECTOR (7 downto 0) := "11110001";
74
+    
75
+begin
76
+
77
+    instance : Etage3_Calcul
78
+    generic map( Nb_bits => 8,
79
+                 OP_vector_size => 2,
80
+                 Instruction_bus_size => 3,
81
+                 Bits_Controle_LC => Bits_Controle_LC,
82
+                 Bits_Controle_MUX => Bits_Controle_MUX)
83
+    port map(    RST => my_RST,
84
+                 IN_A => my_IN_A,
85
+                 IN_B => my_IN_B,
86
+                 IN_C => my_IN_C,
87
+                 IN_Instruction => my_IN_Instruction,
88
+                 OUT_A => my_OUT_A,
89
+                 OUT_B => my_OUT_B,
90
+                 OUT_Instruction => my_OUT_Instruction,
91
+                 N => my_N,
92
+                 O => my_O,
93
+                 Z => my_Z,
94
+                 C => my_C);
95
+    
96
+    process 
97
+    begin     
98
+        my_IN_A <= "01011111";
99
+        my_IN_B <= "10100110";
100
+        my_IN_C <= "01101101";
101
+        my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
102
+        my_RST <= '0' after 45 ns;
103
+        wait;
104
+    end process;    
105
+end Behavioral;

+ 105
- 0
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd View File

@@ -0,0 +1,105 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 13:37:04
6
+-- Design Name: 
7
+-- Module Name: Test_Etage4_Memoire - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etage4_Memoire is
35
+--  Port ( );
36
+end Test_Etage4_Memoire;
37
+
38
+architecture Behavioral of Test_Etage4_Memoire is
39
+    component Etage4_Memoire is
40
+    Generic ( Nb_bits : Natural;
41
+              Mem_size : Natural;
42
+              Instruction_bus_size : Natural;
43
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
44
+              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
45
+              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
46
+        Port ( CLK : in STD_LOGIC;
47
+               RST : in STD_LOGIC;
48
+               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50
+               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
51
+               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
53
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
54
+    end component;
55
+    
56
+    signal my_CLK : STD_LOGIC := '0';
57
+    signal my_RST : STD_LOGIC := '1';
58
+    signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
59
+    signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
60
+    signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
61
+    signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
62
+    signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63
+    signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
64
+    
65
+    constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
66
+    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
67
+    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
68
+    
69
+    constant CLK_period : time := 10 ns;
70
+    
71
+begin
72
+
73
+    instance : Etage4_Memoire
74
+    generic map( Nb_bits => 8,
75
+                 Mem_size => 256,
76
+                 Instruction_bus_size => 3,
77
+                 Bits_Controle_LC => Bits_Controle_LC,
78
+                 Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
79
+                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
80
+    port map(    CLK => my_CLK,
81
+                 RST => my_RST,
82
+                 IN_A => my_IN_A,
83
+                 IN_B => my_IN_B,
84
+                 IN_Instruction => my_IN_Instruction,
85
+                 OUT_A => my_OUT_A,
86
+                 OUT_B => my_OUT_B,
87
+                 OUT_Instruction => my_OUT_Instruction);
88
+    
89
+    CLK_process :process
90
+    begin
91
+        my_CLK <= '0';
92
+        wait for CLK_period/2;
93
+        my_CLK <= '1';
94
+        wait for CLK_period/2;
95
+    end process;
96
+    
97
+    process 
98
+    begin     
99
+        my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
100
+        my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
101
+        my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
102
+        my_RST <= '0' after 125 ns;
103
+        wait;
104
+    end process;    
105
+end Behavioral;

+ 118
- 0
Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd View File

@@ -0,0 +1,118 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 22:28:40
6
+-- Design Name: 
7
+-- Module Name: Test_Etape1_LectureInstruction - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Etape1_LectureInstruction is
35
+--  Port ( );
36
+end Test_Etape1_LectureInstruction;
37
+
38
+architecture Behavioral of Test_Etape1_LectureInstruction is
39
+    component Etage1_LectureInstruction is
40
+    Generic (Instruction_size_in_memory : Natural;
41
+             Addr_size_mem_instruction : Natural;
42
+             Mem_instruction_size : Natural;
43
+             Nb_bits : Natural;
44
+             Instruction_bus_size : Natural;
45
+             Nb_registres : Natural;
46
+             Mem_adresse_retour_size : Natural;
47
+             Adresse_size_mem_adresse_retour : Natural;
48
+             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
49
+             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
50
+             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
51
+             Code_Instruction_JMP : STD_LOGIC_VECTOR;
52
+             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
53
+             Code_Instruction_CALL : STD_LOGIC_VECTOR;
54
+             Code_Instruction_RET : STD_LOGIC_VECTOR);
55
+    Port ( CLK : in STD_LOGIC;
56
+           RST : in STD_LOGIC;
57
+           Z : in STD_LOGIC;
58
+           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
59
+           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
60
+           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
61
+           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
62
+    end component;
63
+    
64
+    signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
65
+    signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
66
+    signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
67
+    signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
68
+    signal my_CLK : STD_LOGIC := '0';
69
+    signal my_RST : STD_LOGIC := '1';
70
+    signal my_Z : STD_LOGIC := '1';
71
+    
72
+    constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
73
+    constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
74
+    constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
75
+    
76
+    constant CLK_period : time := 10 ns;
77
+    
78
+begin
79
+    instance : Etage1_LectureInstruction
80
+    generic map (Instruction_size_in_memory => 28,
81
+                 Addr_size_mem_instruction => 4,
82
+                 Mem_instruction_size => 16,
83
+                 Nb_bits => 8,
84
+                 Instruction_bus_size => 4,
85
+                 Nb_registres => 16,
86
+                 Mem_adresse_retour_size => 4,
87
+                 Adresse_size_mem_adresse_retour => 2,
88
+                 Instructions_critiques_lecture => Instructions_critiques_lecture,
89
+                 Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
90
+                 Instructions_critiques_ecriture => Instructions_critiques_ecriture,
91
+                 Code_Instruction_JMP => "1100",
92
+                 Code_Instruction_JMZ => "1101",
93
+                 Code_Instruction_CALL => "1110",
94
+                 Code_Instruction_RET => "1111"
95
+    )
96
+    port map (
97
+        CLK => my_CLK,
98
+        RST => my_RST,
99
+        z => my_Z,
100
+        A => my_A,
101
+        B => my_B,
102
+        C => my_C,
103
+        Instruction => my_Instruction
104
+    );
105
+			
106
+    CLK_process :process
107
+    begin
108
+        my_CLK <= '0';
109
+        wait for CLK_period/2;
110
+        my_CLK <= '1';
111
+        wait for CLK_period/2;
112
+    end process;
113
+    
114
+    process 
115
+    begin   
116
+        wait;
117
+    end process;    
118
+end Behavioral;

+ 66
- 0
Processeur.srcs/sim_1/new/Test_LC.vhd View File

@@ -0,0 +1,66 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 22:43:43
6
+-- Design Name: 
7
+-- Module Name: Test_LC - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_LC is
35
+--  Port ( );
36
+end Test_LC;
37
+
38
+architecture Behavioral of Test_LC is
39
+component LC is
40
+    Generic (Instruction_Vector_Size : Natural;
41
+            Command_size : Natural;
42
+            Bits_Controle : STD_LOGIC_VECTOR);
43
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
44
+           Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
45
+end component;
46
+    
47
+    signal my_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
48
+    signal my_Commande : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
49
+    constant Bits_Controle : STD_LOGIC_VECTOR (15 downto 0) := x"c138";
50
+begin
51
+
52
+    instance : LC
53
+    generic map (Instruction_Vector_Size => 3,
54
+                 Command_size => 2,
55
+                 Bits_Controle => Bits_Controle)
56
+    port map (
57
+        Instruction => my_Instruction,
58
+        Commande => my_Commande
59
+    );
60
+    
61
+    process 
62
+    begin
63
+        my_Instruction <= "000" after 1 ns, "001" after 2 ns, "010" after 3 ns, "011" after 4 ns, "100" after 5 ns, "101" after 6 ns, "110" after 7 ns, "111" after 8 ns;
64
+        wait;
65
+    end process;    
66
+end Behavioral;

+ 74
- 0
Processeur.srcs/sim_1/new/Test_MUX.vhd View File

@@ -0,0 +1,74 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 22:43:43
6
+-- Design Name: 
7
+-- Module Name: Test_MUX - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_MUX is
35
+--  Port ( );
36
+end Test_MUX;
37
+
38
+architecture Behavioral of Test_MUX is
39
+component MUX is
40
+    Generic (Nb_bits : Natural;
41
+            Instruction_Vector_Size : Natural;
42
+            Bits_Controle : STD_LOGIC_VECTOR);
43
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
44
+           IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
46
+           OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
47
+end component;
48
+    
49
+    signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
50
+    signal my_IN1 : STD_LOGIC_VECTOR (15 downto 0);
51
+    signal my_IN2 : STD_LOGIC_VECTOR (15 downto 0);
52
+    signal my_OUTPUT : STD_LOGIC_VECTOR (15 downto 0);
53
+    
54
+begin
55
+
56
+    instance : MUX
57
+    generic map (Nb_bits => 16,
58
+                 Instruction_Vector_Size => 4,
59
+                 Bits_Controle => x"aaaa")
60
+    port map (
61
+        Instruction => my_Instruction,
62
+        IN1 => my_IN1,
63
+        IN2 => my_IN2,
64
+        OUTPUT => my_OUTPUT
65
+    );
66
+    
67
+    process 
68
+    begin
69
+        my_IN1 <= x"abcd";
70
+        my_IN2 <= x"1234";
71
+        my_Instruction <= "0000" after 1 ns, "0001" after 2 ns, "0010" after 3 ns, "0011" after 4 ns, "0100" after 5 ns, "0101" after 6 ns, "0110" after 7 ns, "0111" after 8 ns;
72
+        wait;
73
+    end process;    
74
+end Behavioral;

+ 80
- 0
Processeur.srcs/sim_1/new/Test_Pipeline.vhd View File

@@ -0,0 +1,80 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 17:35:57
6
+-- Design Name: 
7
+-- Module Name: Test_Pipeline - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Pipeline is
35
+--  Port ( );
36
+end Test_Pipeline;
37
+
38
+architecture Behavioral of Test_Pipeline is
39
+    
40
+    component Pipeline is
41
+    Generic (Nb_bits : Natural := 8;
42
+             Instruction_En_Memoire_Size : Natural := 28;
43
+             Addr_Memoire_Instruction_Size : Natural := 3;
44
+             Memoire_Instruction_Size : Natural := 8;
45
+             Instruction_Bus_Size : Natural := 4;
46
+             Nb_Instructions : Natural := 16;
47
+             Nb_Registres : Natural := 16;
48
+             Memoire_Size : Natural := 8;
49
+             Memoire_Adresses_Retour_Size : Natural := 16;
50
+             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
51
+    Port (CLK : STD_LOGIC;
52
+          RST : STD_LOGIC);
53
+    end component;
54
+    
55
+    signal my_CLK : STD_LOGIC := '0';
56
+    signal my_RST : STD_LOGIC := '1';
57
+    
58
+    constant CLK_period : time := 10 ns;
59
+    
60
+begin
61
+    instance : Pipeline
62
+    generic map (Addr_Memoire_Instruction_Size => 4,
63
+                 Memoire_Instruction_Size => 16)
64
+    port map (CLK => my_CLK,
65
+              RST => my_RST);
66
+              
67
+    CLK_process :process
68
+    begin
69
+        my_CLK <= '1';
70
+        wait for CLK_period/2;
71
+        my_CLK <= '0';
72
+        wait for CLK_period/2;
73
+    end process;
74
+    
75
+    process 
76
+    begin
77
+        my_RST <= '0' after 34 ns, '1' after 57 ns;
78
+        wait;
79
+    end process;
80
+end Behavioral;

+ 85
- 0
Processeur.srcs/sources_1/new/ALU.vhd View File

@@ -0,0 +1,85 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 13.04.2021 10:07:41
6
+-- Design Name: 
7
+-- Module Name: ALU - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity ALU is
36
+    Generic (Nb_bits : Natural);
37
+    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
38
+           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
39
+           OP : in STD_LOGIC_VECTOR (2 downto 0);
40
+           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
41
+           N : out STD_LOGIC;
42
+           O : out STD_LOGIC;
43
+           Z : out STD_LOGIC;
44
+           C : out STD_LOGIC);
45
+end ALU;
46
+
47
+architecture Behavioral of ALU is
48
+    signal A9 :  STD_LOGIC_VECTOR (Nb_bits downto 0);
49
+    signal B9 :  STD_LOGIC_VECTOR (Nb_bits downto 0);
50
+    signal ADD :  STD_LOGIC_VECTOR (Nb_bits downto 0);
51
+    signal SUB :  STD_LOGIC_VECTOR (Nb_bits downto 0);
52
+    signal MUL :  STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0);
53
+    signal intern_N : STD_LOGIC;
54
+    signal intern_Z : STD_LOGIC;
55
+    constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
56
+    constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
57
+    
58
+    
59
+begin
60
+    A9 <= '0' & A;
61
+    B9 <= '0' & B;
62
+    ADD <= A9 + B9;
63
+    SUB <= A9 - B9;
64
+    MUL <= A * B;    
65
+    
66
+    S <= ADD (Nb_bits-1 downto 0) when OP = "001" else 
67
+         SUB (Nb_bits-1 downto 0) when OP = "010" else 
68
+         MUL (Nb_bits-1 downto 0) when OP = "011" else
69
+         -- Add division
70
+         (0 => intern_N, others => '0') when OP = "101" else
71
+         (0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else
72
+         (0 => intern_Z, others => '0') when OP = "111" else
73
+         (others => '0');
74
+         
75
+         
76
+    intern_N <= SUB (Nb_bits);
77
+    intern_Z <= '1' when (SUB = ZERO_N1) else 
78
+         '0';
79
+         
80
+    N <= intern_N;
81
+    O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
82
+         '1';
83
+    Z <= intern_Z;
84
+    C <= ADD (Nb_bits);
85
+end Behavioral;

+ 68
- 0
Processeur.srcs/sources_1/new/BancRegistres.vhd View File

@@ -0,0 +1,68 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 15.04.2021 08:23:48
6
+-- Design Name: 
7
+-- Module Name: BancRegistres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+--use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+--use IEEE.STD_LOGIC_ARITH.ALL;
26
+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
29
+use IEEE.NUMERIC_STD.ALL;
30
+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
35
+
36
+entity BancRegistres is
37
+    Generic (Nb_bits : Natural;
38
+             Addr_size : Natural;
39
+             Nb_regs : Natural);
40
+    Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
41
+           AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
42
+           AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
43
+           W : in STD_LOGIC;
44
+           DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
45
+           RST : in STD_LOGIC;
46
+           CLK : in STD_LOGIC;
47
+           QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
48
+           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
49
+end BancRegistres;
50
+
51
+-- ASK MEILLEURE IDEE UN TABLEAU
52
+architecture Behavioral of BancRegistres is
53
+    signal REGISTRES : STD_LOGIC_VECTOR ((Nb_regs * Nb_bits)-1 downto 0) := (others => '0');
54
+begin
55
+    process
56
+    begin
57
+        wait until CLK'event and CLK = '1';
58
+        if (RST = '0') then
59
+            REGISTRES <= (others => '0');
60
+        else 
61
+            if (W = '1') then
62
+                REGISTRES (((to_integer(unsigned(AddrW)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(AddrW))) <= DATA;
63
+            end if;
64
+        end if;
65
+    end process;
66
+    QA <= REGISTRES (((to_integer(unsigned(AddrA)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrA)));
67
+    QB <= REGISTRES (((to_integer(unsigned(AddrB)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(AddrB)));
68
+end Behavioral;

+ 196
- 0
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd View File

@@ -0,0 +1,196 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage1_LectureInstruction - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity Etage1_LectureInstruction is
36
+    Generic (Instruction_size_in_memory : Natural;
37
+             Addr_size_mem_instruction : Natural;
38
+             Mem_instruction_size : Natural;
39
+             Nb_bits : Natural;
40
+             Instruction_bus_size : Natural;
41
+             Nb_registres : Natural;
42
+             Mem_adresse_retour_size : Natural;
43
+             Adresse_size_mem_adresse_retour : Natural;
44
+             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
45
+             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
46
+             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
47
+             Code_Instruction_JMP : STD_LOGIC_VECTOR;
48
+             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
49
+             Code_Instruction_CALL : STD_LOGIC_VECTOR;
50
+             Code_Instruction_RET : STD_LOGIC_VECTOR);
51
+    Port ( CLK : in STD_LOGIC;
52
+           RST : in STD_LOGIC;
53
+           Z : in STD_LOGIC;
54
+           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
55
+           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
56
+           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
57
+           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
58
+end Etage1_LectureInstruction;
59
+
60
+architecture Behavioral of Etage1_LectureInstruction is
61
+    component MemoireInstructions is
62
+    Generic (Nb_bits : Natural;
63
+             Addr_size : Natural;
64
+             Mem_size : Natural);
65
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
66
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
67
+    end component;
68
+    
69
+    component MemoireAdressesRetour is
70
+        Generic (Nb_bits : Natural;
71
+                 Addr_size : Natural;
72
+                 Mem_size : Natural);
73
+        Port ( R : in STD_LOGIC;
74
+               W : in STD_LOGIC;
75
+               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
76
+               RST : in STD_LOGIC;
77
+               CLK : in STD_LOGIC;
78
+               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
79
+               E : out STD_LOGIC;
80
+               F : out STD_LOGIC);
81
+    end component;
82
+    
83
+    signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
84
+    signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
85
+    signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
86
+    
87
+    subtype Registre is integer range -1 to Nb_registres - 1;
88
+    type Tab_registres is array (1 to 4) of Registre;
89
+    signal Tableau : Tab_registres := (others => - 1);
90
+    
91
+    signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
92
+    signal Nul : STD_LOGIC := '0';
93
+    signal R_Aux : STD_LOGIC := '0';
94
+    signal W_Aux : STD_LOGIC := '0';
95
+
96
+    constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
97
+    constant Argument_nul : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
98
+    
99
+    signal bulles : boolean := false;
100
+    
101
+    signal compteur : integer := 0;
102
+    
103
+begin
104
+    instance : MemoireInstructions
105
+    generic map (Nb_bits => Instruction_size_in_memory,
106
+                 Addr_size => Addr_size_mem_instruction,
107
+                 Mem_size => Mem_instruction_size)
108
+    port map (Addr => Pointeur_Instruction,
109
+              D_OUT => Instruction_courante);
110
+              
111
+    instance_MemoireAdressesRetour : MemoireAdressesRetour
112
+    generic map (Nb_bits => Addr_size_mem_instruction,
113
+                 Addr_size => Adresse_size_mem_adresse_retour,
114
+                 Mem_size => Mem_adresse_retour_size
115
+    )
116
+    port map ( R => R_Aux,
117
+               W => W_Aux,
118
+               D_IN => Pointeur_instruction_next,
119
+               RST => RST,
120
+               CLK => CLK,
121
+               D_OUT => Adresse_Retour,
122
+               E => Nul,
123
+               F => Nul
124
+    );
125
+
126
+              
127
+    process 
128
+    begin
129
+        wait until CLK'event and CLK = '1';
130
+        if (RST = '0') then
131
+            Tableau <= (others => -1);
132
+            Pointeur_Instruction <= (others => '0');
133
+            C <= Argument_nul;
134
+            B <= Argument_nul;
135
+            A <= Argument_nul;
136
+            Instruction <= Instruction_nulle;
137
+        else
138
+            Tableau(4) <= Tableau(3);
139
+            Tableau(3) <= Tableau(2);
140
+            Tableau(2) <= Tableau(1);
141
+            Tableau(1) <= -1;
142
+            if (not bulles) then
143
+                if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
144
+                    C <= Argument_nul;
145
+                    B <= Argument_nul;
146
+                    A <= Argument_nul;
147
+                    Instruction <= Instruction_nulle;
148
+                    Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
149
+                elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
150
+                    C <= Argument_nul;
151
+                    B <= Argument_nul;
152
+                    A <= Argument_nul;
153
+                    Instruction <= Instruction_nulle;
154
+                    Pointeur_Instruction <= Adresse_Retour;
155
+                elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
156
+                    compteur <= compteur + 1;
157
+                    C <= Argument_nul;
158
+                    B <= Argument_nul;
159
+                    A <= Argument_nul;
160
+                    Instruction <= Instruction_nulle;
161
+                    if (compteur = 2) then
162
+                        if (Z = '1') then
163
+                            Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
164
+                        else 
165
+                            Pointeur_Instruction <= Pointeur_Instruction + 1;
166
+                        end if;
167
+                        compteur <= 0;
168
+                    end if;
169
+                else
170
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
171
+                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
172
+                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
173
+                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
174
+                    if (Instructions_critiques_ecriture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') then
175
+                        Tableau(1) <= to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)));
176
+                    end if;
177
+                    Pointeur_Instruction <= Pointeur_Instruction + 1;
178
+                end if;
179
+            else 
180
+                C <= Argument_nul;
181
+                B <= Argument_nul;
182
+                A <= Argument_nul;
183
+                Instruction <= Instruction_nulle;
184
+            end if;
185
+        end if;
186
+    end process;
187
+    
188
+    
189
+    -- Condition degueu -> Instruction qui lit dans B et B dans tableau ou instruction qui lit dans C et C dans tableau 
190
+    bulles <= ((Instructions_critiques_lecture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3)))) or ((Instructions_critiques_lecture_double(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') and ((to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2)) or (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))));
191
+    R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
192
+             '0';
193
+    W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
194
+             '0';
195
+    Pointeur_instruction_next <= Pointeur_instruction + 1;
196
+end Behavioral;

+ 134
- 0
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd View File

@@ -0,0 +1,134 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage2_5_Registres - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Etage2_5_Registres is
35
+    Generic ( Nb_bits : Natural;
36
+              Nb_registres : Natural;
37
+              Instruction_bus_size : Natural;
38
+              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
39
+              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
40
+    Port ( CLK : in STD_LOGIC;
41
+           RST : in STD_LOGIC;
42
+           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
43
+           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
44
+           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
46
+           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
47
+           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49
+           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
50
+           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
51
+           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52
+           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
53
+end Etage2_5_Registres;
54
+
55
+architecture Behavioral of Etage2_5_Registres is
56
+    component BancRegistres is
57
+    Generic (Nb_bits : Natural;
58
+             Addr_size : Natural;
59
+             Nb_regs : Natural);
60
+    Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
61
+           AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
62
+           AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
63
+           W : in STD_LOGIC;
64
+           DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
65
+           RST : in STD_LOGIC;
66
+           CLK : in STD_LOGIC;
67
+           QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
68
+           QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
69
+    end component;
70
+    
71
+    component LC is
72
+        Generic (Instruction_Vector_Size : Natural;
73
+                Command_size : Natural;
74
+                Bits_Controle : STD_LOGIC_VECTOR);
75
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
76
+               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
77
+    end component;
78
+    
79
+    component MUX is
80
+        Generic (Nb_bits : Natural;
81
+                Instruction_Vector_Size : Natural;
82
+                Bits_Controle : STD_LOGIC_VECTOR);
83
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
84
+               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
85
+               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
86
+               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
87
+    end component;
88
+    
89
+    signal Commande_BancRegistres : STD_LOGIC_VECTOR (0 downto 0) := "0";
90
+    signal Sortie_BancRegistres : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
91
+    signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
92
+    signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
93
+    
94
+begin
95
+    instance_LC : LC
96
+    generic map (Instruction_Vector_Size => Instruction_bus_size,
97
+                 Command_size => 1,
98
+                 Bits_Controle => Bits_Controle_LC_5)
99
+    port map (   Instruction => IN_5_Instruction,
100
+                 Commande => Commande_BancRegistres);
101
+                 
102
+    instance_MUX : MUX
103
+    generic map (Nb_bits => Nb_bits,
104
+                 Instruction_Vector_Size => Instruction_bus_size,
105
+                 Bits_Controle => Bits_Controle_MUX_2)
106
+    port map (   Instruction => IN_2_Instruction,
107
+                 IN1 => IN_2_B,
108
+                 IN2 => Sortie_BancRegistres,
109
+                 OUTPUT => intern_OUT_2_B);
110
+
111
+    instance_BancRegistres : BancRegistres
112
+    generic map (Nb_bits => Nb_bits,
113
+                 Addr_size => Nb_bits,
114
+                 Nb_regs => Nb_registres)
115
+    port map ( AddrA => IN_2_B,
116
+               AddrB => IN_2_C,
117
+               AddrW => IN_5_A,
118
+               W => Commande_BancRegistres(0),
119
+               DATA => IN_5_B,
120
+               RST => RST,
121
+               CLK => CLK,
122
+               QA => Sortie_BancRegistres,
123
+               QB => intern_OUT_2_C);                 
124
+                 
125
+    OUT_2_A <= (others => '0') when RST = '0' else
126
+               IN_2_A;
127
+    OUT_2_B <= (others => '0') when RST = '0' else
128
+               intern_OUT_2_B;
129
+    OUT_2_C <= (others => '0') when RST = '0' else
130
+               intern_OUT_2_C;
131
+    OUT_2_Instruction <= (others => '0') when RST = '0' else
132
+               IN_2_Instruction;    
133
+    
134
+end Behavioral;

+ 136
- 0
Processeur.srcs/sources_1/new/Etage3_Calcul.vhd View File

@@ -0,0 +1,136 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage3_Calcul - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Etage3_Calcul is
35
+    Generic ( Nb_bits : Natural;
36
+              Instruction_bus_size : Natural;
37
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
38
+              Bits_Controle_MUX : STD_LOGIC_VECTOR);
39
+    Port ( RST : in STD_LOGIC;
40
+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
41
+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
42
+           IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
43
+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
44
+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
46
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
47
+           N : out STD_LOGIC;
48
+           O : out STD_LOGIC;
49
+           Z : out STD_LOGIC;
50
+           C : out STD_LOGIC);
51
+end Etage3_Calcul;
52
+
53
+architecture Structural of Etage3_Calcul is
54
+    component ALU is
55
+    Generic (Nb_bits : Natural);
56
+    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
57
+           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
58
+           OP : in STD_LOGIC_VECTOR (2 downto 0);
59
+           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
60
+           N : out STD_LOGIC;
61
+           O : out STD_LOGIC;
62
+           Z : out STD_LOGIC;
63
+           C : out STD_LOGIC);
64
+    end component;
65
+    
66
+    component LC is
67
+        Generic (Instruction_Vector_Size : Natural;
68
+                Command_size : Natural;
69
+                Bits_Controle : STD_LOGIC_VECTOR);
70
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
71
+               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
72
+    end component;
73
+    
74
+    component MUX is
75
+        Generic (Nb_bits : Natural;
76
+                Instruction_Vector_Size : Natural;
77
+                Bits_Controle : STD_LOGIC_VECTOR);
78
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
79
+               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
80
+               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
81
+               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
82
+    end component;
83
+    
84
+    signal OP_ALU : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
85
+    signal Sortie_ALU : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
86
+    
87
+    signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
88
+    signal intern_N : STD_LOGIC := '0';
89
+    signal intern_O : STD_LOGIC := '0';
90
+    signal intern_Z : STD_LOGIC := '0';
91
+    signal intern_C : STD_LOGIC := '0';
92
+    
93
+    
94
+begin
95
+    instance_LC : LC
96
+    generic map (Instruction_Vector_Size => Instruction_bus_size,
97
+                 Command_size => 3,
98
+                 Bits_Controle => Bits_Controle_LC)
99
+    port map (   Instruction => IN_Instruction,
100
+                 Commande => OP_ALU);
101
+                 
102
+    instance_MUX : MUX
103
+    generic map (Nb_bits => Nb_bits,
104
+                 Instruction_Vector_Size => Instruction_bus_size,
105
+                 Bits_Controle => Bits_Controle_MUX)
106
+    port map (   Instruction => IN_Instruction,
107
+                 IN1 => IN_B,
108
+                 IN2 => Sortie_ALU,
109
+                 OUTPUT => intern_OUT_B);
110
+
111
+    instance_ALU : ALU
112
+    generic map (Nb_bits => Nb_bits)
113
+    port map    (A => IN_B,
114
+                 B => IN_C,
115
+                 OP => OP_ALU,
116
+                 S => Sortie_ALU,
117
+                 N => intern_N,
118
+                 O => intern_O,
119
+                 Z => intern_Z,
120
+                 C => intern_C);
121
+    
122
+    OUT_A <= (others => '0') when RST = '0' else
123
+             IN_A;
124
+    OUT_B <= (others => '0') when RST = '0' else
125
+             intern_OUT_B;
126
+    OUT_Instruction <= (others => '0') when RST = '0' else
127
+             IN_Instruction;
128
+    N <= '0' when RST = '0' else
129
+             intern_N;
130
+    O <= '0' when RST = '0' else
131
+             intern_O;
132
+    Z <= '0' when RST = '0' else
133
+             intern_Z;
134
+    C <= '0' when RST = '0' else
135
+             intern_C;
136
+end Structural;

+ 131
- 0
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File

@@ -0,0 +1,131 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 18.04.2021 21:19:41
6
+-- Design Name: 
7
+-- Module Name: Etage4_Memoire - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Etage4_Memoire is
35
+    Generic ( Nb_bits : Natural;
36
+              Mem_size : Natural;
37
+              Instruction_bus_size : Natural;
38
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
39
+              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
40
+              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
41
+    Port ( CLK : in STD_LOGIC;
42
+           RST : in STD_LOGIC;
43
+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
44
+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
45
+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
46
+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
47
+           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
49
+end Etage4_Memoire;
50
+
51
+architecture Structural of Etage4_Memoire is
52
+    component MemoireDonnees is
53
+    Generic (Nb_bits : Natural;
54
+             Addr_size : Natural;
55
+             Mem_size : Natural);
56
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
57
+           RW : in STD_LOGIC;
58
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
59
+           RST : in STD_LOGIC;
60
+           CLK : in STD_LOGIC;
61
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
62
+    end component;
63
+    
64
+    component LC is
65
+        Generic (Instruction_Vector_Size : Natural;
66
+                Command_size : Natural;
67
+                Bits_Controle : STD_LOGIC_VECTOR);
68
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
69
+               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
70
+    end component;
71
+    
72
+    component MUX is
73
+        Generic (Nb_bits : Natural;
74
+                Instruction_Vector_Size : Natural;
75
+                Bits_Controle : STD_LOGIC_VECTOR);
76
+        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
77
+               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
78
+               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
79
+               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
80
+    end component;
81
+    
82
+    signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
83
+    signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
84
+    signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
85
+    signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
86
+    
87
+begin
88
+    instance_LC : LC
89
+    generic map (Instruction_Vector_Size => Instruction_bus_size,
90
+                 Command_size => 1,
91
+                 Bits_Controle => Bits_Controle_LC)
92
+    port map (   Instruction => IN_Instruction,
93
+                 Commande => Commande_MemoireDonnees);
94
+                 
95
+    instance_MUX_IN : MUX
96
+    generic map (Nb_bits => Nb_bits,
97
+                 Instruction_Vector_Size => Instruction_bus_size,
98
+                 Bits_Controle => Bits_Controle_MUX_IN)
99
+    port map (   Instruction => IN_Instruction,
100
+                 IN1 => IN_A,
101
+                 IN2 => IN_B,
102
+                 OUTPUT => Addr_MemoireDonnees);
103
+                 
104
+    instance_MUX_OUT : MUX
105
+    generic map (Nb_bits => Nb_bits,
106
+                 Instruction_Vector_Size => Instruction_bus_size,
107
+                 Bits_Controle => Bits_Controle_MUX_OUT)
108
+    port map (   Instruction => IN_Instruction,
109
+                 IN1 => Sortie_MemoireDonnees,
110
+                 IN2 => IN_B,
111
+                 OUTPUT => intern_OUT_B);
112
+
113
+    instance_MemoireDonnees : MemoireDonnees
114
+    generic map (Nb_bits => Nb_bits,
115
+                 Addr_size => Nb_bits,
116
+                 Mem_size => Mem_size)
117
+    port map ( Addr => Addr_MemoireDonnees,
118
+               RW => Commande_MemoireDonnees(0),
119
+               D_IN => IN_B,
120
+               RST => RST,
121
+               CLK => CLK,
122
+               D_OUT => Sortie_MemoireDonnees);
123
+                 
124
+    OUT_A <= (others => '0') when RST = '0' else
125
+             IN_A;
126
+    OUT_B <= (others => '0') when RST = '0' else
127
+             intern_OUT_B;
128
+    OUT_Instruction <= (others => '0') when RST = '0' else
129
+             IN_Instruction;
130
+
131
+end Structural;

+ 45
- 0
Processeur.srcs/sources_1/new/LC.vhd View File

@@ -0,0 +1,45 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 21:49:57
6
+-- Design Name: 
7
+-- Module Name: LC - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity LC is
35
+    Generic (Instruction_Vector_Size : Natural;
36
+            Command_size : Natural;
37
+            Bits_Controle : STD_LOGIC_VECTOR);
38
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
39
+           Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
40
+end LC;
41
+
42
+architecture Behavioral of LC is
43
+begin
44
+    Commande <= Bits_Controle (((1 + to_integer(unsigned(Instruction))) * Command_size - 1) downto (Command_size * to_integer(unsigned(Instruction))));
45
+end Behavioral;

+ 48
- 0
Processeur.srcs/sources_1/new/MUX.vhd View File

@@ -0,0 +1,48 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 17.04.2021 21:49:57
6
+-- Design Name: 
7
+-- Module Name: MUX - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity MUX is
35
+    Generic (Nb_bits : Natural;
36
+            Instruction_Vector_Size : Natural;
37
+            Bits_Controle : STD_LOGIC_VECTOR);
38
+    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
39
+           IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
40
+           IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
41
+           OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
42
+end MUX;
43
+
44
+architecture Behavioral of MUX is
45
+begin
46
+    OUTPUT <= IN1 when (Bits_Controle(to_integer(unsigned(Instruction))) = '1') else 
47
+              IN2;
48
+end Behavioral;

+ 77
- 0
Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd View File

@@ -0,0 +1,77 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 14:35:04
6
+-- Design Name: 
7
+-- Module Name: MemoireAdressesRetour - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity MemoireAdressesRetour is
36
+    Generic (Nb_bits : Natural;
37
+             Addr_size : Natural;
38
+             Mem_size : Natural);
39
+    Port ( R : in STD_LOGIC;
40
+           W : in STD_LOGIC;
41
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
42
+           RST : in STD_LOGIC;
43
+           CLK : in STD_LOGIC;
44
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
45
+           E : out STD_LOGIC;
46
+           F : out STD_LOGIC);
47
+end MemoireAdressesRetour;
48
+
49
+architecture Behavioral of MemoireAdressesRetour is
50
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
51
+    signal Addr : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
52
+    constant EMPTY : STD_LOGIC_VECTOR (Addr_size downto 0) := (others => '0');
53
+    constant FULL : STD_LOGIC_VECTOR (Addr_size downto 0) := (Addr_size => '1', others => '0');
54
+begin
55
+    process
56
+    begin
57
+        wait until CLK'event and CLK = '1';
58
+        if (RST = '0' ) then
59
+            MEMORY <= (others => '0');
60
+            Addr <= (others => '0');
61
+        else
62
+            if (W = '1') then
63
+                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
64
+                Addr <= Addr + 1;
65
+            elsif (R = '1') then 
66
+                Addr <= Addr - 1;
67
+            end if;
68
+        end if;
69
+    end process;
70
+    E <= '1' when Addr = EMPTY else
71
+         '0';
72
+    F <= '1' when Addr = FULL else
73
+         '0';
74
+         
75
+    D_OUT <= (others => '0') when Addr = EMPTY else
76
+             MEMORY (to_integer(unsigned(Addr)) * Nb_bits - 1 downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
77
+end Behavioral;

+ 62
- 0
Processeur.srcs/sources_1/new/MemoireDonnees.vhd View File

@@ -0,0 +1,62 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 14:35:04
6
+-- Design Name: 
7
+-- Module Name: MemoireDonnees - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity MemoireDonnees is
35
+    Generic (Nb_bits : Natural;
36
+             Addr_size : Natural;
37
+             Mem_size : Natural);
38
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
39
+           RW : in STD_LOGIC;
40
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
41
+           RST : in STD_LOGIC;
42
+           CLK : in STD_LOGIC;
43
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
44
+end MemoireDonnees;
45
+
46
+architecture Behavioral of MemoireDonnees is
47
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0');
48
+begin
49
+    process
50
+    begin
51
+        wait until CLK'event and CLK = '1';
52
+        if (RST = '0') then
53
+            MEMORY <= (others => '0');
54
+        else 
55
+            if (RW = '0') then
56
+                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
57
+            else 
58
+                D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
59
+            end if;
60
+        end if;
61
+    end process;
62
+end Behavioral;

+ 46
- 0
Processeur.srcs/sources_1/new/MemoireInstructions.vhd View File

@@ -0,0 +1,46 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 16.04.2021 14:35:04
6
+-- Design Name: 
7
+-- Module Name: MemoireInstructions - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity MemoireInstructions is
35
+    Generic (Nb_bits : Natural;
36
+             Addr_size : Natural;
37
+             Mem_size : Natural);
38
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
39
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
40
+end MemoireInstructions;
41
+
42
+architecture Behavioral of MemoireInstructions is
43
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"0000000"&x"f000000"&x"7040001"&x"6030001"&x"5020001"&x"9010500"&x"9000300"&x"d010000"&x"2000000"&x"e030000";
44
+begin
45
+    D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
46
+end Behavioral;

+ 290
- 0
Processeur.srcs/sources_1/new/Pipeline.vhd View File

@@ -0,0 +1,290 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 19.04.2021 16:57:41
6
+-- Design Name: 
7
+-- Module Name: Pipeline - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Pipeline is
35
+    Generic (Nb_bits : Natural := 8;
36
+             Instruction_En_Memoire_Size : Natural := 28;
37
+             Addr_Memoire_Instruction_Size : Natural := 3;
38
+             Memoire_Instruction_Size : Natural := 8;
39
+             Instruction_Bus_Size : Natural := 4;
40
+             Nb_Instructions : Natural := 16;
41
+             Nb_Registres : Natural := 16;
42
+             Memoire_Size : Natural := 8;
43
+             Memoire_Adresses_Retour_Size : Natural := 16;
44
+             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
45
+    Port (CLK : STD_LOGIC;
46
+          RST : STD_LOGIC);
47
+end Pipeline;
48
+
49
+architecture Behavioral of Pipeline is
50
+    
51
+    component Etage1_LectureInstruction is
52
+    Generic (Instruction_size_in_memory : Natural;
53
+             Addr_size_mem_instruction : Natural;
54
+             Mem_instruction_size : Natural;
55
+             Nb_bits : Natural;
56
+             Instruction_bus_size : Natural;
57
+             Nb_registres : Natural;
58
+             Mem_adresse_retour_size : Natural;
59
+             Adresse_size_mem_adresse_retour : Natural;
60
+             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
61
+             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
62
+             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
63
+             Code_Instruction_JMP : STD_LOGIC_VECTOR;
64
+             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
65
+             Code_Instruction_CALL : STD_LOGIC_VECTOR;
66
+             Code_Instruction_RET : STD_LOGIC_VECTOR);
67
+    Port ( CLK : in STD_LOGIC;
68
+           RST : in STD_LOGIC;
69
+           Z : in STD_LOGIC;
70
+           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
71
+           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
72
+           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
73
+           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
74
+    end component;
75
+    
76
+    component Etage2_5_Registres is
77
+    Generic ( Nb_bits : Natural;
78
+              Nb_registres : Natural;
79
+              Instruction_bus_size : Natural;
80
+              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
81
+              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
82
+    Port ( CLK : in STD_LOGIC;
83
+           RST : in STD_LOGIC;
84
+           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
85
+           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
86
+           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
87
+           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
88
+           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
89
+           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
90
+           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
91
+           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
92
+           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
93
+           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
94
+           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
95
+    end component;
96
+    
97
+    component Etage3_Calcul is
98
+    Generic ( Nb_bits : Natural;
99
+              Instruction_bus_size : Natural;
100
+              Bits_Controle_LC : STD_LOGIC_VECTOR;
101
+              Bits_Controle_MUX : STD_LOGIC_VECTOR);
102
+    Port ( RST : in STD_LOGIC;
103
+           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
104
+           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
105
+           IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
106
+           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
107
+           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);