Processeur/Processeur.srcs/sources_1/new/LC.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 17.04.2021 21:49:57
-- Design Name: 
-- Module Name: LC - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LC is
    Generic (Instruction_Vector_Size : Natural;
            Command_size : Natural;
            Bits_Controle : STD_LOGIC_VECTOR);
    Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
           Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end LC;

architecture Behavioral of LC is
begin
    Commande <= Bits_Controle (((1 + to_integer(unsigned(Instruction))) * Command_size - 1) downto (Command_size * to_integer(unsigned(Instruction))));
end Behavioral;