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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 18.04.2021 22:28:40
- -- Design Name:
- -- Module Name: Test_Etape1_LectureInstruction - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity Test_Etape1_LectureInstruction is
- -- Port ( );
- end Test_Etape1_LectureInstruction;
-
- architecture Behavioral of Test_Etape1_LectureInstruction is
- component Etage1_LectureInstruction is
- Generic (Instruction_size_in_memory : Natural;
- Addr_size_mem_instruction : Natural;
- Mem_instruction_size : Natural;
- Nb_bits : Natural;
- Instruction_bus_size : Natural;
- Nb_registres : Natural;
- Mem_adresse_retour_size : Natural;
- Adresse_size_mem_adresse_retour : Natural;
- Instructions_critiques_lecture : STD_LOGIC_VECTOR;
- Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
- Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
- Code_Instruction_JMP : STD_LOGIC_VECTOR;
- Code_Instruction_JMZ : STD_LOGIC_VECTOR;
- Code_Instruction_CALL : STD_LOGIC_VECTOR;
- Code_Instruction_RET : STD_LOGIC_VECTOR);
- Port ( CLK : in STD_LOGIC;
- RST : in STD_LOGIC;
- Z : in STD_LOGIC;
- A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
- end component;
-
- signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
- signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
- signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
- signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
- signal my_CLK : STD_LOGIC := '0';
- signal my_RST : STD_LOGIC := '1';
- signal my_Z : STD_LOGIC := '1';
-
- constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
- constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
- constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
-
- constant CLK_period : time := 10 ns;
-
- begin
- instance : Etage1_LectureInstruction
- generic map (Instruction_size_in_memory => 28,
- Addr_size_mem_instruction => 4,
- Mem_instruction_size => 16,
- Nb_bits => 8,
- Instruction_bus_size => 4,
- Nb_registres => 16,
- Mem_adresse_retour_size => 4,
- Adresse_size_mem_adresse_retour => 2,
- Instructions_critiques_lecture => Instructions_critiques_lecture,
- Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
- Instructions_critiques_ecriture => Instructions_critiques_ecriture,
- Code_Instruction_JMP => "1100",
- Code_Instruction_JMZ => "1101",
- Code_Instruction_CALL => "1110",
- Code_Instruction_RET => "1111"
- )
- port map (
- CLK => my_CLK,
- RST => my_RST,
- z => my_Z,
- A => my_A,
- B => my_B,
- C => my_C,
- Instruction => my_Instruction
- );
-
- CLK_process :process
- begin
- my_CLK <= '0';
- wait for CLK_period/2;
- my_CLK <= '1';
- wait for CLK_period/2;
- end process;
-
- process
- begin
- wait;
- end process;
- end Behavioral;
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