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Test_Etape1_LectureInstruction.vhd 4.1KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 18.04.2021 22:28:40
  6. -- Design Name:
  7. -- Module Name: Test_Etape1_LectureInstruction - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity Test_Etape1_LectureInstruction is
  30. -- Port ( );
  31. end Test_Etape1_LectureInstruction;
  32. architecture Behavioral of Test_Etape1_LectureInstruction is
  33. component Etage1_LectureInstruction is
  34. Generic (Instruction_size_in_memory : Natural;
  35. Addr_size_mem_instruction : Natural;
  36. Mem_instruction_size : Natural;
  37. Nb_bits : Natural;
  38. Instruction_bus_size : Natural;
  39. Nb_registres : Natural;
  40. Mem_adresse_retour_size : Natural;
  41. Adresse_size_mem_adresse_retour : Natural;
  42. Instructions_critiques_lecture : STD_LOGIC_VECTOR;
  43. Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
  44. Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
  45. Code_Instruction_JMP : STD_LOGIC_VECTOR;
  46. Code_Instruction_JMZ : STD_LOGIC_VECTOR;
  47. Code_Instruction_CALL : STD_LOGIC_VECTOR;
  48. Code_Instruction_RET : STD_LOGIC_VECTOR);
  49. Port ( CLK : in STD_LOGIC;
  50. RST : in STD_LOGIC;
  51. Z : in STD_LOGIC;
  52. A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  53. B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  54. C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  55. Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
  56. end component;
  57. signal my_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
  58. signal my_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
  59. signal my_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
  60. signal my_Instruction : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
  61. signal my_CLK : STD_LOGIC := '0';
  62. signal my_RST : STD_LOGIC := '1';
  63. signal my_Z : STD_LOGIC := '1';
  64. constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (15 downto 0) := "0000100111111110";
  65. constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (15 downto 0) := "0000000011111110";
  66. constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (15 downto 0) := "0000011111111110";
  67. constant CLK_period : time := 10 ns;
  68. begin
  69. instance : Etage1_LectureInstruction
  70. generic map (Instruction_size_in_memory => 28,
  71. Addr_size_mem_instruction => 4,
  72. Mem_instruction_size => 16,
  73. Nb_bits => 8,
  74. Instruction_bus_size => 4,
  75. Nb_registres => 16,
  76. Mem_adresse_retour_size => 4,
  77. Adresse_size_mem_adresse_retour => 2,
  78. Instructions_critiques_lecture => Instructions_critiques_lecture,
  79. Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
  80. Instructions_critiques_ecriture => Instructions_critiques_ecriture,
  81. Code_Instruction_JMP => "1100",
  82. Code_Instruction_JMZ => "1101",
  83. Code_Instruction_CALL => "1110",
  84. Code_Instruction_RET => "1111"
  85. )
  86. port map (
  87. CLK => my_CLK,
  88. RST => my_RST,
  89. z => my_Z,
  90. A => my_A,
  91. B => my_B,
  92. C => my_C,
  93. Instruction => my_Instruction
  94. );
  95. CLK_process :process
  96. begin
  97. my_CLK <= '0';
  98. wait for CLK_period/2;
  99. my_CLK <= '1';
  100. wait for CLK_period/2;
  101. end process;
  102. process
  103. begin
  104. wait;
  105. end process;
  106. end Behavioral;