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TestALU.vhd 2.3KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 16.04.2021 21:25:53
  6. -- Design Name:
  7. -- Module Name: TestALU - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity TestALU is
  30. -- Port ( );
  31. end TestALU;
  32. architecture Behavioral of TestALU is
  33. component ALU is
  34. Generic (Nb_bits : Natural);
  35. Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
  36. B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
  37. OP : in STD_LOGIC_VECTOR (1 downto 0);
  38. S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
  39. N : out STD_LOGIC;
  40. O : out STD_LOGIC;
  41. Z : out STD_LOGIC;
  42. C : out STD_LOGIC);
  43. end component;
  44. signal my_A : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  45. signal my_B : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  46. signal my_OP : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
  47. signal my_S : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
  48. signal my_N : STD_LOGIC := '0';
  49. signal my_O : STD_LOGIC := '0';
  50. signal my_Z : STD_LOGIC := '0';
  51. signal my_C : STD_LOGIC := '0';
  52. begin
  53. instance : ALU
  54. generic map (Nb_bits => 16)
  55. port map (
  56. A => my_A,
  57. B => my_B,
  58. OP => my_OP,
  59. S => my_S,
  60. N => my_N,
  61. O => my_O,
  62. Z => my_Z,
  63. C => my_C
  64. );
  65. process
  66. begin
  67. my_A <= x"0007" after 10 ns, x"00ff" after 100 ns;
  68. my_B <= x"0008" after 10 ns, x"ff01" after 100 ns;
  69. my_OP <= "01" after 10 ns, "10" after 30 ns, "11" after 50 ns, "01" after 67 ns, "00" after 100 ns;
  70. wait;
  71. end process;
  72. end Behavioral;