Processeur/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 18.04.2021 21:19:41
-- Design Name: 
-- Module Name: Etage4_Memoire - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Etage4_Memoire is
    Generic ( Nb_bits : Natural;
              Mem_size : Natural;
              Instruction_bus_size : Natural;
              Bits_Controle_LC : STD_LOGIC_VECTOR;
              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end Etage4_Memoire;

architecture Structural of Etage4_Memoire is
    component MemoireDonnees is
    Generic (Nb_bits : Natural;
             Addr_size : Natural;
             Mem_size : Natural);
    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
           RW : in STD_LOGIC;
           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           RST : in STD_LOGIC;
           CLK : in STD_LOGIC;
           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
    end component;
    
    component LC is
        Generic (Instruction_Vector_Size : Natural;
                Command_size : Natural;
                Bits_Controle : STD_LOGIC_VECTOR);
        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
    end component;
    
    component MUX is
        Generic (Nb_bits : Natural;
                Instruction_Vector_Size : Natural;
                Bits_Controle : STD_LOGIC_VECTOR);
        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
    end component;
    
    signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
    signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    
begin
    instance_LC : LC
    generic map (Instruction_Vector_Size => Instruction_bus_size,
                 Command_size => 1,
                 Bits_Controle => Bits_Controle_LC)
    port map (   Instruction => IN_Instruction,
                 Commande => Commande_MemoireDonnees);
                 
    instance_MUX_IN : MUX
    generic map (Nb_bits => Nb_bits,
                 Instruction_Vector_Size => Instruction_bus_size,
                 Bits_Controle => Bits_Controle_MUX_IN)
    port map (   Instruction => IN_Instruction,
                 IN1 => IN_A,
                 IN2 => IN_B,
                 OUTPUT => Addr_MemoireDonnees);
                 
    instance_MUX_OUT : MUX
    generic map (Nb_bits => Nb_bits,
                 Instruction_Vector_Size => Instruction_bus_size,
                 Bits_Controle => Bits_Controle_MUX_OUT)
    port map (   Instruction => IN_Instruction,
                 IN1 => Sortie_MemoireDonnees,
                 IN2 => IN_B,
                 OUTPUT => intern_OUT_B);

    instance_MemoireDonnees : MemoireDonnees
    generic map (Nb_bits => Nb_bits,
                 Addr_size => Nb_bits,
                 Mem_size => Mem_size)
    port map ( Addr => Addr_MemoireDonnees,
               RW => Commande_MemoireDonnees(0),
               D_IN => IN_B,
               RST => RST,
               CLK => CLK,
               D_OUT => Sortie_MemoireDonnees);
                 
    OUT_A <= (others => '0') when RST = '0' else
             IN_A;
    OUT_B <= (others => '0') when RST = '0' else
             intern_OUT_B;
    OUT_Instruction <= (others => '0') when RST = '0' else
             IN_Instruction;

end Structural;