Processeur/Processeur.srcs/sources_1/new/Pipeline.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.04.2021 16:57:41
-- Design Name: 
-- Module Name: Pipeline - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Pipeline is
    Generic (Nb_bits : Natural := 8;
             Instruction_En_Memoire_Size : Natural := 28;
             Addr_Memoire_Instruction_Size : Natural := 3;
             Memoire_Instruction_Size : Natural := 8;
             Instruction_Bus_Size : Natural := 4;
             Nb_Instructions : Natural := 16;
             Nb_Registres : Natural := 16;
             Memoire_Size : Natural := 8;
             Memoire_Adresses_Retour_Size : Natural := 16;
             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
    Port (CLK : STD_LOGIC;
          RST : STD_LOGIC);
end Pipeline;

architecture Behavioral of Pipeline is
    
    component Etage1_LectureInstruction is
    Generic (Instruction_size_in_memory : Natural;
             Addr_size_mem_instruction : Natural;
             Mem_instruction_size : Natural;
             Nb_bits : Natural;
             Instruction_bus_size : Natural;
             Nb_registres : Natural;
             Mem_adresse_retour_size : Natural;
             Adresse_size_mem_adresse_retour : Natural;
             Instructions_critiques_lecture : STD_LOGIC_VECTOR;
             Instructions_critiques_lecture_double : STD_LOGIC_VECTOR;
             Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
             Code_Instruction_JMP : STD_LOGIC_VECTOR;
             Code_Instruction_JMZ : STD_LOGIC_VECTOR;
             Code_Instruction_CALL : STD_LOGIC_VECTOR;
             Code_Instruction_RET : STD_LOGIC_VECTOR);
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           Z : in STD_LOGIC;
           A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
    end component;
    
    component Etage2_5_Registres is
    Generic ( Nb_bits : Natural;
              Nb_registres : Natural;
              Instruction_bus_size : Natural;
              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
    end component;
    
    component Etage3_Calcul is
    Generic ( Nb_bits : Natural;
              Instruction_bus_size : Natural;
              Bits_Controle_LC : STD_LOGIC_VECTOR;
              Bits_Controle_MUX : STD_LOGIC_VECTOR);
    Port ( RST : in STD_LOGIC;
           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
    end component;
        
    component Etage4_Memoire is
        Generic ( Nb_bits : Natural;
                  Mem_size : Natural;
                  Instruction_bus_size : Natural;
                  Bits_Controle_LC : STD_LOGIC_VECTOR;
                  Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
                  Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
        Port ( CLK : in STD_LOGIC;
               RST : in STD_LOGIC;
               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
    end component;
    
    signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
    signal N : STD_LOGIC := '0';
    signal Z : STD_LOGIC := '0';
    signal O : STD_LOGIC := '0';
    signal C : STD_LOGIC := '0';
    
    constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1101011000000001";
    constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
    constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111100000001";
    constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111011111111111";
    constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111101111111111";
    constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000010000000000";
    constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
    constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1100";
    constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1101";
    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1110";
    constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "1111";
    
    constant Instructions_critiques_lecture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000100111111110";
    constant Instructions_critiques_lecture_double : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000000011111110";
    constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "0000011111111110";
begin
    instance_Etage1 : Etage1_LectureInstruction
    generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
                 Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
                 Mem_instruction_size => Memoire_Instruction_Size,
                 Nb_bits => Nb_bits,
                 Instruction_bus_size => Instruction_Bus_Size,
                 Nb_registres => Nb_Registres,
                 Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
                 Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
                 Instructions_critiques_lecture => Instructions_critiques_lecture,
                 Instructions_critiques_lecture_double => Instructions_critiques_lecture_double,
                 Instructions_critiques_ecriture => Instructions_critiques_ecriture,
                 Code_Instruction_JMP => Code_Instruction_JMP,
                 Code_Instruction_JMZ => Code_Instruction_JMZ,
                 Code_Instruction_CALL => Code_Instruction_CALL,
                 Code_Instruction_RET => Code_Instruction_RET
    )
    port map (
        CLK => CLK,
        RST => RST,
        Z => Z,
        A => A_from_1,
        B => B_from_1,
        C => C_from_1,
        Instruction => Instruction_from_1
    );
    
    instance_Etage2_5 : Etage2_5_Registres
    generic map( Nb_bits => Nb_bits,
                 Nb_Registres => Nb_Registres,
                 Instruction_bus_size => Instruction_Bus_Size,
                 Bits_Controle_LC_5 => Bits_Controle_LC_5,
                 Bits_Controle_MUX_2 => Bits_Controle_MUX_2
    )
    port map(    CLK => CLK,
                 RST => RST,
                 IN_2_A => A_to_2,
                 IN_2_B => B_to_2,
                 IN_2_C => C_to_2,
                 IN_2_Instruction => Instruction_to_2,
                 OUT_2_A => A_from_2,
                 OUT_2_B => B_from_2,
                 OUT_2_C => C_from_2,
                 OUT_2_Instruction => Instruction_from_2,
                 IN_5_A => A_to_5,
                 IN_5_B => B_to_5,
                 IN_5_Instruction => Instruction_to_5
    );
    
    instance_Etage3 : Etage3_Calcul
    generic map( Nb_bits => Nb_bits,
                 Instruction_bus_size => Instruction_Bus_Size,
                 Bits_Controle_LC => Bits_Controle_LC_3,
                 Bits_Controle_MUX => Bits_Controle_MUX_3
    )
    port map(    RST => RST,
                 IN_A => A_to_3,
                 IN_B => B_to_3,
                 IN_C => C_to_3,
                 IN_Instruction => Instruction_to_3,
                 OUT_A => A_from_3,
                 OUT_B => B_from_3,
                 OUT_Instruction => Instruction_from_3,
                 N => N,
                 O => O,
                 Z => Z,
                 C => C
    );
    
    instance_Etage4 : Etage4_Memoire
    generic map( Nb_bits => Nb_bits,
                 Mem_size => Memoire_Size,
                 Instruction_bus_size => Instruction_Bus_Size,
                 Bits_Controle_LC => Bits_Controle_LC_4,
                 Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT
    )
    port map(    CLK => CLK,
                 RST => RST,
                 IN_A => A_to_4,
                 IN_B => B_to_4,
                 IN_Instruction => Instruction_to_4,
                 OUT_A => A_from_4,
                 OUT_B => B_from_4,
                 OUT_Instruction => Instruction_from_4
    );

    process
    begin
        wait until CLK'event and CLK = '1';
        A_to_2 <= A_from_1;
        B_to_2 <= B_from_1;
        C_to_2 <= C_from_1;
        Instruction_to_2 <= Instruction_from_1;
        
        A_to_3 <= A_from_2;
        B_to_3 <= B_from_2;
        C_to_3 <= C_from_2;
        Instruction_to_3 <= Instruction_from_2;

        A_to_4 <= A_from_3;
        B_to_4 <= B_from_3;
        Instruction_to_4 <= Instruction_from_3;

        A_to_5 <= A_from_4;
        B_to_5 <= B_from_4;
        Instruction_to_5 <= Instruction_from_4;
    end process;        
end Behavioral;