Processeur/Processeur.srcs/sources_1/new/ALU.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.04.2021 10:07:41
-- Design Name: 
-- Module Name: ALU - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Generic (Nb_bits : Natural);
    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           OP : in STD_LOGIC_VECTOR (2 downto 0);
           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
end ALU;

architecture Behavioral of ALU is
    signal A9 :  STD_LOGIC_VECTOR (Nb_bits downto 0);
    signal B9 :  STD_LOGIC_VECTOR (Nb_bits downto 0);
    signal ADD :  STD_LOGIC_VECTOR (Nb_bits downto 0);
    signal SUB :  STD_LOGIC_VECTOR (Nb_bits downto 0);
    signal MUL :  STD_LOGIC_VECTOR ((2*Nb_bits)-1 downto 0);
    signal intern_N : STD_LOGIC;
    signal intern_Z : STD_LOGIC;
    constant ZERO_N : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
    constant ZERO_N1 : STD_LOGIC_VECTOR (Nb_bits downto 0) := (others => '0');
    
    
begin
    A9 <= '0' & A;
    B9 <= '0' & B;
    ADD <= A9 + B9;
    SUB <= A9 - B9;
    MUL <= A * B;    
    
    S <= ADD (Nb_bits-1 downto 0) when OP = "001" else 
         SUB (Nb_bits-1 downto 0) when OP = "010" else 
         MUL (Nb_bits-1 downto 0) when OP = "011" else
         -- Add division
         (0 => intern_N, others => '0') when OP = "101" else
         (0 => '1', others => '0') when OP = "110" and intern_Z = '0' and intern_N = '0' else
         (0 => intern_Z, others => '0') when OP = "111" else
         (others => '0');
         
         
    intern_N <= SUB (Nb_bits);
    intern_Z <= '1' when (SUB = ZERO_N1) else 
         '0';
         
    N <= intern_N;
    O <= '0' when (MUL ((2*Nb_bits)-1 downto Nb_bits) = ZERO_N) else
         '1';
    Z <= intern_Z;
    C <= ADD (Nb_bits);
end Behavioral;