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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 16.04.2021 12:58:02
- -- Design Name:
- -- Module Name: TestMemoireInstructions - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity TestMemoireInstructions is
- -- Port ( );
- end TestMemoireInstructions;
-
- architecture Behavioral of TestMemoireInstructions is
- component MemoireInstructions is
- Generic (Nb_bits : Natural;
- Addr_size : Natural;
- Mem_size : Natural);
- Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
- D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
- end component;
-
- signal my_Addr : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
- signal my_D_OUT : STD_LOGIC_VECTOR (27 downto 0);
-
- begin
-
- instance : MemoireInstructions
- generic map (Nb_bits => 28,
- Addr_size => 4,
- Mem_size => 16
- )
- port map (
- Addr => my_Addr,
- D_OUT => my_D_OUT
- );
-
- process
- begin
- my_Addr <= "0001" after 10 ns, "0010" after 20 ns, "0011" after 30 ns;
- wait;
- end process;
- end Behavioral;
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