Processeur/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.04.2021 14:31:37
-- Design Name: 
-- Module Name: Test_Etage2_5_Registres - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_Etage2_5_Registres is
--  Port ( );
end Test_Etage2_5_Registres;

architecture Behavioral of Test_Etage2_5_Registres is
    component Etage2_5_Registres is
    Generic ( Nb_bits : Natural;
              Nb_registres : Natural;
              Instruction_bus_size : Natural;
              Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
              Bits_Controle_MUX_2 : STD_LOGIC_VECTOR);
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
    end component;
    
    signal my_CLK : STD_LOGIC := '0';
    signal my_RST : STD_LOGIC := '1';
    signal my_IN_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
    signal my_OUT_2_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_OUT_2_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_OUT_2_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_OUT_2_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
    signal my_IN_5_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_5_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_5_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
    
    constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (7 downto 0) := "01111110";
    constant Bits_Controle_MUX_2 : STD_LOGIC_VECTOR (7 downto 0) := "01100001";
    
    constant CLK_period : time := 10 ns;
    
begin

    instance : Etage2_5_Registres
    generic map( Nb_bits => 8,
                 Nb_Registres => 16,
                 Instruction_bus_size => 3,
                 Bits_Controle_LC_5 => Bits_Controle_LC_5,
                 Bits_Controle_MUX_2 => Bits_Controle_MUX_2)
    port map(    CLK => my_CLK,
                 RST => my_RST,
                 IN_2_A => my_IN_2_A,
                 IN_2_B => my_IN_2_B,
                 IN_2_C => my_IN_2_C,
                 IN_2_Instruction => my_IN_2_Instruction,
                 OUT_2_A => my_OUT_2_A,
                 OUT_2_B => my_OUT_2_B,
                 OUT_2_C => my_OUT_2_C,
                 OUT_2_Instruction => my_OUT_2_Instruction,
                 IN_5_A => my_IN_5_A,
                 IN_5_B => my_IN_5_B,
                 IN_5_Instruction => my_IN_5_Instruction);
    
    CLK_process :process
    begin
        my_CLK <= '1';
        wait for CLK_period/2;
        my_CLK <= '0';
        wait for CLK_period/2;
    end process;
    
    process 
    begin     
        my_RST <= '0' after 33 ns;
        my_IN_2_A <= "01011111" after 0 ns;
        my_IN_2_B <= "00000011" after 0 ns, "00000100" after 40 ns;
        my_IN_2_C <= "00000001" after 0 ns, "00000000" after 40 ns;
        my_IN_2_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
        my_IN_5_A <= "00000010" after 0 ns, "00000000" after 10 ns, "00000011" after 20 ns, "00000010" after 30 ns;
        my_IN_5_B <= "11111111" after 0 ns, "11111110" after 10 ns, "11111101" after 20 ns, "11111100" after 30 ns;
        my_IN_5_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns;
        wait;
    end process;    
end Behavioral;