Processeur/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.04.2021 12:58:02
-- Design Name: 
-- Module Name: TestMemoireAdressesRetour - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TestMemoireAdressesRetour is
--  Port ( );
end TestMemoireAdressesRetour;

architecture Behavioral of TestMemoireAdressesRetour is
    component MemoireAdressesRetour is
    Generic (Nb_bits : Natural;
             Addr_size : Natural;
             Mem_size : Natural);
    Port ( R : in STD_LOGIC;
           W : in STD_LOGIC;
           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           RST : in STD_LOGIC;
           CLK : in STD_LOGIC;
           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           E : out STD_LOGIC;
           F : out STD_LOGIC);
    end component;
    
    signal my_R : STD_LOGIC := '0';
    signal my_W : STD_LOGIC := '0';
    signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_RST : STD_LOGIC := '0';
    signal my_CLK : STD_LOGIC := '0';
    signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
    signal my_E : STD_LOGIC;
    signal my_F : STD_LOGIC;
    
    constant CLK_period : time := 10 ns;
    
begin

    instance : MemoireAdressesRetour
    generic map (Nb_bits => 8,
                 Addr_size => 2,
                 Mem_size => 4
    )
    port map (
        R => my_R,
        W => my_W,
        D_IN => my_D_IN,
        RST => my_RST,
        CLK => my_CLK,
        D_OUT => my_D_OUT,
        E => my_E,
        F => my_F
    );
			
    CLK_process :process
    begin
        my_CLK <= '0';
        wait for CLK_period/2;
        my_CLK <= '1';
        wait for CLK_period/2;
    end process;
    
    process 
    begin
        my_RST <= '1' after 0 ns, '0' after 100 ns;
        my_R <= '1' after 20 ns, '0' after 30 ns;
        my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 90 ns, '0' after 110 ns;
        my_D_IN <= "01010101" after 10 ns, "11100111" after 30 ns, "11111111" after 50 ns, "11111110" after 60 ns, "11111101" after 70 ns, "11111100" after 80 ns;
        
        wait;
    end process;    
end Behavioral;