Processeur/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 18.04.2021 21:19:41
-- Design Name: 
-- Module Name: Etage3_Calcul - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Etage3_Calcul is
    Generic ( Nb_bits : Natural;
              Instruction_bus_size : Natural;
              Bits_Controle_LC : STD_LOGIC_VECTOR;
              Bits_Controle_MUX : STD_LOGIC_VECTOR);
    Port ( RST : in STD_LOGIC;
           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
end Etage3_Calcul;

architecture Structural of Etage3_Calcul is
    component ALU is
    Generic (Nb_bits : Natural);
    Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           OP : in STD_LOGIC_VECTOR (2 downto 0);
           S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
           Z : out STD_LOGIC;
           C : out STD_LOGIC);
    end component;
    
    component LC is
        Generic (Instruction_Vector_Size : Natural;
                Command_size : Natural;
                Bits_Controle : STD_LOGIC_VECTOR);
        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
               Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
    end component;
    
    component MUX is
        Generic (Nb_bits : Natural;
                Instruction_Vector_Size : Natural;
                Bits_Controle : STD_LOGIC_VECTOR);
        Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
               IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
               OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
    end component;
    
    signal OP_ALU : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
    signal Sortie_ALU : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    
    signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
    signal intern_N : STD_LOGIC := '0';
    signal intern_O : STD_LOGIC := '0';
    signal intern_Z : STD_LOGIC := '0';
    signal intern_C : STD_LOGIC := '0';
    
    
begin
    instance_LC : LC
    generic map (Instruction_Vector_Size => Instruction_bus_size,
                 Command_size => 3,
                 Bits_Controle => Bits_Controle_LC)
    port map (   Instruction => IN_Instruction,
                 Commande => OP_ALU);
                 
    instance_MUX : MUX
    generic map (Nb_bits => Nb_bits,
                 Instruction_Vector_Size => Instruction_bus_size,
                 Bits_Controle => Bits_Controle_MUX)
    port map (   Instruction => IN_Instruction,
                 IN1 => IN_B,
                 IN2 => Sortie_ALU,
                 OUTPUT => intern_OUT_B);

    instance_ALU : ALU
    generic map (Nb_bits => Nb_bits)
    port map    (A => IN_B,
                 B => IN_C,
                 OP => OP_ALU,
                 S => Sortie_ALU,
                 N => intern_N,
                 O => intern_O,
                 Z => intern_Z,
                 C => intern_C);
    
    OUT_A <= (others => '0') when RST = '0' else
             IN_A;
    OUT_B <= (others => '0') when RST = '0' else
             intern_OUT_B;
    OUT_Instruction <= (others => '0') when RST = '0' else
             IN_Instruction;
    N <= '0' when RST = '0' else
             intern_N;
    O <= '0' when RST = '0' else
             intern_O;
    Z <= '0' when RST = '0' else
             intern_Z;
    C <= '0' when RST = '0' else
             intern_C;
end Structural;