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TestBancRegistres.vhd 3.0KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 16.04.2021 12:58:02
  6. -- Design Name:
  7. -- Module Name: TestBancRegistres - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity TestBancRegistres is
  30. -- Port ( );
  31. end TestBancRegistres;
  32. architecture Behavioral of TestBancRegistres is
  33. component BancRegistres
  34. Generic (Nb_bits : Natural;
  35. Addr_size : Natural;
  36. Nb_regs : Natural);
  37. Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
  38. AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
  39. AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
  40. W : in STD_LOGIC;
  41. DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
  42. RST : in STD_LOGIC;
  43. CLK : in STD_LOGIC;
  44. QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
  45. QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
  46. end component;
  47. signal my_AddrA : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
  48. signal my_AddrB : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
  49. signal my_AddrW : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
  50. signal my_W : STD_LOGIC := '0';
  51. signal my_DATA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
  52. signal my_RST : STD_LOGIC := '0';
  53. signal my_CLK : STD_LOGIC := '0';
  54. signal my_QA : STD_LOGIC_VECTOR (7 downto 0);
  55. signal my_QB : STD_LOGIC_VECTOR (7 downto 0);
  56. constant CLK_period : time := 10 ns;
  57. begin
  58. instance : BancRegistres
  59. generic map (Nb_bits => 8,
  60. Addr_size => 2,
  61. Nb_regs => 4
  62. )
  63. port map (
  64. AddrA => my_AddrA,
  65. AddrB => my_AddrB,
  66. AddrW => my_AddrW,
  67. W => my_W,
  68. DATA => my_DATA,
  69. RST => my_RST,
  70. CLK => my_CLK,
  71. QA => my_QA,
  72. QB => my_QB
  73. );
  74. CLK_process :process
  75. begin
  76. my_CLK <= '0';
  77. wait for CLK_period/2;
  78. my_CLK <= '1';
  79. wait for CLK_period/2;
  80. end process;
  81. process
  82. begin
  83. my_RST <= '1' after 0 ns, '0' after 100 ns;
  84. my_AddrA <= "11" after 20 ns, "00" after 50 ns;
  85. my_AddrB <= "11" after 30 ns;
  86. my_AddrW <= "11" after 10 ns, "00" after 50 ns;
  87. my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 60 ns, '1' after 110 ns;
  88. my_DATA <= "01010101" after 10 ns, "11111111" after 50 ns;
  89. wait;
  90. end process;
  91. end Behavioral;