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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 16.04.2021 12:58:02
- -- Design Name:
- -- Module Name: TestBancRegistres - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity TestBancRegistres is
- -- Port ( );
- end TestBancRegistres;
-
- architecture Behavioral of TestBancRegistres is
- component BancRegistres
- Generic (Nb_bits : Natural;
- Addr_size : Natural;
- Nb_regs : Natural);
- Port ( AddrA : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
- AddrB : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
- AddrW : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
- W : in STD_LOGIC;
- DATA : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
- RST : in STD_LOGIC;
- CLK : in STD_LOGIC;
- QA : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
- QB : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
- end component;
-
- signal my_AddrA : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
- signal my_AddrB : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
- signal my_AddrW : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
- signal my_W : STD_LOGIC := '0';
- signal my_DATA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
- signal my_RST : STD_LOGIC := '0';
- signal my_CLK : STD_LOGIC := '0';
- signal my_QA : STD_LOGIC_VECTOR (7 downto 0);
- signal my_QB : STD_LOGIC_VECTOR (7 downto 0);
-
- constant CLK_period : time := 10 ns;
-
- begin
-
- instance : BancRegistres
- generic map (Nb_bits => 8,
- Addr_size => 2,
- Nb_regs => 4
- )
- port map (
- AddrA => my_AddrA,
- AddrB => my_AddrB,
- AddrW => my_AddrW,
- W => my_W,
- DATA => my_DATA,
- RST => my_RST,
- CLK => my_CLK,
- QA => my_QA,
- QB => my_QB
- );
-
- CLK_process :process
- begin
- my_CLK <= '0';
- wait for CLK_period/2;
- my_CLK <= '1';
- wait for CLK_period/2;
- end process;
-
- process
- begin
- my_RST <= '1' after 0 ns, '0' after 100 ns;
- my_AddrA <= "11" after 20 ns, "00" after 50 ns;
- my_AddrB <= "11" after 30 ns;
- my_AddrW <= "11" after 10 ns, "00" after 50 ns;
- my_W <= '1' after 10 ns, '0' after 20 ns, '1' after 50 ns, '0' after 60 ns, '1' after 110 ns;
- my_DATA <= "01010101" after 10 ns, "11111111" after 50 ns;
-
- wait;
- end process;
- end Behavioral;
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