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TestMemoireDonnees.vhd 2.5KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 16.04.2021 12:58:02
  6. -- Design Name:
  7. -- Module Name: TestMemoireDonnees - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity TestMemoireDonnees is
  30. -- Port ( );
  31. end TestMemoireDonnees;
  32. architecture Behavioral of TestMemoireDonnees is
  33. component MemoireDonnees is
  34. Generic (Nb_bits : Natural;
  35. Addr_size : Natural;
  36. Mem_size : Natural);
  37. Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
  38. RW : in STD_LOGIC;
  39. D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
  40. RST : in STD_LOGIC;
  41. CLK : in STD_LOGIC;
  42. D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
  43. end component;
  44. signal my_Addr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
  45. signal my_RW : STD_LOGIC := '1';
  46. signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
  47. signal my_RST : STD_LOGIC := '0';
  48. signal my_CLK : STD_LOGIC := '0';
  49. signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
  50. constant CLK_period : time := 10 ns;
  51. begin
  52. instance : MemoireDonnees
  53. generic map (Nb_bits => 8,
  54. Addr_size => 2,
  55. Mem_size => 4
  56. )
  57. port map (
  58. Addr => my_Addr,
  59. RW => my_RW,
  60. D_IN => my_D_IN,
  61. RST => my_RST,
  62. CLK => my_CLK,
  63. D_OUT => my_D_OUT
  64. );
  65. CLK_process :process
  66. begin
  67. my_CLK <= '0';
  68. wait for CLK_period/2;
  69. my_CLK <= '1';
  70. wait for CLK_period/2;
  71. end process;
  72. process
  73. begin
  74. my_RST <= '1' after 0 ns, '0' after 100 ns;
  75. my_RW <= '1' after 0 ns, '0' after 10 ns, '1' after 30 ns;
  76. my_Addr <= "01" after 10 ns, "10" after 20 ns, "11" after 40 ns, "01" after 70 ns;
  77. my_D_IN <= "01010101" after 10 ns, "11100111" after 20 ns, "11111111" after 50 ns;
  78. wait;
  79. end process;
  80. end Behavioral;