123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293 |
- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 16.04.2021 12:58:02
- -- Design Name:
- -- Module Name: TestMemoireDonnees - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity TestMemoireDonnees is
- -- Port ( );
- end TestMemoireDonnees;
-
- architecture Behavioral of TestMemoireDonnees is
- component MemoireDonnees is
- Generic (Nb_bits : Natural;
- Addr_size : Natural;
- Mem_size : Natural);
- Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
- RW : in STD_LOGIC;
- D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
- RST : in STD_LOGIC;
- CLK : in STD_LOGIC;
- D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0));
- end component;
-
- signal my_Addr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
- signal my_RW : STD_LOGIC := '1';
- signal my_D_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
- signal my_RST : STD_LOGIC := '0';
- signal my_CLK : STD_LOGIC := '0';
- signal my_D_OUT : STD_LOGIC_VECTOR (7 downto 0);
-
- constant CLK_period : time := 10 ns;
-
- begin
-
- instance : MemoireDonnees
- generic map (Nb_bits => 8,
- Addr_size => 2,
- Mem_size => 4
- )
- port map (
- Addr => my_Addr,
- RW => my_RW,
- D_IN => my_D_IN,
- RST => my_RST,
- CLK => my_CLK,
- D_OUT => my_D_OUT
- );
-
- CLK_process :process
- begin
- my_CLK <= '0';
- wait for CLK_period/2;
- my_CLK <= '1';
- wait for CLK_period/2;
- end process;
-
- process
- begin
- my_RST <= '1' after 0 ns, '0' after 100 ns;
- my_RW <= '1' after 0 ns, '0' after 10 ns, '1' after 30 ns;
- my_Addr <= "01" after 10 ns, "10" after 20 ns, "11" after 40 ns, "01" after 70 ns;
- my_D_IN <= "01010101" after 10 ns, "11100111" after 20 ns, "11111111" after 50 ns;
-
- wait;
- end process;
- end Behavioral;
|