rlacroix/Projet-Systemes-Informatiques
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Author SHA1 Message Date
Raphaël LACROIX
52ea586362 fixed missing store in post process 2023-05-31 22:01:23 +02:00
Raphaël LACROIX
eb384e3018 wrapped import in order to check for the installation of packages 2023-05-31 22:00:18 +02:00
Raphaël LACROIX
4529d87b04 Added vhdl/inter make options 2023-05-31 21:59:52 +02:00
Raphaël LACROIX
0642e1bab6 Added fibonacci test file 2023-05-31 21:59:39 +02:00
Raphaël LACROIX
365376fcfd asm for previous commit's testFile 2023-05-31 16:48:24 +02:00
Raphaël LACROIX
cb61c7d395 testFile with fibonacci program 2023-05-31 16:47:20 +02:00
Raphaël LACROIX
62f9580aee added style.css (the graphical interpreter's stylesheet) because code is better when it looks cool 2023-05-31 16:46:49 +02:00
Raphaël LACROIX
cf04e317f7 Merge remote-tracking branch 'origin/master' 2023-05-31 16:45:53 +02:00
Raphaël LACROIX
c8f53d34b8 fixed the yacc JMF without boolean variable 2023-05-31 16:45:03 +02:00
Raphaël LACROIX
2c9bb64de1 added the new interpreters 2023-05-31 16:44:29 +02:00
Lacroix Raphael
834c2b01df added jmp, jmf support, speculative execution of LI DI then flushing, boolean conditions 2023-05-30 16:29:31 +02:00
Lacroix Raphael
576b41da4d fixed data path and aleas 2023-05-30 13:38:05 +02:00
Lacroix Raphael
8a7685b049 xilinx generqted files 2023-05-30 08:46:35 +02:00
Lacroix Raphael
1a7e84b6d3 started preparing tests 2023-05-30 00:49:56 +02:00
Raphaël LACROIX
f6a33bfaf0 Merge remote-tracking branch 'origin/master' 
# Conflicts:
#	VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
 2023-05-29 23:49:23 +02:00
Raphaël LACROIX
b6c719eb89 the rest of the ams steps 2023-05-29 23:47:17 +02:00
Raphaël LACROIX
c0b06b9565 added hardcoded operations (from cross compiler) in the InstructionMemory.vhd 2023-05-29 23:46:32 +02:00
Raphaël LACROIX
68b0a2ea01 added new testfiles 2023-05-29 23:45:50 +02:00
Raphaël LACROIX
3885da0ea5 added more operand (again) 2023-05-29 23:45:26 +02:00
Raphaël LACROIX
e621b754bf finished cross compiler for test 2023-05-29 23:43:29 +02:00
Raphaël LACROIX
8f5be60008 updated opcodes 2023-05-29 23:43:05 +02:00
Lacroix Raphael
c462cd7fe7 WIP tried stuff 2023-05-29 21:57:46 +02:00
Lacroix Raphael
12859bebe9 Merge remote-tracking branch 'origin/master' 
# Conflicts:
#	VHDL/ALU/ALU.cache/wt/project.wpc
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb
#	VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
 2023-05-29 21:42:46 +02:00
alejeune
134db4c2c9 Update ALU 2023-05-29 21:39:05 +02:00
Lacroix Raphael
474ba6b265 added test files for full CPU 2023-05-29 21:37:49 +02:00
Raphaël LACROIX
873502243b Merge remote-tracking branch 'origin/ALU' 2023-05-29 20:33:37 +02:00
alejeune
6997cf24e8 work in progress ALU 2023-05-29 20:30:32 +02:00
Raphaël LACROIX
ae447be456 added the alea handling and IP implementation 2023-05-29 19:54:40 +02:00
alejeune
46465784b8 added IP 2023-05-29 14:28:17 +02:00
alejeune
ce3fda3a4e Merge branch 'master' of https://git.etud.insa-toulouse.fr/rlacroix/Projet-Systemes-Informatiques 2023-05-29 13:59:24 +02:00
alejeune
22c945e716 Added VHDL part of the project 2023-05-29 13:58:26 +02:00
Raphaël LACROIX
c369d180b0 branch merge 2023-05-12 16:03:47 +02:00
Raphaël LACROIX
019a8c506e corrected typo in yacc 2023-05-12 16:03:28 +02:00
alejeune
1f8fa678bc Added translation registers (2) 2023-05-12 15:57:55 +02:00
alejeune
f006ac975a Added translation registers 2023-05-12 15:43:03 +02:00
alejeune
360f3d29eb Added translation registers 2023-05-12 15:37:57 +02:00
Raphaël LACROIX
88cc4fe7e7 first draft of the script to translate the code 2023-05-04 12:15:28 +02:00
Raphaël LACROIX
f3ac463013 updated asm format 2023-05-04 12:14:50 +02:00
Raphaël LACROIX
c34150e026 final conditions and loops tested 2023-04-20 11:48:47 +02:00
Raphaël LACROIX
ff74c5be44 While done (and tested) 2023-04-20 11:29:52 +02:00
alejeune
6661eb3865 Added conditional functions 2023-04-20 11:12:14 +02:00
Raphaël LACROIX
b354d938ea While done 2023-04-20 11:05:52 +02:00
Raphaël LACROIX
6927b7da82 If Done (and todo cleaned up) 2023-04-20 10:23:57 +02:00
Raphaël LACROIX
358e98d6d6 If Done 2023-04-20 10:23:32 +02:00
Raphaël LACROIX
18f64a1653 NOT A COMMIT 2023-04-20 08:15:13 +02:00
Raphaël LACROIX
39bad0048b changed asmTable way 2023-04-18 16:55:52 +02:00
Raphaël LACROIX
86af52f0ac added basic asmTable functionalities 2023-04-18 16:27:50 +02:00
Raphaël LACROIX
c71e340389 NOT REAL PUSH 2023-04-18 16:13:40 +02:00
Raphaël LACROIX
5d7d2a82f9 removed old files 2023-04-18 11:45:30 +02:00
Raphaël LACROIX
ced95f1a97 updated gitignore and blocs 2023-04-18 11:44:32 +02:00