Added VHDL part of the project
This commit is contained in:
alejeune
parent
1f8fa678bc
commit
22c945e716
96 changed files with 3209 additions and 0 deletions
55
VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
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55
VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
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version:1
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eof:3153781590
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12
VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
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VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
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version:1
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eof:2164592515
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VHDL/ALU/ALU.cache/wt/project.wpc
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VHDL/ALU/ALU.cache/wt/project.wpc
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version:1
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eof:
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VHDL/ALU/ALU.cache/wt/synthesis.wdf
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VHDL/ALU/ALU.cache/wt/synthesis.wdf
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313433342e3033314d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3237342e3230374d42:00:00
|
||||
eof:3465561614
|
||||
3
VHDL/ALU/ALU.cache/wt/synthesis_details.wdf
Normal file
3
VHDL/ALU/ALU.cache/wt/synthesis_details.wdf
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
version:1
|
||||
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
|
||||
eof:2511430288
|
||||
93
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
Normal file
93
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Mon May 29 13:52:52 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="4" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="14" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="2" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="2" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="3" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="6" type="JavaHandler"/>
|
||||
<property name="SimulationRelaunch" value="3" type="JavaHandler"/>
|
||||
<property name="SimulationRun" value="27" type="JavaHandler"/>
|
||||
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
|
||||
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
|
||||
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="6" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="40" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="12" type="GuiHandlerData"/>
|
||||
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
|
||||
<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="159" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="35" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_FIT" value="2" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_IN" value="13" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_OUT" value="21" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_CHECKPOINT" value="14" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EDIT" value="6" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="44" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="7" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="12" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="29" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="12" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TEXT_EDITOR" value="6" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="6" type="GuiHandlerData"/>
|
||||
<property name="OpenFileAction_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="OpenFileAction_OPEN_DIRECTORY" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="26" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="13" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
|
||||
<property name="RDIViews_WAVEFORM_VIEWER" value="79" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="15" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="12" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
|
||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="36" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_NEXT_MARKER" value="2" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="16" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="10" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
4
VHDL/ALU/ALU.cache/wt/xsim.wdf
Normal file
4
VHDL/ALU/ALU.cache/wt/xsim.wdf
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
version:1
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
|
||||
eof:241934075
|
||||
6
VHDL/ALU/ALU.hw/ALU.lpr
Normal file
6
VHDL/ALU/ALU.hw/ALU.lpr
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
1
VHDL/ALU/ALU.ip_user_files/README.txt
Normal file
1
VHDL/ALU/ALU.ip_user_files/README.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
</Runs>
|
||||
|
||||
0
VHDL/ALU/ALU.runs/synth_1/.Vivado_Synthesis.queue.rst
Normal file
0
VHDL/ALU/ALU.runs/synth_1/.Vivado_Synthesis.queue.rst
Normal file
5
VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst
Normal file
5
VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="alejeune" Host="" Pid="846704">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
0
VHDL/ALU/ALU.runs/synth_1/.vivado.end.rst
Normal file
0
VHDL/ALU/ALU.runs/synth_1/.vivado.end.rst
Normal file
BIN
VHDL/ALU/ALU.runs/synth_1/ALU.dcp
Normal file
BIN
VHDL/ALU/ALU.runs/synth_1/ALU.dcp
Normal file
Binary file not shown.
52
VHDL/ALU/ALU.runs/synth_1/ALU.tcl
Normal file
52
VHDL/ALU/ALU.runs/synth_1/ALU.tcl
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
create_project -in_memory -part xc7a35tcpg236-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project]
|
||||
set_property parent.project_path /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
|
||||
set_property ip_output_repo /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_vhdl -library xil_defaultlib /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 0
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top ALU -part xc7a35tcpg236-1
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef ALU.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
238
VHDL/ALU/ALU.runs/synth_1/ALU.vds
Normal file
238
VHDL/ALU/ALU.runs/synth_1/ALU.vds
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
#-----------------------------------------------------------
|
||||
# Vivado v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:48:29 2023
|
||||
# Process ID: 846737
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
||||
# Command line: vivado -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.vds
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source ALU.tcl -notrace
|
||||
Command: synth_design -top ALU -part xc7a35tcpg236-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 846814
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcpg236-1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module ALU
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |CARRY4 | 18|
|
||||
|2 |LUT2 | 31|
|
||||
|3 |LUT3 | 6|
|
||||
|4 |LUT4 | 41|
|
||||
|5 |LUT5 | 12|
|
||||
|6 |LUT6 | 52|
|
||||
|7 |LD | 16|
|
||||
|8 |IBUF | 19|
|
||||
|9 |OBUF | 12|
|
||||
+------+-------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 207|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 16 instances were transformed.
|
||||
LD => LDCE: 16 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596
|
||||
WARNING: [Constraints 18-5210] No constraint will be written out.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023...
|
||||
BIN
VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.pb
Normal file
BIN
VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.pb
Normal file
Binary file not shown.
179
VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.rpt
Normal file
179
VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.rpt
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
|
||||
| Date : Sun May 14 22:49:12 2023
|
||||
| Host : srv-tp06 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
|
||||
| Design : ALU
|
||||
| Device : 7a35tcpg236-1
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 120 | 0 | 20800 | 0.58 |
|
||||
| LUT as Logic | 120 | 0 | 20800 | 0.58 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 16 | 0 | 41600 | 0.04 |
|
||||
| Register as Flip Flop | 0 | 0 | 41600 | 0.00 |
|
||||
| Register as Latch | 16 | 0 | 41600 | 0.04 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 16 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 31 | 0 | 106 | 29.25 |
|
||||
| Bonded IPADs | 0 | 0 | 10 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 4 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 104 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 106 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 106 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 52 | LUT |
|
||||
| LUT4 | 41 | LUT |
|
||||
| LUT2 | 31 | LUT |
|
||||
| IBUF | 19 | IO |
|
||||
| CARRY4 | 18 | CarryLogic |
|
||||
| LDCE | 16 | Flop & Latch |
|
||||
| OBUF | 12 | IO |
|
||||
| LUT5 | 12 | LUT |
|
||||
| LUT3 | 6 | LUT |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
244
VHDL/ALU/ALU.runs/synth_1/ISEWrap.js
Executable file
244
VHDL/ALU/ALU.runs/synth_1/ISEWrap.js
Executable file
|
|
@ -0,0 +1,244 @@
|
|||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
63
VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh
Executable file
63
VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh
Executable file
|
|
@ -0,0 +1,63 @@
|
|||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
0
VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__
Normal file
0
VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__
Normal file
33
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
Normal file
33
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
|
||||
<File Type="PA-TCL" Name="ALU.tcl"/>
|
||||
<File Type="RDS-DCP" Name="ALU.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ALU.vds"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ALU_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ALU_utilization_synth.rpt"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
VHDL/ALU/ALU.runs/synth_1/htr.txt
Normal file
9
VHDL/ALU/ALU.runs/synth_1/htr.txt
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
31
VHDL/ALU/ALU.runs/synth_1/project.wdf
Normal file
31
VHDL/ALU/ALU.runs/synth_1/project.wdf
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00
|
||||
eof:2773257219
|
||||
40
VHDL/ALU/ALU.runs/synth_1/rundef.js
Normal file
40
VHDL/ALU/ALU.runs/synth_1/rundef.js
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;";
|
||||
} else {
|
||||
PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
11
VHDL/ALU/ALU.runs/synth_1/runme.bat
Normal file
11
VHDL/ALU/ALU.runs/synth_1/runme.bat
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
237
VHDL/ALU/ALU.runs/synth_1/runme.log
Normal file
237
VHDL/ALU/ALU.runs/synth_1/runme.log
Normal file
|
|
@ -0,0 +1,237 @@
|
|||
|
||||
*** Running vivado
|
||||
with args -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
|
||||
|
||||
****** Vivado v2018.2 (64-bit)
|
||||
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source ALU.tcl -notrace
|
||||
Command: synth_design -top ALU -part xc7a35tcpg236-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 846814
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcpg236-1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module ALU
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |CARRY4 | 18|
|
||||
|2 |LUT2 | 31|
|
||||
|3 |LUT3 | 6|
|
||||
|4 |LUT4 | 41|
|
||||
|5 |LUT5 | 12|
|
||||
|6 |LUT6 | 52|
|
||||
|7 |LD | 16|
|
||||
|8 |IBUF | 19|
|
||||
|9 |OBUF | 12|
|
||||
+------+-------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 207|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 16 instances were transformed.
|
||||
LD => LDCE: 16 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596
|
||||
WARNING: [Constraints 18-5210] No constraint will be written out.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023...
|
||||
39
VHDL/ALU/ALU.runs/synth_1/runme.sh
Executable file
39
VHDL/ALU/ALU.runs/synth_1/runme.sh
Executable file
|
|
@ -0,0 +1,39 @@
|
|||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin
|
||||
else
|
||||
PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64
|
||||
else
|
||||
LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
12
VHDL/ALU/ALU.runs/synth_1/vivado.jou
Normal file
12
VHDL/ALU/ALU.runs/synth_1/vivado.jou
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# Vivado v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:48:29 2023
|
||||
# Process ID: 846737
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
||||
# Command line: vivado -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.vds
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source ALU.tcl -notrace
|
||||
BIN
VHDL/ALU/ALU.runs/synth_1/vivado.pb
Normal file
BIN
VHDL/ALU/ALU.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl
Normal file
11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
Normal file
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
Normal file
Binary file not shown.
7
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj
Normal file
7
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
# compile vhdl design source files
|
||||
vhdl xil_defaultlib \
|
||||
"../../../../ALU.srcs/sources_1/new/ALU.vhd" \
|
||||
"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
55
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
Normal file
55
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity ALU
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity ALU
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity ALU
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity ALU
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity ALU
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:88]
|
||||
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
|
||||
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
27
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
Executable file
27
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
Executable file
|
|
@ -0,0 +1,27 @@
|
|||
#!/bin/bash -f
|
||||
# ****************************************************************************
|
||||
# Vivado (TM) v2018.2 (64-bit)
|
||||
#
|
||||
# Filename : compile.sh
|
||||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Script for compiling the simulation design source files
|
||||
#
|
||||
# Generated by Vivado on Mon May 15 12:53:49 CEST 2023
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
#
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: compile.sh
|
||||
#
|
||||
# ****************************************************************************
|
||||
ExecStep()
|
||||
{
|
||||
"$@"
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -ne 0 ]
|
||||
then
|
||||
exit $RETVAL
|
||||
fi
|
||||
}
|
||||
echo "xvhdl --incr --relax -prj Test_Alu_vhdl.prj"
|
||||
ExecStep xvhdl --incr --relax -prj Test_Alu_vhdl.prj 2>&1 | tee -a compile.log
|
||||
17
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
Normal file
17
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
Vivado Simulator 2018.2
|
||||
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
||||
Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log
|
||||
Using 8 slave threads.
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling package ieee.std_logic_arith
|
||||
Compiling package ieee.std_logic_unsigned
|
||||
Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.test_alu
|
||||
Built simulation snapshot Test_Alu_behav
|
||||
26
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
Executable file
26
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
Executable file
|
|
@ -0,0 +1,26 @@
|
|||
#!/bin/bash -f
|
||||
# ****************************************************************************
|
||||
# Vivado (TM) v2018.2 (64-bit)
|
||||
#
|
||||
# Filename : elaborate.sh
|
||||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Script for elaborating the compiled design
|
||||
#
|
||||
# Generated by Vivado on Mon May 15 12:53:50 CEST 2023
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
#
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: elaborate.sh
|
||||
#
|
||||
# ****************************************************************************
|
||||
ExecStep()
|
||||
{
|
||||
"$@"
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -ne 0 ]
|
||||
then
|
||||
exit $RETVAL
|
||||
fi
|
||||
}
|
||||
ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log
|
||||
2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log
Normal file
2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
Vivado Simulator 2018.2
|
||||
Time resolution is 1 ps
|
||||
26
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
Executable file
26
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
Executable file
|
|
@ -0,0 +1,26 @@
|
|||
#!/bin/bash -f
|
||||
# ****************************************************************************
|
||||
# Vivado (TM) v2018.2 (64-bit)
|
||||
#
|
||||
# Filename : simulate.sh
|
||||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Script for simulating the design by launching the simulator
|
||||
#
|
||||
# Generated by Vivado on Mon May 15 12:53:51 CEST 2023
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
#
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: simulate.sh
|
||||
#
|
||||
# ****************************************************************************
|
||||
ExecStep()
|
||||
{
|
||||
"$@"
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -ne 0 ]
|
||||
then
|
||||
exit $RETVAL
|
||||
fi
|
||||
}
|
||||
ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log
|
||||
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
Normal file
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:27:26 2023
|
||||
# Process ID: 831441
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
Normal file
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:27:26 2023
|
||||
# Process ID: 831441
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:27 2023...
|
||||
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou
Normal file
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Fri May 12 18:00:54 2023
|
||||
# Process ID: 31637
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log
Normal file
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Fri May 12 18:00:54 2023
|
||||
# Process ID: 31637
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
INFO: [Common 17-206] Exiting Webtalk at Fri May 12 18:00:55 2023...
|
||||
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou
Normal file
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Fri May 12 18:03:10 2023
|
||||
# Process ID: 32017
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log
Normal file
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Fri May 12 18:03:10 2023
|
||||
# Process ID: 32017
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
INFO: [Common 17-206] Exiting Webtalk at Fri May 12 18:03:11 2023...
|
||||
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou
Normal file
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:27:00 2023
|
||||
# Process ID: 831173
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log
Normal file
13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:27:00 2023
|
||||
# Process ID: 831173
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:01 2023...
|
||||
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
Normal file
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
Normal file
Binary file not shown.
|
|
@ -0,0 +1 @@
|
|||
-wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Test_Alu_behav" "xil_defaultlib.Test_Alu" -log "elaborate.log"
|
||||
|
|
@ -0,0 +1 @@
|
|||
Breakpoint File Version 1.0
|
||||
Binary file not shown.
|
|
@ -0,0 +1,106 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern void execute_38(char*, char *);
|
||||
extern void execute_39(char*, char *);
|
||||
extern void execute_40(char*, char *);
|
||||
extern void execute_32(char*, char *);
|
||||
extern void execute_33(char*, char *);
|
||||
extern void execute_34(char*, char *);
|
||||
extern void execute_35(char*, char *);
|
||||
extern void execute_36(char*, char *);
|
||||
extern void execute_37(char*, char *);
|
||||
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[10] = {(funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)vhdl_transfunc_eventcallback};
|
||||
const int NumRelocateId= 10;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 10);
|
||||
iki_vhdl_file_variable_register(dp + 3576);
|
||||
iki_vhdl_file_variable_register(dp + 3632);
|
||||
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/Test_Alu_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/Test_Alu_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/Test_Alu_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/Test_Alu_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/Test_Alu_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
|
|
@ -0,0 +1,5 @@
|
|||
1684096019
|
||||
1684096045
|
||||
51
|
||||
1
|
||||
aef36ef3a0d94dac9e6058b656907afd
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2258646</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Sun May 14 22:27:25 2023</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>LIN64</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2018.2 (64-bit)</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>aef36ef3a0d94dac9e6058b656907afd</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>12</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>48ade6b1-45bb-42c1-b620-33b3e004d501</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>48ade6b1-45bb-42c1-b620-33b3e004d501</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>800.000 MHz</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Ubuntu</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>Ubuntu 20.04.6 LTS</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>134.000 GB</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>2</TD>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>iteration=0</TD>
|
||||
<TD>runtime=1 us</TD>
|
||||
<TD>simulation_memory=122600_KB</TD>
|
||||
<TD>simulation_time=0.03_sec</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
version = "1.0";
|
||||
clients =
|
||||
(
|
||||
{ client_name = "project";
|
||||
rules = (
|
||||
{
|
||||
context="software_version_and_target_device";
|
||||
xml_map="software_version_and_target_device";
|
||||
html_map="software_version_and_target_device";
|
||||
html_format="UserEnvStyle";
|
||||
},
|
||||
{
|
||||
context="user_environment";
|
||||
xml_map="user_environment";
|
||||
html_map="user_environment";
|
||||
html_format="UserEnvStyle";
|
||||
}
|
||||
);
|
||||
},
|
||||
|
||||
{ client_name = "xsim";
|
||||
rules = (
|
||||
{
|
||||
context="xsim\\command_line_options";
|
||||
xml_map="xsim\\command_line_options";
|
||||
html_map="xsim\\command_line_options";
|
||||
html_format="UnisimStatsStyle";
|
||||
},
|
||||
{
|
||||
context="xsim\\usage";
|
||||
xml_map="xsim\\usage";
|
||||
html_map="xsim\\usage";
|
||||
html_format="UnisimStatsStyle";
|
||||
}
|
||||
);
|
||||
}
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sun May 14 22:27:26 2023'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2258646" description="" />
|
||||
<keyValuePair key="date_generated" value="Sun May 14 22:27:25 2023" description="" />
|
||||
<keyValuePair key="os_platform" value="LIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.2 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="aef36ef3a0d94dac9e6058b656907afd" description="" />
|
||||
<keyValuePair key="project_iteration" value="12" description="" />
|
||||
<keyValuePair key="random_id" value="48ade6b1-45bb-42c1-b620-33b3e004d501" description="" />
|
||||
<keyValuePair key="registration_id" value="48ade6b1-45bb-42c1-b620-33b3e004d501" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="800.000 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Ubuntu" description="" />
|
||||
<keyValuePair key="os_release" value="Ubuntu 20.04.6 LTS" description="" />
|
||||
<keyValuePair key="system_ram" value="134.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="2" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xsim" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="iteration" value="0" description="" />
|
||||
<keyValuePair key="runtime" value="1 us" description="" />
|
||||
<keyValuePair key="simulation_memory" value="122600_KB" description="" />
|
||||
<keyValuePair key="simulation_time" value="0.03_sec" description="" />
|
||||
<keyValuePair key="trace_waveform" value="true" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Mon May 15 14:24:45 2023" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "50" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "3200.000 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Memory -value "122600_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 2250690028 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,12 @@
|
|||
|
||||
{
|
||||
crc : 117194062558042768 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" ,
|
||||
buildDate : "Jun 14 2018" ,
|
||||
buildTime : "20:07:38" ,
|
||||
linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Test_Alu_behav/xsimk\" \"xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simulator_kernel.so\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simbridge_kernel.so\"" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,41 @@
|
|||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=1024
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=65536
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=75
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
|
||||
OBJECT_NAME_COLUMN_WIDTH=75
|
||||
OBJECT_VALUE_COLUMN_WIDTH=75
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=75
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
Executable file
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
Executable file
Binary file not shown.
|
|
@ -0,0 +1,7 @@
|
|||
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 45953
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 32664 KB (Peak: 32724 KB)
|
||||
Design Loading CPU Usage: 10 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 122600 KB (Peak: 179936 KB)
|
||||
Simulation CPU Usage: 10 ms
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,6 @@
|
|||
0.6
|
||||
2018.2
|
||||
Jun 14 2018
|
||||
20:07:38
|
||||
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1684148028,vhdl,,,,test_alu,,,,,,,,
|
||||
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1684096722,vhdl,,,,alu,,,,,,,,
|
||||
1
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini
Normal file
1
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini
Normal file
|
|
@ -0,0 +1 @@
|
|||
xil_defaultlib=xsim.dir/xil_defaultlib
|
||||
2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log
Normal file
2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_Alu
|
||||
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb
Normal file
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb
Normal file
Binary file not shown.
107
VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd
Normal file
107
VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12.05.2023 17:40:52
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Alu - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_Alu is
|
||||
-- Port ( );
|
||||
end Test_Alu;
|
||||
|
||||
architecture Behavioral of Test_Alu is
|
||||
|
||||
|
||||
component ALU
|
||||
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
|
||||
S : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
-- inputs
|
||||
signal local_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal local_Ctrl_Alu : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
|
||||
|
||||
--outputs
|
||||
signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal local_N : STD_LOGIC := '0';
|
||||
signal local_O : STD_LOGIC := '0';
|
||||
signal local_Z : STD_LOGIC := '0';
|
||||
signal local_C : STD_LOGIC := '0';
|
||||
|
||||
-- constant Clock_period : time := 10ns;
|
||||
|
||||
begin
|
||||
|
||||
-- instantiate
|
||||
instance : ALU PORT MAP (
|
||||
A => local_A,
|
||||
B => local_B,
|
||||
Ctrl_Alu => local_Ctrl_Alu,
|
||||
S => local_S,
|
||||
N => local_N,
|
||||
O => local_O,
|
||||
Z => local_Z,
|
||||
C => local_C
|
||||
);
|
||||
|
||||
local_Ctrl_Alu <= "000",
|
||||
"001" after 20 ns,
|
||||
"010" after 30 ns,
|
||||
"100" after 40 ns,
|
||||
"001" after 50 ns, -- test Z flag
|
||||
"000" after 60 ns, -- test C flag
|
||||
"010" after 70 ns; -- test O flag
|
||||
|
||||
local_A <= x"00",
|
||||
x"10" after 10 ns,
|
||||
x"a2" after 20 ns,
|
||||
x"12" after 30 ns,
|
||||
x"18" after 40 ns,
|
||||
x"19" after 50 ns,
|
||||
"10000000" after 60 ns;
|
||||
|
||||
local_B <= x"00",
|
||||
x"78" after 10 ns,
|
||||
x"b9" after 20 ns,
|
||||
x"02" after 30 ns,
|
||||
x"a2" after 40 ns,
|
||||
x"19" after 50 ns,
|
||||
"10000000" after 60 ns;
|
||||
|
||||
|
||||
|
||||
|
||||
end Behavioral;
|
||||
58
VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
Normal file
58
VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12.05.2023 16:14:24
|
||||
-- Design Name:
|
||||
-- Module Name: ALU - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity ALU is
|
||||
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
|
||||
S : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end ALU;
|
||||
|
||||
architecture Behavioral of ALU is
|
||||
signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";
|
||||
begin
|
||||
res <= (x"00" & A) + (x"00" & B) when (Ctrl_Alu = "000") else
|
||||
(x"00" & A) - (x"00" & B) when (Ctrl_Alu = "001") else
|
||||
A * B when (Ctrl_Alu = "010"); -- else
|
||||
-- A mod B when (Ctrl_Alu = "100");
|
||||
S <= res(7 downto 0);
|
||||
N <= '1' when B > A and Ctrl_Alu="001" else '0';
|
||||
O <= '1' when res(15 downto 8) > x"01" and Ctrl_Alu="010" else '0';
|
||||
Z <= '1' when res(15 downto 0) = x"0" else '0';
|
||||
C <= '1' when res(8)='1' and (Ctrl_Alu = "000") else '0';
|
||||
end Behavioral;
|
||||
52
VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd
Normal file
52
VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 13:55:29
|
||||
-- Design Name:
|
||||
-- Module Name: InstructionMemory - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity InstructionMemory is
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
|
||||
end InstructionMemory;
|
||||
|
||||
architecture Behavioral of InstructionMemory is
|
||||
type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0);
|
||||
signal Mem : Mem_array;
|
||||
begin
|
||||
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
Inst_out <= Mem(to_integer(unsigned(Addr)));
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
63
VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd
Normal file
63
VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 13:37:41
|
||||
-- Design Name:
|
||||
-- Module Name: DataMemory - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity DataMemory is
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Data_in : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Rw : in STD_LOGIC;
|
||||
Rst : in STD_LOGIC;
|
||||
Clk : in STD_LOGIC;
|
||||
Data_out : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end DataMemory;
|
||||
|
||||
architecture Behavioral of DataMemory is
|
||||
type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
|
||||
signal Mem : Mem_array;
|
||||
begin
|
||||
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
if Rst = '0' then -- Reset
|
||||
mem <= (others => x"00");
|
||||
else if Rw = '1' then --reading
|
||||
Data_out <= Mem(to_integer(unsigned(Addr)));
|
||||
else -- writting
|
||||
Mem(to_integer(unsigned(Addr))) <= Data_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
287
VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
Normal file
287
VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
Normal file
|
|
@ -0,0 +1,287 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 14:29:58
|
||||
-- Design Name:
|
||||
-- Module Name: Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Pipeline is
|
||||
Port ( Clk : in STD_LOGIC);
|
||||
end Pipeline;
|
||||
|
||||
architecture Behavioral of Pipeline is
|
||||
|
||||
signal IP : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal Rst : STD_LOGIC; -- to modify
|
||||
|
||||
component InstructionMemory
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
|
||||
end component;
|
||||
|
||||
signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
|
||||
|
||||
component Stage_Li_Di
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_C : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal Li_A, Li_Op, Li_B, Li_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
|
||||
component Registers
|
||||
Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
Addr_B : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
Addr_W : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
W : in STD_LOGIC;
|
||||
Data : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Rst : in STD_LOGIC;
|
||||
Clk : in STD_LOGIC;
|
||||
QA : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
QB : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
|
||||
component Stage_Di_Ex
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_C : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
|
||||
component ALU
|
||||
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
|
||||
S : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
N : out STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
Z : out STD_LOGIC;
|
||||
C : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC;
|
||||
|
||||
component Stage_Ex_Mem
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal Mem_RW : STD_LOGIC;
|
||||
signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
|
||||
component DataMemory
|
||||
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Data_in : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Rw : in STD_LOGIC;
|
||||
Rst : in STD_LOGIC;
|
||||
Clk : in STD_LOGIC;
|
||||
Data_out : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end component;
|
||||
|
||||
component Stage_Mem_Re
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
signal Re_W : STD_LOGIC;
|
||||
|
||||
begin
|
||||
|
||||
-- instructionMemory
|
||||
MemInst : InstructionMemory PORT MAP (
|
||||
Addr => IP,
|
||||
Clk => Clk,
|
||||
Inst_out => Li);
|
||||
|
||||
-- Stage_Li_Di
|
||||
Stage1 : Stage_Li_Di PORT MAP (
|
||||
In_A => Li(23 downto 16),
|
||||
In_B => Li(15 downto 8),
|
||||
In_C => Li(7 downto 0),
|
||||
In_Op => Li(31 downto 24),
|
||||
Clk => Clk,
|
||||
Out_A => Di_A,
|
||||
Out_B => Di_B,
|
||||
Out_Op => Di_Op,
|
||||
Out_C => Di_C);
|
||||
|
||||
-- Registers
|
||||
StageRegisters : Registers PORT MAP (
|
||||
Addr_A => Di_B,
|
||||
Addr_B => Di_C,
|
||||
Addr_W => Re_A,
|
||||
W => Re_W,
|
||||
Data => Re_B,
|
||||
Rst => Rst,
|
||||
Clk => Clk,
|
||||
QA => Di_RegB,
|
||||
QB => Di_C2);
|
||||
|
||||
-- Stage DI/EX
|
||||
Stage2 : Stage_Di_Ex PORT MAP (
|
||||
In_A => Di_A,
|
||||
In_B => Di_FinalB,
|
||||
In_C => Di_C2,
|
||||
In_Op => Di_Op,
|
||||
Clk => Clk,
|
||||
Out_A => Ex_A,
|
||||
Out_B => Ex_B,
|
||||
Out_Op => Ex_Op,
|
||||
Out_C => Ex_C);
|
||||
|
||||
-- ALU
|
||||
Ual : ALU PORT MAP (
|
||||
A => Ex_B,
|
||||
B => Ex_C,
|
||||
Ctrl_Alu => Ex_Ctrl_ALu,
|
||||
S => Ex_Res_Alu,
|
||||
N => S_NFlag,
|
||||
O => S_OFlag,
|
||||
Z => S_ZFlag,
|
||||
C => S_CFlag);
|
||||
|
||||
-- Stage Ex/Mem
|
||||
Stage3 : Stage_Ex_Mem PORT MAP (
|
||||
In_A => Ex_A,
|
||||
In_B => Ex_FinalB,
|
||||
In_Op => Ex_Op,
|
||||
Clk => Clk,
|
||||
Out_A => Mem_A,
|
||||
Out_B => Mem_B,
|
||||
Out_Op => Mem_Op);
|
||||
|
||||
-- DataMemory
|
||||
DataMem : DataMemory PORT MAP (
|
||||
Addr => Mem_Addr,
|
||||
Data_in => Mem_B,
|
||||
Rw => Mem_RW,
|
||||
Rst => Rst,
|
||||
Clk => Clk,
|
||||
Data_out => Mem_Data_Out);
|
||||
|
||||
-- Stage Mem/RE
|
||||
Stage4 : Stage_Mem_Re PORT MAP (
|
||||
In_A => Mem_A,
|
||||
In_B => Mem_FinalB,
|
||||
In_Op => Mem_Op,
|
||||
Clk => Clk,
|
||||
Out_A => Re_A,
|
||||
Out_B => Re_B,
|
||||
Out_Op => Re_Op);
|
||||
|
||||
-- Instruction code
|
||||
-- ADD 00000001
|
||||
-- MUL 00000010
|
||||
-- SUB 00000011
|
||||
-- DIV 00000100
|
||||
-- COP 00000101
|
||||
-- AFC 00000110
|
||||
-- LOAD 00000111
|
||||
-- STORE 00001000
|
||||
|
||||
|
||||
-- Mux post registers
|
||||
Di_FinalB <= Di_B when
|
||||
Di_OP = "00000110" -- AFC
|
||||
else Di_RegB;
|
||||
|
||||
-- Mux post ALU
|
||||
Ex_FinalB <= Ex_B when
|
||||
Ex_Op = "00000110" --AFC
|
||||
or Ex_Op = "00000101" --COP
|
||||
or Ex_Op = "00000111" --LOAD
|
||||
or Ex_Op = "00001000" --STORE
|
||||
else Ex_Res_Alu;
|
||||
|
||||
-- LC pre ALU
|
||||
Ex_Ctrl_ALu <= "000" when Ex_Op = "00000001" --ADD
|
||||
else "001" when Ex_Op = "00000011" -- SUB
|
||||
else "010" when Ex_Op = "00000010" -- MUL
|
||||
else "100" when Ex_Op = "00000100" -- DIV
|
||||
else "111"; --ERROR
|
||||
|
||||
-- Mux post data memory
|
||||
Mem_FinalB <= Mem_B when
|
||||
Mem_Op = "00000110" --AFC
|
||||
or Mem_Op = "00000101" --COP
|
||||
or Mem_Op = "00000001" --ADD
|
||||
or Mem_Op = "00000011" -- SUB
|
||||
or Mem_Op = "00000010" -- MUL
|
||||
or Mem_Op = "00000100" -- DIV
|
||||
else Mem_FinalB ; --LOAD & STORE
|
||||
|
||||
-- Mux pre data memory
|
||||
Mem_Addr <= Mem_B when Mem_Op = "00000111" --LOAD
|
||||
else Mem_A; --STORE
|
||||
|
||||
-- LC pre data memory
|
||||
Mem_RW <= '1' when Mem_Op = "00000111" --LOAD
|
||||
else '0'; --STORE
|
||||
|
||||
-- LC post Pip_Mem_Re
|
||||
Re_W <= '0' when Re_Op = "00001000" --STORE
|
||||
else '1';
|
||||
|
||||
|
||||
end Behavioral;
|
||||
71
VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd
Normal file
71
VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 12:56:05
|
||||
-- Design Name:
|
||||
-- Module Name: registers - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Registers is
|
||||
Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
Addr_B : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
Addr_W : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
W : in STD_LOGIC;
|
||||
Data : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Rst : in STD_LOGIC;
|
||||
Clk : in STD_LOGIC;
|
||||
QA : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
QB : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end Registers;
|
||||
|
||||
architecture Behavioral of Registers is
|
||||
type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
|
||||
signal Regs : Reg_array;
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
|
||||
if Rst = '0' then -- Reset
|
||||
Regs <= (others => x"00");
|
||||
elsif W = '1' then -- Writing
|
||||
Regs(to_integer(unsigned(Addr_W))) <= Data;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
QA <= Regs(to_integer(unsigned(Addr_A)))
|
||||
when W = '0' or Addr_W /= Addr_A
|
||||
else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q
|
||||
|
||||
QB <= Regs(to_integer(unsigned(Addr_B)))
|
||||
when W = '0' or Addr_W /= Addr_B
|
||||
else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q
|
||||
|
||||
end Behavioral;
|
||||
59
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd
Normal file
59
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 14:09:59
|
||||
-- Design Name:
|
||||
-- Module Name: Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Stage_Di_Ex is
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_C : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end Stage_Di_Ex;
|
||||
|
||||
architecture Behavioral of Stage_Di_Ex is
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
Out_A <= In_A;
|
||||
Out_B <= In_B;
|
||||
Out_C <= In_C;
|
||||
Out_Op <= In_Op;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
56
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd
Normal file
56
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 14:09:59
|
||||
-- Design Name:
|
||||
-- Module Name: Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Stage_Ex_Mem is
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end Stage_Ex_Mem;
|
||||
|
||||
architecture Behavioral of Stage_Ex_Mem is
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
Out_A <= In_A;
|
||||
Out_B <= In_B;
|
||||
Out_Op <= In_Op;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
59
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd
Normal file
59
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 14:09:59
|
||||
-- Design Name:
|
||||
-- Module Name: Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Stage_Li_Di is
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_C : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end Stage_Li_Di;
|
||||
|
||||
architecture Behavioral of Stage_Li_Di is
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
Out_A <= In_A;
|
||||
Out_B <= In_B;
|
||||
Out_C <= In_C;
|
||||
Out_Op <= In_Op;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
56
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd
Normal file
56
VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15.05.2023 14:09:59
|
||||
-- Design Name:
|
||||
-- Module Name: Pipeline - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Stage_Mem_Re is
|
||||
Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_B : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
In_Op : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Clk : in STD_LOGIC;
|
||||
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end Stage_Mem_Re;
|
||||
|
||||
architecture Behavioral of Stage_Mem_Re is
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until clk'event and clk = '1';
|
||||
Out_A <= In_A;
|
||||
Out_B <= In_B;
|
||||
Out_Op <= In_Op;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
0
VHDL/ALU/ALU.srcs/sources_1/new/register.vhd
Normal file
0
VHDL/ALU/ALU.srcs/sources_1/new/register.vhd
Normal file
209
VHDL/ALU/ALU.xpr
Normal file
209
VHDL/ALU/ALU.xpr
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="38" Path="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="aef36ef3a0d94dac9e6058b656907afd"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="32"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/InstructionMemory.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Memory.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Registers.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Di_Ex.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Ex_Mem.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Li_Di.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Mem_Re.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Pipeline"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sim_1/new/VHDL.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/Test_Alu_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Test_Alu"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/Test_Alu_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
</Project>
|
||||
63
VHDL/ALU/Test_Alu_behav.wcfg
Normal file
63
VHDL/ALU/Test_Alu_behav.wcfg
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="Test_Alu_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="Test_Alu" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="5763000fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="93063001fs"></ZoomEndTime>
|
||||
<Cursor1Time time="35663000fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="142"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="132"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="8" />
|
||||
<wave_markers>
|
||||
<marker label="" time="1000000000" />
|
||||
<marker label="" time="994959000" />
|
||||
</wave_markers>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_A">
|
||||
<obj_property name="ElementShortName">local_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_A[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_B">
|
||||
<obj_property name="ElementShortName">local_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_B[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_Ctrl_Alu">
|
||||
<obj_property name="ElementShortName">local_Ctrl_Alu[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_Ctrl_Alu[2:0]</obj_property>
|
||||
<obj_property name="Radix">BINARYRADIX</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_S">
|
||||
<obj_property name="ElementShortName">local_S[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_S[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_N">
|
||||
<obj_property name="ElementShortName">local_N</obj_property>
|
||||
<obj_property name="ObjectShortName">local_N</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_O">
|
||||
<obj_property name="ElementShortName">local_O</obj_property>
|
||||
<obj_property name="ObjectShortName">local_O</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_Z">
|
||||
<obj_property name="ElementShortName">local_Z</obj_property>
|
||||
<obj_property name="ObjectShortName">local_Z</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_C">
|
||||
<obj_property name="ElementShortName">local_C</obj_property>
|
||||
<obj_property name="ObjectShortName">local_C</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Loading…
Reference in a new issue