33 lines
1.2 KiB
XML
33 lines
1.2 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
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<File Type="PA-TCL" Name="ALU.tcl"/>
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<File Type="RDS-DCP" Name="ALU.dcp"/>
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<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
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<File Type="RDS-RDS" Name="ALU.vds"/>
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<File Type="RDS-UTIL-PB" Name="ALU_utilization_synth.pb"/>
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<File Type="RDS-UTIL" Name="ALU_utilization_synth.rpt"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/new/ALU.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="ALU"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
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<Step Id="synth_design"/>
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</Strategy>
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</GenRun>
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