52 lines
1.3 KiB
VHDL
52 lines
1.3 KiB
VHDL
----------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 15.05.2023 13:55:29
|
|
-- Design Name:
|
|
-- Module Name: InstructionMemory - Behavioral
|
|
-- Project Name:
|
|
-- Target Devices:
|
|
-- Tool Versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
----------------------------------------------------------------------------------
|
|
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.NUMERIC_STD.ALL;
|
|
|
|
-- Uncomment the following library declaration if using
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
-- any Xilinx leaf cells in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity InstructionMemory is
|
|
Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0);
|
|
Clk : in STD_LOGIC;
|
|
Inst_out : out STD_LOGIC_VECTOR (31 downto 0));
|
|
end InstructionMemory;
|
|
|
|
architecture Behavioral of InstructionMemory is
|
|
type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0);
|
|
signal Mem : Mem_array;
|
|
begin
|
|
|
|
process
|
|
begin
|
|
wait until clk'event and clk = '1';
|
|
Inst_out <= Mem(to_integer(unsigned(Addr)));
|
|
end process;
|
|
|
|
end Behavioral;
|