From 22c945e716feca8c4edecdc5fa18442cfe106372 Mon Sep 17 00:00:00 2001 From: alejeune Date: Mon, 29 May 2023 13:58:26 +0200 Subject: [PATCH] Added VHDL part of the project --- VHDL/ALU/ALU.cache/wt/gui_handlers.wdf | 55 ++++ .../ALU.cache/wt/java_command_handlers.wdf | 12 + VHDL/ALU/ALU.cache/wt/project.wpc | 3 + VHDL/ALU/ALU.cache/wt/synthesis.wdf | 39 +++ VHDL/ALU/ALU.cache/wt/synthesis_details.wdf | 3 + VHDL/ALU/ALU.cache/wt/webtalk_pa.xml | 93 ++++++ VHDL/ALU/ALU.cache/wt/xsim.wdf | 4 + VHDL/ALU/ALU.hw/ALU.lpr | 6 + VHDL/ALU/ALU.ip_user_files/README.txt | 1 + VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml | 5 + VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml | 5 + .../synth_1/.Vivado_Synthesis.queue.rst | 0 VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst | 5 + VHDL/ALU/ALU.runs/synth_1/.vivado.end.rst | 0 VHDL/ALU/ALU.runs/synth_1/ALU.dcp | Bin 0 -> 36220 bytes VHDL/ALU/ALU.runs/synth_1/ALU.tcl | 52 ++++ VHDL/ALU/ALU.runs/synth_1/ALU.vds | 238 +++++++++++++++ .../ALU.runs/synth_1/ALU_utilization_synth.pb | Bin 0 -> 276 bytes .../synth_1/ALU_utilization_synth.rpt | 179 +++++++++++ VHDL/ALU/ALU.runs/synth_1/ISEWrap.js | 244 +++++++++++++++ VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh | 63 ++++ .../synth_1/__synthesis_is_complete__ | 0 VHDL/ALU/ALU.runs/synth_1/gen_run.xml | 33 ++ VHDL/ALU/ALU.runs/synth_1/htr.txt | 9 + VHDL/ALU/ALU.runs/synth_1/project.wdf | 31 ++ VHDL/ALU/ALU.runs/synth_1/rundef.js | 40 +++ VHDL/ALU/ALU.runs/synth_1/runme.bat | 11 + VHDL/ALU/ALU.runs/synth_1/runme.log | 237 +++++++++++++++ VHDL/ALU/ALU.runs/synth_1/runme.sh | 39 +++ VHDL/ALU/ALU.runs/synth_1/vivado.jou | 12 + VHDL/ALU/ALU.runs/synth_1/vivado.pb | Bin 0 -> 24295 bytes .../ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl | 11 + .../sim_1/behav/xsim/Test_Alu_behav.wdb | Bin 0 -> 7475 bytes .../sim_1/behav/xsim/Test_Alu_vhdl.prj | 7 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log | 55 ++++ VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh | 27 ++ .../ALU.sim/sim_1/behav/xsim/elaborate.log | 17 ++ .../ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh | 26 ++ .../ALU/ALU.sim/sim_1/behav/xsim/simulate.log | 2 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh | 26 ++ VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou | 12 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log | 13 + .../sim_1/behav/xsim/webtalk_31637.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_31637.backup.log | 13 + .../sim_1/behav/xsim/webtalk_32017.backup.jou | 12 + .../sim_1/behav/xsim/webtalk_32017.backup.log | 13 + .../behav/xsim/webtalk_831173.backup.jou | 12 + .../behav/xsim/webtalk_831173.backup.log | 13 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 1964 bytes .../Test_Alu_behav/Compile_Options.txt | 1 + .../Test_Alu_behav/TempBreakPointFile.txt | 1 + .../Test_Alu_behav/obj/xsim_0.lnx64.o | Bin 0 -> 16416 bytes .../xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c | 106 +++++++ .../Test_Alu_behav/obj/xsim_1.lnx64.o | Bin 0 -> 4560 bytes .../webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 53 ++++ .../webtalk/usage_statistics_ext_xsim.wdm | 38 +++ .../webtalk/usage_statistics_ext_xsim.xml | 44 +++ .../Test_Alu_behav/webtalk/xsim_webtalk.tcl | 32 ++ .../xsim/xsim.dir/Test_Alu_behav/xsim.dbg | Bin 0 -> 3796 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.mem | Bin 0 -> 2805 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.reloc | Bin 0 -> 478 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.rlx | 12 + .../xsim/xsim.dir/Test_Alu_behav/xsim.rtti | Bin 0 -> 318 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.svtype | Bin 0 -> 16 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.type | Bin 0 -> 6760 bytes .../xsim/xsim.dir/Test_Alu_behav/xsim.xdbg | Bin 0 -> 1776 bytes .../xsim.dir/Test_Alu_behav/xsimSettings.ini | 41 +++ .../xsim.dir/Test_Alu_behav/xsimcrash.log | 0 .../behav/xsim/xsim.dir/Test_Alu_behav/xsimk | Bin 0 -> 31496 bytes .../xsim.dir/Test_Alu_behav/xsimkernel.log | 7 + .../xsim/xsim.dir/xil_defaultlib/alu.vdb | Bin 0 -> 5551 bytes .../xsim/xsim.dir/xil_defaultlib/test_alu.vdb | Bin 0 -> 7062 bytes .../xil_defaultlib/xil_defaultlib.rlx | 6 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini | 1 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log | 2 + VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb | Bin 0 -> 355 bytes VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd | 107 +++++++ VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd | 58 ++++ .../sources_1/new/InstructionMemory.vhd | 52 ++++ VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd | 63 ++++ VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd | 287 ++++++++++++++++++ VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd | 71 +++++ .../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd | 59 ++++ .../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd | 56 ++++ .../ALU.srcs/sources_1/new/Stage_Li_Di.vhd | 59 ++++ .../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd | 56 ++++ VHDL/ALU/ALU.srcs/sources_1/new/register.vhd | 0 VHDL/ALU/ALU.xpr | 209 +++++++++++++ VHDL/ALU/Test_Alu_behav.wcfg | 63 ++++ 96 files changed, 3209 insertions(+) create mode 100644 VHDL/ALU/ALU.cache/wt/gui_handlers.wdf create mode 100644 VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf create mode 100644 VHDL/ALU/ALU.cache/wt/project.wpc create mode 100644 VHDL/ALU/ALU.cache/wt/synthesis.wdf create mode 100644 VHDL/ALU/ALU.cache/wt/synthesis_details.wdf create mode 100644 VHDL/ALU/ALU.cache/wt/webtalk_pa.xml create mode 100644 VHDL/ALU/ALU.cache/wt/xsim.wdf create mode 100644 VHDL/ALU/ALU.hw/ALU.lpr create mode 100644 VHDL/ALU/ALU.ip_user_files/README.txt create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml create mode 100644 VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml create mode 100644 VHDL/ALU/ALU.runs/synth_1/.Vivado_Synthesis.queue.rst create mode 100644 VHDL/ALU/ALU.runs/synth_1/.vivado.begin.rst create mode 100644 VHDL/ALU/ALU.runs/synth_1/.vivado.end.rst create mode 100644 VHDL/ALU/ALU.runs/synth_1/ALU.dcp create mode 100644 VHDL/ALU/ALU.runs/synth_1/ALU.tcl create mode 100644 VHDL/ALU/ALU.runs/synth_1/ALU.vds create mode 100644 VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.pb create mode 100644 VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.rpt create mode 100755 VHDL/ALU/ALU.runs/synth_1/ISEWrap.js create mode 100755 VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh create mode 100644 VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__ create mode 100644 VHDL/ALU/ALU.runs/synth_1/gen_run.xml create mode 100644 VHDL/ALU/ALU.runs/synth_1/htr.txt create mode 100644 VHDL/ALU/ALU.runs/synth_1/project.wdf create mode 100644 VHDL/ALU/ALU.runs/synth_1/rundef.js create mode 100644 VHDL/ALU/ALU.runs/synth_1/runme.bat create mode 100644 VHDL/ALU/ALU.runs/synth_1/runme.log create mode 100755 VHDL/ALU/ALU.runs/synth_1/runme.sh create mode 100644 VHDL/ALU/ALU.runs/synth_1/vivado.jou create mode 100644 VHDL/ALU/ALU.runs/synth_1/vivado.pb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu.tcl create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log create mode 100755 VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log create mode 100755 VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log create mode 100755 VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/Compile_Options.txt create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/TempBreakPointFile.txt create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.svtype create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimSettings.ini create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimcrash.log create mode 100755 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log create mode 100644 VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb create mode 100644 VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd create mode 100644 VHDL/ALU/ALU.srcs/sources_1/new/register.vhd create mode 100644 VHDL/ALU/ALU.xpr create mode 100644 VHDL/ALU/Test_Alu_behav.wcfg diff --git a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..a4efb65 --- /dev/null +++ b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf @@ -0,0 +1,55 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f6164645f656c656d656e74:3336:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3430:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:32:00:00 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Editing these files is not recommended. diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..7f1dfcd --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..b9bdcb4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..7f1dfcd --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..7f1dfcd --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..b9bdcb4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..7f1dfcd --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..7f1dfcd --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml b/VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..b9bdcb4 --- /dev/null +++ b/VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/VHDL/ALU/ALU.runs/synth_1/.Vivado_Synthesis.queue.rst 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zKsf=R90Fb>9PfE~hAPDb1yVzcp;eKw=K+8?D*%A`_`09li-blBdptlb!q+|2n;N5@ zw02CLXxWOKV3fIQ)DU(5`KeX}&1?Ws^(%72-kg_oM6E;^^&O6os3N(rJy zsgvy#ReX37=5gv#Q`DJqN|pVjD0xE-QNOyUkOd{xkKL!d$S^SdakoC@@h}6HC?> LDCE: 16 instances + +INFO: [Common 17-83] Releasing license: Synthesis +11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594 +INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.pb b/VHDL/ALU/ALU.runs/synth_1/ALU_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..66dd86c596412c4f471fcd2b1915afd1e365691b GIT binary patch literal 276 zcmd;LGcqu=&@-CEtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh b/VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__ b/VHDL/ALU/ALU.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..89ae79e --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/VHDL/ALU/ALU.runs/synth_1/htr.txt b/VHDL/ALU/ALU.runs/synth_1/htr.txt new file mode 100644 index 0000000..6768be2 --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl diff --git a/VHDL/ALU/ALU.runs/synth_1/project.wdf b/VHDL/ALU/ALU.runs/synth_1/project.wdf new file mode 100644 index 0000000..25be11b --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00 +eof:2773257219 diff --git a/VHDL/ALU/ALU.runs/synth_1/rundef.js b/VHDL/ALU/ALU.runs/synth_1/rundef.js new file mode 100644 index 0000000..4826119 --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;"; +} else { + PathVal = "/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64;/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.bat b/VHDL/ALU/ALU.runs/synth_1/runme.bat new file mode 100644 index 0000000..8eb74b1 --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.log b/VHDL/ALU/ALU.runs/synth_1/runme.log new file mode 100644 index 0000000..0ed1116 --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/runme.log @@ -0,0 +1,237 @@ + +*** Running vivado + with args -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source ALU.tcl -notrace +Command: synth_design -top ALU -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 846814 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46] +INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 3 Input 16 Bit Adders := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module ALU +Detailed RTL Component Info : ++---Adders : + 3 Input 16 Bit Adders := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |CARRY4 | 18| +|2 |LUT2 | 31| +|3 |LUT3 | 6| +|4 |LUT4 | 41| +|5 |LUT5 | 12| +|6 |LUT6 | 52| +|7 |LD | 16| +|8 |IBUF | 19| +|9 |OBUF | 12| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 207| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 16 instances were transformed. + LD => LDCE: 16 instances + +INFO: [Common 17-83] Releasing license: Synthesis +11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594 +INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023... diff --git a/VHDL/ALU/ALU.runs/synth_1/runme.sh b/VHDL/ALU/ALU.runs/synth_1/runme.sh new file mode 100755 index 0000000..461a56e --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin +else + PATH=/usr/local/insa/Xilinx.VIVADO/SDK/2018.2/bin:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/bin/lin64:/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.jou b/VHDL/ALU/ALU.runs/synth_1/vivado.jou new file mode 100644 index 0000000..367bb7b --- /dev/null +++ b/VHDL/ALU/ALU.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun May 14 22:48:29 2023 +# Process ID: 846737 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1 +# Command line: vivado -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.vds +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source ALU.tcl -notrace diff --git a/VHDL/ALU/ALU.runs/synth_1/vivado.pb b/VHDL/ALU/ALU.runs/synth_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..eb2a4512d8bbd7325e092888e668d02e72291905 GIT binary patch literal 24295 zcmeHP>2DlK72kGZhb_XcCD>&#%Tme8+QiuzcUR91d-%%1+8g7YBLcnK)_zMspKz!l`ArOZI;uN1aK7lxe_yXVf19(+^O!suR+cpkuuV$6?^!fU| zSMR-g^{VQJdg$ze+3hMuyM?E1G$ucYEC=tXbw#c^YHy3kwUR{6wCSee>P{;-*ch*rBuVZ((mTC#`m@3#lVhlb zp1k3}%bKx;qqN!APf3+#Xa;rN61nWSQ_6M_jLXn0gX-DlV@kfxyH$N1@r|WY=uDh z2NbvPO|47u1^Z$Pt34OLfJL#z{t^5EOm(Ga)Arz^jLUe1c1>#+Us#!kS9(-=6K+eS zS}l`$9p2eeGy|?Q~%)tN!w~^!UQG{p_@Tk!gWcYq?r@0tqSJOENB>44r}8QJwvE$OpbBpf3uSHAAyIVAK2Y z0XfYFDw#geY?hncZ+st+NTXblD}k*KIl;g?;!aR&8Srp=K$>> z&kg@Hq}iVe=xYPbE|`YxSP%vrd`r=_Hu#HaWCxmutK>$Y{UIgS(nSm-P4P-Do`YL) zLwga;@E!y&n@XDn-&K|oKzGZ!5OyAhN7G2xZfHQo%l4tTYy>?MNX7D;)^MVeBhM}L zc=UBhtymnEs`Z%(FApKlqQ~=drwJmJDk4js!j8OnP5o=g*&(d{aNz8L*n8N*QMtY> z)*-&K)FFtkat-2Z=;87BDmTNx8+ZL`UXoF~%0D@V&S}ObwJhdVy5guEp66~WmZsbd z@|_9DAW1#w=^<&gAoZ~5Rx+tLJ~>Zwubc;@0n?w@necj<;@jb`L#F==0ey2|`fE3r z@pTxLbhQUw7q{9`U_e5S%-*GHxhXL#4(z>BDOW1hphp|Fcb0wgYCC-N*eHdvHp7 zFf8?qp??jsAjN>;0PY`{^h4zO$VeCOp3Cvpt|08?C#+SV%F%=I66Bz8&CzT}Q|&zK zDPE#i;u6W|{fpF5G#$n(aiLhM1#u?Fuv&3)=h0)#;OE+HYT5a3Z^Yl8N99K`#xkUN zJ=cLFjA0xhu*<>TXA>5VR8jaXN_dBhJCX8WG$aMh&T{@ zK%MMI@ZzoPdR+B&^lUgPj$7GDa-HJU`dVDAbEq^3M^`m!DVEydMX-|@o03)&6Dn>w zme+mf#DGRzV;G%X@#=Z3;GFaBC{&I@WjwPx)LD*|y&kvF1vDEAl`#)UbL$-P#Rsk8 zIk*~Ev521b!X~dMtWmF~j&HayYh~>odwoKsoK3uh)!BRKR!k7Pg%)qD!bqkm;tQ&& zW1SjXPN!89FQWOixfQqrGbFKF7%tCC4O|oXkzB(vJe(Zm!`L|-2o>L~$@m<4PD~*u zre%v)X>xSydCG!i+BTjyU84;y!Yi_K7FA-!iDPdsZ^Zp(2}!pV%YgbBnT3O7Rs)AXm zvPjs>i(gtIHBzotGfGPYB2QXrsU|hkbv`OBm7-;*QE7>#W(TOX6(4FZ$D>ghO?jc# zpXrL0ebZgw81=-(Yx9pof$t{*`pO{irRa1N=MsaN95Wl0(4$%R!!7*3g-Ym2v+?5` zRXc{Mn_IhhMd|e*4a>2=;)6`_9Q7tEUyg*igi1$IZWQGVJenv>SiylW(X^+=%dkSlp=_*<=P9g^rFf*+xC!Uj z=gqicKZq`bwX%_J)r6ybKzKb?2{AM~B4$ctNL%;r4Q974L$@bFfEUccjv! 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Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..e0c1b363e9318448ec3a9f4456e362ada0b38285 GIT binary patch literal 7475 zcmeHLYitx%6u#vpRge~q0YzG|Wf5&>TUu-ZX?MFzDU?#_LLVaAZFh9H?C#W^-9Au5 ziNW-T@kNaUlr#a6po!=YF;R;_O^r=SRTQKoG%e{NReYlB>DU|?W9;ub;z?@H^*xyoMPSiV9d#<6w^Gp!+z0U>`-3$GHEkVB01 z?+ulbs)@?=Caw>1&9k?{;V9xBU5Qb7xUrDy$ZXrJg_P$khAjU=qkfNW^-w;4prJoM zj#e(^G~vc8(MrA_;lEi&1?hIeXB-o#9RLdtKxvH9NRAr9RMd_H906QoxN-Cohaa9} z8sflUj0|xNA4FTVy2-F=urwfOVFuSzxhBPEiW$iK)tY6XZm#)UkjbA2~y(f&lTA)+?$ z<9fI_>Jlqn9V0I45$%4&QHxk{)FDMIteCE&QTAu|AVgERtDV8+m-Yv-3QzEhyp}dDuUY9xOPL!(1DASVxdu zSac+NxHj^58dwVsCX!aJjXa(PX3U?MU$u7k;KPv_^JnCVX&UoqVkezW4`P( zzc|kX4_v_$?ZSusg!LwP(1MplHUzwRgvfqzkKmcehJZJpYq5s0*8~sG0| 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b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj new file mode 100644 index 0000000..566e460 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../ALU.srcs/sources_1/new/ALU.vhd" \ +"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \ + +# Do not sort compile order +nosort diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..dcdfb14 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,55 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity ALU +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:88] +ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38] +INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh new file mode 100755 index 0000000..a729c87 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh @@ -0,0 +1,27 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : compile.sh +# Simulator : Xilinx Vivado Simulator +# Description : Script for compiling the simulation design source files +# +# Generated by Vivado on Mon May 15 12:53:49 CEST 2023 +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: compile.sh +# +# **************************************************************************** +ExecStep() +{ +"$@" +RETVAL=$? +if [ $RETVAL -ne 0 ] +then +exit $RETVAL +fi +} +echo "xvhdl --incr --relax -prj Test_Alu_vhdl.prj" +ExecStep xvhdl --incr --relax -prj Test_Alu_vhdl.prj 2>&1 | tee -a compile.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..04a434c --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,17 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.std_logic_arith +Compiling package ieee.std_logic_unsigned +Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default] +Compiling architecture behavioral of entity xil_defaultlib.test_alu +Built simulation snapshot Test_Alu_behav diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh new file mode 100755 index 0000000..3f91c4e --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : Xilinx Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Mon May 15 12:53:50 CEST 2023 +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +ExecStep() +{ +"$@" +RETVAL=$? +if [ $RETVAL -ne 0 ] +then +exit $RETVAL +fi +} +ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh new file mode 100755 index 0000000..e0151ae --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : Xilinx Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Mon May 15 12:53:51 CEST 2023 +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +ExecStep() +{ +"$@" +RETVAL=$? +if [ $RETVAL -ne 0 ] +then +exit $RETVAL +fi +} +ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..05685f9 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun May 14 22:27:26 2023 +# Process ID: 831441 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log new file mode 100644 index 0000000..2518533 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun May 14 22:27:26 2023 +# Process ID: 831441 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:27 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou new file mode 100644 index 0000000..7eeb0ee --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri May 12 18:00:54 2023 +# Process ID: 31637 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log new file mode 100644 index 0000000..266b444 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_31637.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri May 12 18:00:54 2023 +# Process ID: 31637 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Fri May 12 18:00:55 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou new file mode 100644 index 0000000..680239c --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri May 12 18:03:10 2023 +# Process ID: 32017 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log new file mode 100644 index 0000000..ac35d6b --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_32017.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri May 12 18:03:10 2023 +# Process ID: 32017 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Fri May 12 18:03:11 2023... diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou new file mode 100644 index 0000000..ad264ba --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun May 14 22:27:00 2023 +# Process ID: 831173 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log new file mode 100644 index 0000000..5c88519 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831173.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun May 14 22:27:00 2023 +# Process ID: 831173 +# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source 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b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c @@ -0,0 +1,106 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[10] = {(funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 10; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 10); + iki_vhdl_file_variable_register(dp + 3576); + iki_vhdl_file_variable_register(dp + 3632); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/Test_Alu_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/Test_Alu_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + 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XSIM Usage Report


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software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedSun May 14 22:27:25 2023os_platformLIN64
product_versionXSIM v2018.2 (64-bit)project_idaef36ef3a0d94dac9e6058b656907afd
project_iteration12random_id48ade6b1-45bb-42c1-b620-33b3e004d501
registration_id48ade6b1-45bb-42c1-b620-33b3e004d501route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Xeon(R) Silver 4216 CPU @ 2.10GHzcpu_speed800.000 MHz
os_nameUbuntuos_releaseUbuntu 20.04.6 LTS
system_ram134.000 GBtotal_processors2

+ + +
vivado_usage

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xsim
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command_line_options
command=xsim
+
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usage
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trace_waveform=true
+

+ + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..c05367b --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
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+ +
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+ + + + + +
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+ diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..68a1eb5 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Mon May 15 14:24:45 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "50" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" +webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3200.000 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "122600_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2250690028 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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+1,6 @@ +0.6 +2018.2 +Jun 14 2018 +20:07:38 +/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1684148028,vhdl,,,,test_alu,,,,,,,, +/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1684096722,vhdl,,,,alu,,,,,,,, diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log new file mode 100644 index 0000000..afa41cd --- /dev/null +++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Test_Alu diff --git a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000000000000000000000000000000000000..57833cc129cdd43fa4a036315c4e2cbd3e772c37 GIT binary patch literal 355 zcmZ`!%}T>S5N?!cS)l~HiH9Xn5Fyp zR9aEQ!!W})Gv5#SaL7?CxoBQdKGNHZ@r>pufckyoQ(c z?Y=u5Z;RZKeg2)g^@?^Aa5Oyo9q^EJuff '0'); + signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal local_Ctrl_Alu : STD_LOGIC_VECTOR (2 downto 0) := (others => '0'); + + --outputs + signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal local_N : STD_LOGIC := '0'; + signal local_O : STD_LOGIC := '0'; + signal local_Z : STD_LOGIC := '0'; + signal local_C : STD_LOGIC := '0'; + + -- constant Clock_period : time := 10ns; + +begin + +-- instantiate +instance : ALU PORT MAP ( + A => local_A, + B => local_B, + Ctrl_Alu => local_Ctrl_Alu, + S => local_S, + N => local_N, + O => local_O, + Z => local_Z, + C => local_C +); + +local_Ctrl_Alu <= "000", + "001" after 20 ns, + "010" after 30 ns, + "100" after 40 ns, + "001" after 50 ns, -- test Z flag + "000" after 60 ns, -- test C flag + "010" after 70 ns; -- test O flag + +local_A <= x"00", + x"10" after 10 ns, + x"a2" after 20 ns, + x"12" after 30 ns, + x"18" after 40 ns, + x"19" after 50 ns, + "10000000" after 60 ns; + +local_B <= x"00", + x"78" after 10 ns, + x"b9" after 20 ns, + x"02" after 30 ns, + x"a2" after 40 ns, + x"19" after 50 ns, + "10000000" after 60 ns; + + + + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd new file mode 100644 index 0000000..555837d --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12.05.2023 16:14:24 +-- Design Name: +-- Module Name: ALU - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ALU is + Port ( A : in STD_LOGIC_VECTOR (7 downto 0); + B : in STD_LOGIC_VECTOR (7 downto 0); + Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div + S : out STD_LOGIC_VECTOR (7 downto 0); + N : out STD_LOGIC; + O : out STD_LOGIC; + Z : out STD_LOGIC; + C : out STD_LOGIC); +end ALU; + +architecture Behavioral of ALU is + signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000"; +begin + res <= (x"00" & A) + (x"00" & B) when (Ctrl_Alu = "000") else + (x"00" & A) - (x"00" & B) when (Ctrl_Alu = "001") else + A * B when (Ctrl_Alu = "010"); -- else + -- A mod B when (Ctrl_Alu = "100"); + S <= res(7 downto 0); + N <= '1' when B > A and Ctrl_Alu="001" else '0'; + O <= '1' when res(15 downto 8) > x"01" and Ctrl_Alu="010" else '0'; + Z <= '1' when res(15 downto 0) = x"0" else '0'; + C <= '1' when res(8)='1' and (Ctrl_Alu = "000") else '0'; +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd new file mode 100644 index 0000000..f067be7 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd @@ -0,0 +1,52 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 13:55:29 +-- Design Name: +-- Module Name: InstructionMemory - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity InstructionMemory is + Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Inst_out : out STD_LOGIC_VECTOR (31 downto 0)); +end InstructionMemory; + +architecture Behavioral of InstructionMemory is + type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0); + signal Mem : Mem_array; +begin + + process + begin + wait until clk'event and clk = '1'; + Inst_out <= Mem(to_integer(unsigned(Addr))); + end process; + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd new file mode 100644 index 0000000..5e0f95f --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd @@ -0,0 +1,63 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 13:37:41 +-- Design Name: +-- Module Name: DataMemory - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DataMemory is + Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); + Data_in : in STD_LOGIC_VECTOR (7 downto 0); + Rw : in STD_LOGIC; + Rst : in STD_LOGIC; + Clk : in STD_LOGIC; + Data_out : out STD_LOGIC_VECTOR (7 downto 0)); +end DataMemory; + +architecture Behavioral of DataMemory is + type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0); + signal Mem : Mem_array; +begin + + process + begin + wait until clk'event and clk = '1'; + if Rst = '0' then -- Reset + mem <= (others => x"00"); + else if Rw = '1' then --reading + Data_out <= Mem(to_integer(unsigned(Addr))); + else -- writting + Mem(to_integer(unsigned(Addr))) <= Data_in; + end if; + end if; + end process; + + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd new file mode 100644 index 0000000..3741490 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -0,0 +1,287 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 14:29:58 +-- Design Name: +-- Module Name: Pipeline - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Pipeline is + Port ( Clk : in STD_LOGIC); +end Pipeline; + +architecture Behavioral of Pipeline is + + signal IP : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Rst : STD_LOGIC; -- to modify + + component InstructionMemory + Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Inst_out : out STD_LOGIC_VECTOR (31 downto 0)); + end component; + + signal Li : STD_LOGIC_VECTOR (31 downto 0) := (others => '0'); + + component Stage_Li_Di + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_C : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0); + Out_C : out STD_LOGIC_VECTOR (7 downto 0) + ); + end component; + + signal Li_A, Li_Op, Li_B, Li_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + + component Registers + Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); + Addr_B : in STD_LOGIC_VECTOR (3 downto 0); + Addr_W : in STD_LOGIC_VECTOR (3 downto 0); + W : in STD_LOGIC; + Data : in STD_LOGIC_VECTOR (7 downto 0); + Rst : in STD_LOGIC; + Clk : in STD_LOGIC; + QA : out STD_LOGIC_VECTOR (7 downto 0); + QB : out STD_LOGIC_VECTOR (7 downto 0) + ); + end component; + + signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Di_RegB, Di_FinalB, Di_C2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + + component Stage_Di_Ex + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_C : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0); + Out_C : out STD_LOGIC_VECTOR (7 downto 0) + ); + end component; + + signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + + component ALU + Port ( A : in STD_LOGIC_VECTOR (7 downto 0); + B : in STD_LOGIC_VECTOR (7 downto 0); + Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div + S : out STD_LOGIC_VECTOR (7 downto 0); + N : out STD_LOGIC; + O : out STD_LOGIC; + Z : out STD_LOGIC; + C : out STD_LOGIC); + end component; + + signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal S_NFlag, S_Oflag, S_CFlag, S_ZFlag : STD_LOGIC; + + component Stage_Ex_Mem + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0) + ); + end component; + + signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Mem_RW : STD_LOGIC; + signal Mem_Addr, Mem_Data_Out, Mem_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + + component DataMemory + Port ( Addr : in STD_LOGIC_VECTOR (7 downto 0); + Data_in : in STD_LOGIC_VECTOR (7 downto 0); + Rw : in STD_LOGIC; + Rst : in STD_LOGIC; + Clk : in STD_LOGIC; + Data_out : out STD_LOGIC_VECTOR (7 downto 0)); + end component; + + component Stage_Mem_Re + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0) + ); + end component; + + signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); + signal Re_W : STD_LOGIC; + +begin + +-- instructionMemory +MemInst : InstructionMemory PORT MAP ( + Addr => IP, + Clk => Clk, + Inst_out => Li); + +-- Stage_Li_Di +Stage1 : Stage_Li_Di PORT MAP ( + In_A => Li(23 downto 16), + In_B => Li(15 downto 8), + In_C => Li(7 downto 0), + In_Op => Li(31 downto 24), + Clk => Clk, + Out_A => Di_A, + Out_B => Di_B, + Out_Op => Di_Op, + Out_C => Di_C); + +-- Registers +StageRegisters : Registers PORT MAP ( + Addr_A => Di_B, + Addr_B => Di_C, + Addr_W => Re_A, + W => Re_W, + Data => Re_B, + Rst => Rst, + Clk => Clk, + QA => Di_RegB, + QB => Di_C2); + +-- Stage DI/EX +Stage2 : Stage_Di_Ex PORT MAP ( + In_A => Di_A, + In_B => Di_FinalB, + In_C => Di_C2, + In_Op => Di_Op, + Clk => Clk, + Out_A => Ex_A, + Out_B => Ex_B, + Out_Op => Ex_Op, + Out_C => Ex_C); + +-- ALU +Ual : ALU PORT MAP ( + A => Ex_B, + B => Ex_C, + Ctrl_Alu => Ex_Ctrl_ALu, + S => Ex_Res_Alu, + N => S_NFlag, + O => S_OFlag, + Z => S_ZFlag, + C => S_CFlag); + +-- Stage Ex/Mem +Stage3 : Stage_Ex_Mem PORT MAP ( + In_A => Ex_A, + In_B => Ex_FinalB, + In_Op => Ex_Op, + Clk => Clk, + Out_A => Mem_A, + Out_B => Mem_B, + Out_Op => Mem_Op); + +-- DataMemory +DataMem : DataMemory PORT MAP ( + Addr => Mem_Addr, + Data_in => Mem_B, + Rw => Mem_RW, + Rst => Rst, + Clk => Clk, + Data_out => Mem_Data_Out); + +-- Stage Mem/RE +Stage4 : Stage_Mem_Re PORT MAP ( + In_A => Mem_A, + In_B => Mem_FinalB, + In_Op => Mem_Op, + Clk => Clk, + Out_A => Re_A, + Out_B => Re_B, + Out_Op => Re_Op); + +-- Instruction code + -- ADD 00000001 + -- MUL 00000010 + -- SUB 00000011 + -- DIV 00000100 + -- COP 00000101 + -- AFC 00000110 + -- LOAD 00000111 + -- STORE 00001000 + + +-- Mux post registers +Di_FinalB <= Di_B when + Di_OP = "00000110" -- AFC + else Di_RegB; + +-- Mux post ALU +Ex_FinalB <= Ex_B when + Ex_Op = "00000110" --AFC + or Ex_Op = "00000101" --COP + or Ex_Op = "00000111" --LOAD + or Ex_Op = "00001000" --STORE + else Ex_Res_Alu; + +-- LC pre ALU +Ex_Ctrl_ALu <= "000" when Ex_Op = "00000001" --ADD + else "001" when Ex_Op = "00000011" -- SUB + else "010" when Ex_Op = "00000010" -- MUL + else "100" when Ex_Op = "00000100" -- DIV + else "111"; --ERROR + +-- Mux post data memory +Mem_FinalB <= Mem_B when + Mem_Op = "00000110" --AFC + or Mem_Op = "00000101" --COP + or Mem_Op = "00000001" --ADD + or Mem_Op = "00000011" -- SUB + or Mem_Op = "00000010" -- MUL + or Mem_Op = "00000100" -- DIV + else Mem_FinalB ; --LOAD & STORE + +-- Mux pre data memory +Mem_Addr <= Mem_B when Mem_Op = "00000111" --LOAD + else Mem_A; --STORE + +-- LC pre data memory +Mem_RW <= '1' when Mem_Op = "00000111" --LOAD + else '0'; --STORE + +-- LC post Pip_Mem_Re +Re_W <= '0' when Re_Op = "00001000" --STORE + else '1'; + + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd new file mode 100644 index 0000000..f132e6e --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd @@ -0,0 +1,71 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 12:56:05 +-- Design Name: +-- Module Name: registers - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Registers is + Port ( Addr_A : in STD_LOGIC_VECTOR (3 downto 0); + Addr_B : in STD_LOGIC_VECTOR (3 downto 0); + Addr_W : in STD_LOGIC_VECTOR (3 downto 0); + W : in STD_LOGIC; + Data : in STD_LOGIC_VECTOR (7 downto 0); + Rst : in STD_LOGIC; + Clk : in STD_LOGIC; + QA : out STD_LOGIC_VECTOR (7 downto 0); + QB : out STD_LOGIC_VECTOR (7 downto 0)); +end Registers; + +architecture Behavioral of Registers is + type Reg_array is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0); + signal Regs : Reg_array; +begin + process + begin + wait until clk'event and clk = '1'; + + if Rst = '0' then -- Reset + Regs <= (others => x"00"); + elsif W = '1' then -- Writing + Regs(to_integer(unsigned(Addr_W))) <= Data; + end if; + + end process; + + QA <= Regs(to_integer(unsigned(Addr_A))) + when W = '0' or Addr_W /= Addr_A + else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q + + QB <= Regs(to_integer(unsigned(Addr_B))) + when W = '0' or Addr_W /= Addr_B + else Regs(to_integer(unsigned(Addr_W))) ; -- to bypass D --> Q + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd new file mode 100644 index 0000000..38fe1e4 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 14:09:59 +-- Design Name: +-- Module Name: Pipeline - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Stage_Di_Ex is + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_C : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0); + Out_C : out STD_LOGIC_VECTOR (7 downto 0) + ); +end Stage_Di_Ex; + +architecture Behavioral of Stage_Di_Ex is + +begin + process + begin + wait until clk'event and clk = '1'; + Out_A <= In_A; + Out_B <= In_B; + Out_C <= In_C; + Out_Op <= In_Op; + end process; + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd new file mode 100644 index 0000000..082b4e3 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 14:09:59 +-- Design Name: +-- Module Name: Pipeline - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Stage_Ex_Mem is + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0) + ); +end Stage_Ex_Mem; + +architecture Behavioral of Stage_Ex_Mem is + +begin + process + begin + wait until clk'event and clk = '1'; + Out_A <= In_A; + Out_B <= In_B; + Out_Op <= In_Op; + end process; + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd new file mode 100644 index 0000000..88424f3 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 14:09:59 +-- Design Name: +-- Module Name: Pipeline - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Stage_Li_Di is + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_C : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0); + Out_C : out STD_LOGIC_VECTOR (7 downto 0) + ); +end Stage_Li_Di; + +architecture Behavioral of Stage_Li_Di is + +begin + process + begin + wait until clk'event and clk = '1'; + Out_A <= In_A; + Out_B <= In_B; + Out_C <= In_C; + Out_Op <= In_Op; + end process; + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd new file mode 100644 index 0000000..4528761 --- /dev/null +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15.05.2023 14:09:59 +-- Design Name: +-- Module Name: Pipeline - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Stage_Mem_Re is + Port ( In_A : in STD_LOGIC_VECTOR (7 downto 0); + In_B : in STD_LOGIC_VECTOR (7 downto 0); + In_Op : in STD_LOGIC_VECTOR (7 downto 0); + Clk : in STD_LOGIC; + Out_A : out STD_LOGIC_VECTOR (7 downto 0); + Out_B : out STD_LOGIC_VECTOR (7 downto 0); + Out_Op : out STD_LOGIC_VECTOR (7 downto 0) + ); +end Stage_Mem_Re; + +architecture Behavioral of Stage_Mem_Re is + +begin + process + begin + wait until clk'event and clk = '1'; + Out_A <= In_A; + Out_B <= In_B; + Out_Op <= In_Op; + end process; + +end Behavioral; diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/register.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/register.vhd new file mode 100644 index 0000000..e69de29 diff --git a/VHDL/ALU/ALU.xpr b/VHDL/ALU/ALU.xpr new file mode 100644 index 0000000..5f3e901 --- /dev/null +++ b/VHDL/ALU/ALU.xpr @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/VHDL/ALU/Test_Alu_behav.wcfg b/VHDL/ALU/Test_Alu_behav.wcfg new file mode 100644 index 0000000..8bcb065 --- /dev/null +++ b/VHDL/ALU/Test_Alu_behav.wcfg @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + local_A[7:0] + local_A[7:0] + UNSIGNEDDECRADIX + + + local_B[7:0] + local_B[7:0] + UNSIGNEDDECRADIX + + + local_Ctrl_Alu[2:0] + local_Ctrl_Alu[2:0] + BINARYRADIX + + + + local_S[7:0] + local_S[7:0] + UNSIGNEDDECRADIX + + + local_N + local_N + + + local_O + local_O + + + local_Z + local_Z + + + local_C + local_C + +