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Raphaël LACROIX 2023-05-29 20:33:37 +02:00
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55
VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
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@ -1,62 +1,77 @@
version:1
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eof:1674420043
eof:1336689854

7
VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
View file

@ -6,9 +6,10 @@ version:1
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eof:710514237
eof:2907318966

2
VHDL/ALU/ALU.cache/wt/project.wpc
View file

@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:13
6d6f64655f636f756e7465727c4755494d6f6465:16
eof:

64
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
View file

@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon May 29 14:19:07 2023">
<application name="pa" timeStamp="Mon May 29 20:28:54 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
<property name="ProjectIteration" value="4" type="ProjectIteration"/>
@ -24,78 +24,94 @@ This means code written to parse this file will need to be revisited each subseq
<property name="OpenProject" value="2" type="JavaHandler"/>
<property name="RunImplementation" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="6" type="JavaHandler"/>
<property name="ShowView" value="4" type="JavaHandler"/>
<property name="SimulationRelaunch" value="3" type="JavaHandler"/>
<property name="SimulationRun" value="27" type="JavaHandler"/>
<property name="ToolsSettings" value="3" type="JavaHandler"/>
<property name="SimulationRun" value="58" type="JavaHandler"/>
<property name="ToolsSettings" value="5" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="9" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="45" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="47" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="19" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="13" type="GuiHandlerData"/>
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="173" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="213" type="GuiHandlerData"/>
<property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="36" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="72" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="13" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="21" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="33" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="25" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="1" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="1" type="GuiHandlerData"/>
<property name="LogPanel_COPY" value="1" type="GuiHandlerData"/>
<property name="LogPanel_FIND" value="1" type="GuiHandlerData"/>
<property name="LogPanel_PAUSE_OUTPUT" value="2" type="GuiHandlerData"/>
<property name="LogPanel_TOGGLE_COLUMN_SELECTION_MODE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="14" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="60" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="9" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="20" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="40" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="6" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="6" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="21" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="1" type="GuiHandlerData"/>
<property name="OpenFileAction_OPEN_DIRECTORY" value="1" type="GuiHandlerData"/>
<property name="OpenFileAction_OPEN_DIRECTORY" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="14" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="26" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="59" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="13" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="19" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
<property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="79" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="100" type="GuiHandlerData"/>
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="4" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="8" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="16" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="13" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="36" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="42" type="GuiHandlerData"/>
<property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/>
<property name="WaveformView_NEXT_MARKER" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="17" type="GuiMode"/>
<property name="GuiMode" value="21" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="11" type="TclMode"/>
<property name="TclMode" value="15" type="TclMode"/>
</item>
</section>
</application>

4
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
View file

@ -1,11 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
<File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
<File Type="RDS-RDS" Name="ALU.vds"/>
<File Type="RDS-UTIL-PB" Name="ALU_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ALU_utilization_synth.rpt"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.vhd">

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
View file

Binary file not shown.

116
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
View file

@ -53,3 +53,119 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
ERROR: [VRFC 10-724] found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<=" [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:85]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd:38]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
ERROR: [VRFC 10-1412] syntax error near B [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:74]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
INFO: [VRFC 10-240] VHDL file /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Mon May 15 12:53:49 CEST 2023
# Generated by Vivado on Mon May 29 20:22:53 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

1
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
View file

@ -12,6 +12,7 @@ Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default]
Compiling architecture behavioral of entity xil_defaultlib.test_alu
Built simulation snapshot Test_Alu_behav

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Mon May 15 12:53:50 CEST 2023
# Generated by Vivado on Mon May 29 20:22:55 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
# Generated by Vivado on Mon May 15 12:53:51 CEST 2023
# Generated by Vivado on Mon May 29 20:22:56 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
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@ -2,8 +2,8 @@
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:26 2023
# Process ID: 831441
# Start of session at: Mon May 29 19:45:48 2023
# Process ID: 341146
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log

6
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
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@ -2,12 +2,12 @@
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:26 2023
# Process ID: 831441
# Start of session at: Mon May 29 19:45:48 2023
# Process ID: 341146
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:27 2023...
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 19:45:49 2023...

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.jou Normal file
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@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 19:26:30 2023
# Process ID: 334386
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace

13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_334386.backup.log Normal file
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@ -0,0 +1,13 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 19:26:30 2023
# Process ID: 334386
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 19:26:31 2023...

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831441.backup.jou Normal file
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@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:26 2023
# Process ID: 831441
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace

13
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831441.backup.log Normal file
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@ -0,0 +1,13 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:26 2023
# Process ID: 831441
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:27 2023...

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
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Binary file not shown.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
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Binary file not shown.

24
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
View file

@ -43,24 +43,20 @@
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern void execute_38(char*, char *);
extern void execute_39(char*, char *);
extern void execute_40(char*, char *);
extern void execute_32(char*, char *);
extern void execute_33(char*, char *);
extern void execute_34(char*, char *);
extern void execute_35(char*, char *);
extern void execute_36(char*, char *);
extern void execute_37(char*, char *);
extern void execute_53(char*, char *);
extern void execute_54(char*, char *);
extern void execute_55(char*, char *);
extern void execute_51(char*, char *);
extern void execute_52(char*, char *);
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[10] = {(funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 10;
funcp funcTab[6] = {(funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_51, (funcp)execute_52, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 6;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 10);
iki_vhdl_file_variable_register(dp + 3576);
iki_vhdl_file_variable_register(dp + 3632);
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 6);
iki_vhdl_file_variable_register(dp + 3800);
iki_vhdl_file_variable_register(dp + 3856);
/*Populate the transaction function pointer field in the whole net structure */

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o
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Binary file not shown.

6
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
View file

@ -1,5 +1,5 @@
1684096019
1684096045
51
1685381189
1685382347
69
1
aef36ef3a0d94dac9e6058b656907afd

6
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html
View file

@ -4,11 +4,11 @@
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2258646</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Sun May 14 22:27:25 2023</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon May 29 19:45:47 2023</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>LIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2018.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>aef36ef3a0d94dac9e6058b656907afd</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>12</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>52</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>48ade6b1-45bb-42c1-b620-33b3e004d501</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>48ade6b1-45bb-42c1-b620-33b3e004d501</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
@ -43,7 +43,7 @@
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>iteration=0</TD>
<TD>runtime=1 us</TD>
<TD>simulation_memory=122600_KB</TD>
<TD>simulation_memory=122616_KB</TD>
<TD>simulation_time=0.03_sec</TD>
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
</TR> </TABLE>

8
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml
View file

@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sun May 14 22:27:26 2023'>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Mon May 29 19:45:48 2023'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2258646" description="" />
<keyValuePair key="date_generated" value="Sun May 14 22:27:25 2023" description="" />
<keyValuePair key="date_generated" value="Mon May 29 19:45:47 2023" description="" />
<keyValuePair key="os_platform" value="LIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.2 (64-bit)" description="" />
<keyValuePair key="project_id" value="aef36ef3a0d94dac9e6058b656907afd" description="" />
<keyValuePair key="project_iteration" value="12" description="" />
<keyValuePair key="project_iteration" value="52" description="" />
<keyValuePair key="random_id" value="48ade6b1-45bb-42c1-b620-33b3e004d501" description="" />
<keyValuePair key="registration_id" value="48ade6b1-45bb-42c1-b620-33b3e004d501" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
@ -35,7 +35,7 @@
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="1 us" description="" />
<keyValuePair key="simulation_memory" value="122600_KB" description="" />
<keyValuePair key="simulation_memory" value="122616_KB" description="" />
<keyValuePair key="simulation_time" value="0.03_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>

18
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
View file

@ -1,6 +1,6 @@
webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Mon May 15 14:24:45 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Mon May 29 20:28:58 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -14,19 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "50" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "68" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3200.000 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "67.000 GB" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "122600_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2250690028 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "122620_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1496851547 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
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@ -1,6 +1,6 @@
{
crc : 117194062558042768 ,
crc : 5165304247125619484 ,
ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" ,
buildDate : "Jun 14 2018" ,

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
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@ -1,7 +1,7 @@
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 45953
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 59047
Design successfully loaded
Design Loading Memory Usage: 32664 KB (Peak: 32724 KB)
Design Loading CPU Usage: 10 ms
Design Loading Memory Usage: 32684 KB (Peak: 32736 KB)
Design Loading CPU Usage: 20 ms
Simulation completed
Simulation Memory Usage: 122600 KB (Peak: 179936 KB)
Simulation CPU Usage: 10 ms
Simulation Memory Usage: 122620 KB (Peak: 179956 KB)
Simulation CPU Usage: 30 ms

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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@ -2,5 +2,5 @@
2018.2
Jun 14 2018
20:07:38
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1684148028,vhdl,,,,test_alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1684096722,vhdl,,,,alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685384562,vhdl,,,,test_alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685384160,vhdl,,,,alu,,,,,,,,

47
VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd
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@ -41,7 +41,7 @@ architecture Behavioral of Test_Alu is
component ALU
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0); -- 000 + / 001 - / 010 * / 100 Div
S : out STD_LOGIC_VECTOR (7 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
@ -52,7 +52,7 @@ architecture Behavioral of Test_Alu is
-- inputs
signal local_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal local_Ctrl_Alu : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal local_Ctrl_Alu : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
--outputs
signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
@ -77,29 +77,34 @@ instance : ALU PORT MAP (
C => local_C
);
local_Ctrl_Alu <= "000",
"001" after 20 ns,
"010" after 30 ns,
"100" after 40 ns,
"001" after 50 ns, -- test Z flag
"000" after 60 ns, -- test C flag
"010" after 70 ns; -- test O flag
local_Ctrl_Alu <= x"01", -- ADD
x"02" after 40 ns, -- MUL
x"03" after 60 ns, -- SUB
x"04" after 90 ns; -- DIV
local_A <= x"00",
x"10" after 10 ns,
x"a2" after 20 ns,
x"12" after 30 ns,
x"18" after 40 ns,
x"19" after 50 ns,
"10000000" after 60 ns;
x"00" after 10 ns,
x"0A" after 20 ns,
x"96" after 30 ns,
x"1D" after 40 ns,
x"0A" after 50 ns,
x"0B" after 60 ns,
x"0F" after 70 ns,
x"19" after 80 ns,
x"18" after 90 ns,
x"19" after 100 ns;
local_B <= x"00",
x"78" after 10 ns,
x"b9" after 20 ns,
x"02" after 30 ns,
x"a2" after 40 ns,
x"19" after 50 ns,
"10000000" after 60 ns;
x"00" after 10 ns,
x"82" after 20 ns,
x"A0" after 30 ns,
x"09" after 40 ns,
x"04" after 50 ns,
x"0B" after 60 ns,
x"12" after 70 ns,
x"0B" after 80 ns,
x"06" after 90 ns,
x"07" after 100 ns;

51
VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
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@ -20,8 +20,9 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
@ -35,7 +36,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0);
S : out STD_LOGIC_VECTOR (7 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
@ -43,16 +44,44 @@ entity ALU is
C : out STD_LOGIC);
end ALU;
-- Instruction code
-- ADD x"01"
-- MUL x"02"
-- SUB x"03"
-- DIV x"04"
-- INF x"09"
-- SUP x"0A"
-- EQ x"0B"
-- NOT x"0C"
-- AND x"0D"
-- OR x"0E"
-- XOR x"0F"
architecture Behavioral of ALU is
signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";
signal res : STD_LOGIC_VECTOR(15 downto 0):= x"0000";
begin
res <= (x"00" & A) + (x"00" & B) when (Ctrl_Alu = "000") else
(x"00" & A) - (x"00" & B) when (Ctrl_Alu = "001") else
A * B when (Ctrl_Alu = "010"); -- else
-- A mod B when (Ctrl_Alu = "100");
process(A, B, Ctrl_Alu)
begin
N <= '0';
O <= '0';
Z <= '0';
C <= '0';
case Ctrl_Alu is
when x"01" => res <= (x"00" & A) + (x"00" & B) ; if (((x"00" & A) + (x"00" & B)) > 255) then C <= '1'; elsif (A+B = 0) then Z <= '1'; end if; -- ADD
when x"02" => res <= A * B; if (A * B > 255) then O <= '1'; elsif A * B = 0 then Z <= '1'; end if; -- MUL
when x"03" => res <= (x"00" & A) - (x"00" & B) ; if (B > A) then N <= '1'; elsif (B = A) then Z <= '1'; end if; -- SUB
when x"04" => if (B /= 0) then res <= (x"00" & std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8))); else res <= x"0000"; end if; -- DIV
when x"09" => if A < B then res <= x"0001"; else res <= x"0000"; end if;
when x"0A" => if A > B then res <= x"0001"; else res <= x"0000"; end if;
when x"0B" => if A = B then res <= x"0001"; else res <= x"0000"; end if;
when x"0C" => if A > 0 then res <= x"0000"; else res <= x"0001"; end if;
when x"0D" => res <= A or B;
when x"0E" => res <= A and B;
when x"0F" => res <= A xor B;
when others => res <= x"0000";
end case;
end process;
S <= res(7 downto 0);
N <= '1' when B > A and Ctrl_Alu="001" else '0';
O <= '1' when res(15 downto 8) > x"01" and Ctrl_Alu="010" else '0';
Z <= '1' when res(15 downto 0) = x"0" else '0';
C <= '1' when res(8)='1' and (Ctrl_Alu = "000") else '0';
end Behavioral;

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VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
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@ -265,56 +265,63 @@ Stage4 : Stage_Mem_Re PORT MAP (
Out_Op => Re_Op);
-- Instruction code
-- ADD 00000001
-- MUL 00000010
-- SUB 00000011
-- DIV 00000100
-- COP 00000101
-- AFC 00000110
-- LOAD 00000111
-- STORE 00001000
-- ADD x"01"
-- MUL x"02"
-- SUB x"03"
-- DIV x"04"
-- COP x"05"
-- AFC x"06"
-- LOAD x"07"
-- STORE x"08"
-- INF x"09"
-- SUP x"0A"
-- EQ x"0B"
-- NOT x"0C"
-- AND x"0D"
-- OR x"0E"
-- NOP x"FF"
-- Mux post registers
Di_FinalB <= Di_B when
Di_OP = "00000110" -- AFC
Di_OP = x"06" -- AFC
else Di_RegB;
-- Mux post ALU
Ex_FinalB <= Ex_B when
Ex_Op = "00000110" --AFC
or Ex_Op = "00000101" --COP
or Ex_Op = "00000111" --LOAD
or Ex_Op = "00001000" --STORE
Ex_Op = x"06" --AFC
or Ex_Op = x"05" --COP
or Ex_Op = x"07" --LOAD
or Ex_Op = x"08" --STORE
else Ex_Res_Alu;
-- LC pre ALU
Ex_Ctrl_ALu <= "000" when Ex_Op = "00000001" --ADD
else "001" when Ex_Op = "00000011" -- SUB
else "010" when Ex_Op = "00000010" -- MUL
else "100" when Ex_Op = "00000100" -- DIV
Ex_Ctrl_ALu <= "000" when Ex_Op = x"01" --ADD
else "001" when Ex_Op = x"03" -- SUB
else "010" when Ex_Op = x"02" -- MUL
else "100" when Ex_Op = x"04" -- DIV
else "111"; --ERROR
-- Mux post data memory
Mem_FinalB <= Mem_B when
Mem_Op = "00000110" --AFC
or Mem_Op = "00000101" --COP
or Mem_Op = "00000001" --ADD
or Mem_Op = "00000011" -- SUB
or Mem_Op = "00000010" -- MUL
or Mem_Op = "00000100" -- DIV
Mem_Op = x"06" --AFC
or Mem_Op = x"05" --COP
or Mem_Op = x"01" --ADD
or Mem_Op = x"03" -- SUB
or Mem_Op = x"02" -- MUL
or Mem_Op = x"04" -- DIV
else Mem_FinalB ; --LOAD & STORE
-- Mux pre data memory
Mem_Addr <= Mem_B when Mem_Op = "00000111" --LOAD
Mem_Addr <= Mem_B when Mem_Op = x"07" --LOAD
else Mem_A; --STORE
-- LC pre data memory
Mem_RW <= '1' when Mem_Op = "00000111" --LOAD
Mem_RW <= '1' when Mem_Op = x"07" --LOAD
else '0'; --STORE
-- LC post Pip_Mem_Re
Re_W <= '0' when Re_Op = "00001000" --STORE
Re_W <= '0' when Re_Op = x"08" --STORE
else '1';
CU : ControlUnit port map (

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VHDL/ALU/ALU.xpr
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@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="32"/>
<Option Name="WTXSimLaunchSim" Val="62"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>

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VHDL/ALU/Test_Alu_behav.wcfg
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@ -10,13 +10,13 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="5763000fs"></ZoomStartTime>
<ZoomEndTime time="93063001fs"></ZoomEndTime>
<Cursor1Time time="35663000fs"></Cursor1Time>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="207800001fs"></ZoomEndTime>
<Cursor1Time time="30600000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="142"></NameColumnWidth>
<ValueColumnWidth column_width="132"></ValueColumnWidth>
<ValueColumnWidth column_width="128"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="8" />
<wave_markers>
@ -34,10 +34,9 @@
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Alu/local_Ctrl_Alu">
<obj_property name="ElementShortName">local_Ctrl_Alu[2:0]</obj_property>
<obj_property name="ObjectShortName">local_Ctrl_Alu[2:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
<obj_property name="isExpanded"></obj_property>
<obj_property name="ElementShortName">local_Ctrl_Alu[7:0]</obj_property>
<obj_property name="ObjectShortName">local_Ctrl_Alu[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Alu/local_S">
<obj_property name="ElementShortName">local_S[7:0]</obj_property>