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added the alea handling and IP implementation

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Raphaël LACROIX 2023-05-29 19:54:40 +02:00
parent 46465784b8
commit ae447be456
3 changed files with 125 additions and 15 deletions
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67
VHDL/ALU/ALU.srcs/sources_1/new/AleaControler.vhd Normal file
View file

@ -0,0 +1,67 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Instruction coEX
-- ADD 00000001
-- MUL 00000010
-- SUB 00000011
-- DIV 00000100
-- COP 00000101
-- AFC 00000110
-- LOAD 00000111
-- STORE 00001000
-- INF 00001001
-- SUP 00001010
-- EQ 00001011
-- NOT 00001100
-- AND 00001101
-- OR 00001110
-- NOP 11111111
-- when the just entered instruction causes a problem with an instruction already in the EX or Mem stage (a write-Back stage would not cause any harm) we:
-- we freeze IP on the current instruction
-- we insert NOPs in the LI_DI OP while there is a conflict in order to let the problematic instruction finish
entity ControlUnit is
Port (
-- get the current op and variables from the 3 pipelines stages that can interract
Op_DI, Op_EX, Op_Mem : in STD_LOGIC_VECTOR (7 downto 0);
A_EX, A_Mem : in STD_LOGIC_VECTOR (7 downto 0);
B_DI : in STD_LOGIC_VECTOR (7 downto 0);
C_DI : in STD_LOGIC_VECTOR (7 downto 0);
CNTRL : out STD_LOGIC);
end ControlUnit;
architecture Behavioral of ControlUnit is
signal alea_DI_EX or alea_DI_MEM: STD_LOGIC;
signal is_LI_arithmetic, is_DI_arithmetic: STD_LOGIC;
begin
CNTRL <= alea_DI_EX or alea_DI_MEM; -- either a problem between the 1st and 2nd or 1st and 3rd
alea_DI_EX <= '1' when
-- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read)
(
-- check Op1 & Op2
(OP_DI != x"08" or OP_DI != x"ff") and (Op_EX != x"06" Op_EX != x"ff") and
-- check Registers are the same
(A_Ex = B_DI) or (A_EX = C_DI)
)
else '0';
alea_DI_Mem <= '1' when
-- read after write : Op1 other than STORE/NOP, op2 other than AFC/NOP, R(write) = R(read)
(
-- check Op1 & Op2
(OP_DI != x"08" or OP_DI != x"ff") and (Op_Mem != x"06" Op_Mem!= x"ff") and
-- check Registers are the same
(A_Mem = B_DI) or (A_Mem = C_DI)
)
else '0';
end Behavioral;

4
VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd
View file

@ -37,7 +37,7 @@ entity IP is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; -- rst when 0
LOAD : in STD_LOGIC;
EN : in STD_LOGIC; -- enable when 1
EN : in STD_LOGIC; -- enable when 0
Din : in STD_LOGIC_VECTOR (7 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0));
end IP;
@ -53,7 +53,7 @@ begin
aux <= x"00";
elsif (LOAD = '1') then
aux <= Din;
elsif (EN = '1') then
elsif (EN = '0') then
aux <= aux + x"01";
end if;
end process;

69
VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
View file

@ -36,8 +36,17 @@ entity Pipeline is
end Pipeline;
architecture Behavioral of Pipeline is
signal IP : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
component IP is
port ( CK : in STD_LOGIC;
RST : in STD_LOGIC; -- rst when 0
LOAD : in STD_LOGIC;
EN : in STD_LOGIC; -- enable when 1
Din : in STD_LOGIC_VECTOR (7 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal IP_out : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal Rst : STD_LOGIC; -- to modify
component InstructionMemory
@ -58,7 +67,7 @@ architecture Behavioral of Pipeline is
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
);
);
end component;
signal Li_A, Li_Op, Li_B, Li_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
@ -73,7 +82,7 @@ architecture Behavioral of Pipeline is
Clk : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (7 downto 0);
QB : out STD_LOGIC_VECTOR (7 downto 0)
);
);
end component;
signal Di_A, Di_Op, Di_B, Di_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
@ -89,7 +98,7 @@ architecture Behavioral of Pipeline is
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0);
Out_C : out STD_LOGIC_VECTOR (7 downto 0)
);
);
end component;
signal Ex_A, Ex_Op, Ex_B, Ex_C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
@ -102,7 +111,8 @@ architecture Behavioral of Pipeline is
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
C : out STD_LOGIC
);
end component;
signal Ex_Ctrl_ALu, Ex_Res_Alu, Ex_FinalB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
@ -116,7 +126,7 @@ architecture Behavioral of Pipeline is
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
);
);
end component;
signal Mem_A, Mem_Op, Mem_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
@ -129,7 +139,8 @@ architecture Behavioral of Pipeline is
Rw : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (7 downto 0));
Data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component Stage_Mem_Re
@ -140,17 +151,40 @@ architecture Behavioral of Pipeline is
Out_A : out STD_LOGIC_VECTOR (7 downto 0);
Out_B : out STD_LOGIC_VECTOR (7 downto 0);
Out_Op : out STD_LOGIC_VECTOR (7 downto 0)
);
);
end component;
component ControlUnit is
Port ( Op_DI, Op_EX, Op_Mem : in STD_LOGIC_VECTOR (7 downto 0);
A_EX, A_Mem : in STD_LOGIC_VECTOR (7 downto 0);
B_DI : in STD_LOGIC_VECTOR (7 downto 0);
C_DI : in STD_LOGIC_VECTOR (7 downto 0);
CNTRL : out STD_LOGIC
);
end component;
signal Re_A, Re_Op, Re_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal Re_W : STD_LOGIC;
-- to control jumping and where to jump
signal addr_to_jump : STD_LOGIC;
signal jump : STD_LOGIC;
signal nop_Cntrl : STD_LOGIC;
begin
-- instructionPointer
inst_point : IP port map (
CLK=> clk,
Dout=> IP_out,
Din => addr_to_jump,
RST => "1",
EN => nop_Cntrl,
LOAD => jump);
-- instructionMemory
MemInst : InstructionMemory PORT MAP (
Addr => IP,
Addr => IP_out,
Clk => Clk,
Inst_out => Li);
@ -159,7 +193,7 @@ Stage1 : Stage_Li_Di PORT MAP (
In_A => Li(23 downto 16),
In_B => Li(15 downto 8),
In_C => Li(7 downto 0),
In_Op => Li(31 downto 24),
In_Op => OP_LI_DI,
Clk => Clk,
Out_A => Di_A,
Out_B => Di_B,
@ -283,5 +317,14 @@ Mem_RW <= '1' when Mem_Op = "00000111" --LOAD
Re_W <= '0' when Re_Op = "00001000" --STORE
else '1';
CU : ControlUnit port map (
Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op;
A_EX =< Di_A, A_Mem => Ex_A;
B_DI => Li(15 downto 8);
C_DI => Li(7 downto 0);
CNTRL => nop_Cntrl);
end Behavioral;
-- in case of alea : replace li(31 downto 24) by NOP
OP_LI_DI<= X"ff" when nop_Cntrl='1' else li(31 downto 24);