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Lacroix Raphael 2023-05-29 21:57:46 +02:00
parent 12859bebe9
commit c462cd7fe7
38 changed files with 148 additions and 168 deletions
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VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
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VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:35:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
eof:1280488146
eof:2032391319

2
VHDL/ALU/ALU.cache/wt/project.wpc
View file

@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:17
6d6f64655f636f756e7465727c4755494d6f6465:18
eof:

59
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
View file

@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon May 29 21:38:21 2023">
<application name="pa" timeStamp="Mon May 29 21:42:56 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
<property name="ProjectIteration" value="4" type="ProjectIteration"/>
@ -17,16 +17,18 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="15" type="JavaHandler"/>
<property name="AddSources" value="16" type="JavaHandler"/>
<property name="CloseProject" value="2" type="JavaHandler"/>
<property name="EditDelete" value="2" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenProject" value="2" type="JavaHandler"/>
<property name="OpenProject" value="3" type="JavaHandler"/>
<property name="RunImplementation" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="6" type="JavaHandler"/>
<property name="ShowView" value="4" type="JavaHandler"/>
<property name="SimulationRelaunch" value="3" type="JavaHandler"/>
<property name="SimulationRun" value="63" type="JavaHandler"/>
<property name="SimulationRun" value="68" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="5" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
@ -34,47 +36,49 @@ This means code written to parse this file will need to be revisited each subseq
<item name="Gui Handlers">
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
<property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="1" type="GuiHandlerData"/>
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="50" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="52" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="19" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="22" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="13" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="14" type="GuiHandlerData"/>
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="239" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="265" type="GuiHandlerData"/>
<property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="77" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="86" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="46" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="26" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="1" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="3" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="1" type="GuiHandlerData"/>
<property name="LogPanel_COPY" value="1" type="GuiHandlerData"/>
<property name="LogPanel_FIND" value="1" type="GuiHandlerData"/>
<property name="LogPanel_PAUSE_OUTPUT" value="2" type="GuiHandlerData"/>
<property name="LogPanel_TOGGLE_COLUMN_SELECTION_MODE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="18" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="64" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="66" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="9" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="22" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="43" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="45" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="14" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="6" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="6" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="7" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="21" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="1" type="GuiHandlerData"/>
@ -84,34 +88,37 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="64" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="69" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="19" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="1" type="GuiHandlerData"/>
<property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="110" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="112" type="GuiHandlerData"/>
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="4" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="8" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="16" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="18" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="13" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="42" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="10" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="47" type="GuiHandlerData"/>
<property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/>
<property name="WaveformView_NEXT_MARKER" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="22" type="GuiMode"/>
<property name="GuiMode" value="1" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="16" type="TclMode"/>
<property name="TclMode" value="0" type="TclMode"/>
</item>
</section>
</application>

2
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
View file

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
<File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
<File Type="RDS-RDS" Name="ALU.vds"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
View file

Binary file not shown.

11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_vhdl.prj
View file

@ -1,16 +1,7 @@
# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../ALU.srcs/sources_1/new/ALU.vhd" \
"../../../../ALU.srcs/sources_1/new/IP.vhd" \
"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \
"../../../../ALU.srcs/sources_1/new/Memory.vhd" \
"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \
"../../../../ALU.srcs/sources_1/new/Registers.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \
"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \
"../../../../ALU.srcs/sim_1/new/test_total.vhd" \
"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \
# Do not sort compile order
nosort

10
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
View file

@ -199,3 +199,13 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Pro
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total

6
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Mon May 29 21:34:18 CEST 2023
# Generated by Vivado on Mon May 29 21:56:43 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,5 +23,5 @@ then
exit $RETVAL
fi
}
echo "xvhdl --incr --relax -prj Test_Alu_vhdl.prj"
ExecStep xvhdl --incr --relax -prj Test_Alu_vhdl.prj 2>&1 | tee -a compile.log
echo "xvhdl --incr --relax -prj Test_total_vhdl.prj"
ExecStep xvhdl --incr --relax -prj Test_total_vhdl.prj 2>&1 | tee -a compile.log

6
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
View file

@ -1,6 +1,6 @@
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log
Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log
Using 8 slave threads.
Starting static elaboration
WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:325]
@ -24,5 +24,5 @@ Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_e
Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default]
Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default]
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default]
Compiling architecture behavioral of entity xil_defaultlib.test_alu
Built simulation snapshot Test_Alu_behav
Compiling architecture behavioral of entity xil_defaultlib.test_total
Built simulation snapshot Test_total_behav

4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Mon May 29 21:34:19 CEST 2023
# Generated by Vivado on Mon May 29 21:56:45 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,4 +23,4 @@ then
exit $RETVAL
fi
}
ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log
ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log

4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
# Generated by Vivado on Mon May 29 21:34:22 CEST 2023
# Generated by Vivado on Mon May 29 21:56:47 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,4 +23,4 @@ then
exit $RETVAL
fi
}
ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log
ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log

14
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
View file

@ -2,11 +2,11 @@
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 19:45:48 2023
# Process ID: 341146
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
# Start of session at: Mon May 29 21:55:04 2023
# Process ID: 509586
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
source /home/rlacroix/Bureau/4ir/syst -notrace

17
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
View file

@ -2,12 +2,13 @@
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon May 29 19:45:48 2023
# Process ID: 341146
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
# Start of session at: Mon May 29 21:55:04 2023
# Process ID: 509586
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 19:45:49 2023...
source /home/rlacroix/Bureau/4ir/syst -notrace
couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023...

12
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@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:26 2023
# Process ID: 831441
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace

13
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@ -1,13 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sun May 14 22:27:26 2023
# Process ID: 831441
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
#-----------------------------------------------------------
source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:27 2023...

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
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@ -43,38 +43,20 @@
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern void execute_87(char*, char *);
extern void execute_79(char*, char *);
extern void execute_80(char*, char *);
extern void execute_81(char*, char *);
extern void execute_82(char*, char *);
extern void execute_83(char*, char *);
extern void execute_84(char*, char *);
extern void execute_85(char*, char *);
extern void execute_86(char*, char *);
extern void execute_53(char*, char *);
extern void execute_54(char*, char *);
extern void execute_55(char*, char *);
extern void execute_61(char*, char *);
extern void execute_63(char*, char *);
extern void execute_65(char*, char *);
extern void execute_66(char*, char *);
extern void execute_67(char*, char *);
extern void execute_69(char*, char *);
extern void execute_71(char*, char *);
extern void execute_72(char*, char *);
extern void execute_74(char*, char *);
extern void execute_76(char*, char *);
extern void execute_78(char*, char *);
extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
extern void execute_51(char*, char *);
extern void execute_52(char*, char *);
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[24] = {(funcp)execute_87, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_54, (funcp)execute_55, (funcp)execute_61, (funcp)execute_63, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_69, (funcp)execute_71, (funcp)execute_72, (funcp)execute_74, (funcp)execute_76, (funcp)execute_78, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 24;
funcp funcTab[6] = {(funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_51, (funcp)execute_52, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 6;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 24);
iki_vhdl_file_variable_register(dp + 23824);
iki_vhdl_file_variable_register(dp + 23880);
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 6);
iki_vhdl_file_variable_register(dp + 3576);
iki_vhdl_file_variable_register(dp + 3632);
/*Populate the transaction function pointer field in the whole net structure */

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2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
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@ -1,5 +1,5 @@
1685381189
1685382347
72
77
1
aef36ef3a0d94dac9e6058b656907afd

22
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
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@ -1,6 +1,6 @@
webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Mon May 29 21:34:21 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Mon May 29 21:48:24 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -14,15 +14,15 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "71" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "76" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "1000.000 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "19" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key File_Counter -value "10" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
@ -30,13 +30,13 @@ webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\co
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "60 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "47 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "22" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "17" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "5" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "8" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "1.43_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "205220_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2966348998 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Compiler_Time -value "1.16_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "200496_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3254441618 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

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@ -1,6 +1,6 @@
{
crc : 3586580812418567682 ,
crc : 3751694400990100050 ,
ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" ,
buildDate : "Jun 14 2018" ,

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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
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@ -1,4 +1,4 @@
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 56337
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 49525
Design successfully loaded
Design Loading Memory Usage: 32728 KB (Peak: 32780 KB)
Design Loading CPU Usage: 30 ms
Design Loading Memory Usage: 32680 KB (Peak: 32740 KB)
Design Loading CPU Usage: 20 ms

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@ -2,8 +2,9 @@
2018.2
Jun 14 2018
20:07:38
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685388243,vhdl,,,,test_alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685386043,vhdl,,,,alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685389246,vhdl,,,,test_alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685390194,vhdl,,,,test_total,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685386043,vhdl,,,,ip,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685386043,vhdl,,,,instructionmemory,,,,,,,,
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685386043,vhdl,,,,datamemory,,,,,,,,

4
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@ -1,2 +1,2 @@
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Pipeline
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_total

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VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd
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@ -31,11 +31,11 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Alu is
entity Test_total is
-- Port ( );
end Test_Alu;
end Test_total;
architecture Behavioral of Test_Alu is
architecture Behavioral of test_total is
component Pipeline
@ -43,7 +43,8 @@ architecture Behavioral of Test_Alu is
end component;
constant clock_period : time := 10 ns;
signal clock : Std_logic;
signal clock : Std_logic := '0';
signal A : Std_logic := '0';
begin
-- instantiate
@ -57,5 +58,7 @@ begin
wait for 100ns;
end process;
A <= not A;
end Behavioral;

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VHDL/ALU/ALU.xpr
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@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="67"/>
<Option Name="WTXSimLaunchSim" Val="73"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -155,9 +155,8 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Test_Alu"/>
<Option Name="TopModule" Val="Test_total"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
@ -192,7 +191,9 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -201,7 +202,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>