started preparing tests
This commit is contained in:
Lacroix Raphael
parent
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69 changed files with 1871 additions and 645 deletions
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3437:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f636865636b5f74696d696e675f7265706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f6d6574686f646f6c6f67795f7265706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f6372656174655f74696d696e675f73756d6d6172795f7265706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e67636f6e73747261696e747377697a6172645f766965775f74696d696e675f636f6e73747261696e7473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3531:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f72657365745f746f5f64656661756c7473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6f7074696f6e73766965775f73686f775f7369676e616c5f696e6469636573:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6164645f6d61726b6572:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6e6578745f6d61726b6572:32:00:00
|
||||
eof:2255965904
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f6c6173745f74696d65:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f74696d655f30:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f6e6578745f6d61726b6572:33:00:00
|
||||
eof:2409938427
|
||||
|
|
|
|||
|
|
@ -1,17 +1,18 @@
|
|||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3638:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3736:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
|
||||
eof:2032391319
|
||||
eof:900808538
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:18
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:19
|
||||
eof:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746370673233362d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:414c55:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:506970656c696e65:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
|
|
@ -33,7 +33,7 @@ version:1
|
|||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313433342e3033314d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3237342e3230374d42:00:00
|
||||
eof:3465561614
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323673:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313637332e3239334d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3531332e3436394d42:00:00
|
||||
eof:2352502396
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Mon May 29 21:42:56 2023">
|
||||
<application name="pa" timeStamp="Tue May 30 00:39:30 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="4" type="ProjectIteration"/>
|
||||
|
|
@ -17,18 +17,19 @@ This means code written to parse this file will need to be revisited each subseq
|
|||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="16" type="JavaHandler"/>
|
||||
<property name="AddSources" value="17" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="2" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="2" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="3" type="JavaHandler"/>
|
||||
<property name="EditUndo" value="1" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="3" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="3" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="6" type="JavaHandler"/>
|
||||
<property name="ShowView" value="4" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="9" type="JavaHandler"/>
|
||||
<property name="ShowView" value="6" type="JavaHandler"/>
|
||||
<property name="SimulationRelaunch" value="3" type="JavaHandler"/>
|
||||
<property name="SimulationRun" value="68" type="JavaHandler"/>
|
||||
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
|
||||
<property name="SimulationRun" value="76" type="JavaHandler"/>
|
||||
<property name="TimingConstraintsWizard" value="2" type="JavaHandler"/>
|
||||
<property name="ToggleViewNavigator" value="3" type="JavaHandler"/>
|
||||
<property name="ToolsSettings" value="5" type="JavaHandler"/>
|
||||
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
|
||||
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
|
||||
|
|
@ -37,24 +38,29 @@ This means code written to parse this file will need to be revisited each subseq
|
|||
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
|
||||
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
|
||||
<property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="52" type="GuiHandlerData"/>
|
||||
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="2" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="11" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="59" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="22" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="24" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_EXISTING_OR_CREATE_NEW_CONSTRAINTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_FILE_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="14" type="GuiHandlerData"/>
|
||||
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
|
||||
<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="265" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="309" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="86" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="104" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_FIT" value="2" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_IN" value="46" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_OUT" value="26" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_FIT" value="5" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_IN" value="48" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_OUT" value="51" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="3" type="GuiHandlerData"/>
|
||||
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
|
|
@ -66,11 +72,11 @@ This means code written to parse this file will need to be revisited each subseq
|
|||
<property name="MainMenuMgr_CHECKPOINT" value="18" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EDIT" value="16" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="66" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="68" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="12" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="22" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="45" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="25" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="46" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="14" type="GuiHandlerData"/>
|
||||
|
|
@ -82,43 +88,59 @@ This means code written to parse this file will need to be revisited each subseq
|
|||
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="21" type="GuiHandlerData"/>
|
||||
<property name="OpenFileAction_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="OpenFileAction_OPEN_DIRECTORY" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="14" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
|
||||
<property name="OpenFileAction_OPEN_DIRECTORY" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REPORTS_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SET_AS_TOP" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="69" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="77" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RUN_POST_SYNTHESIS_FUNCTIONAL" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="19" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="20" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
|
||||
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="1" type="GuiHandlerData"/>
|
||||
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="3" type="GuiHandlerData"/>
|
||||
<property name="PrimaryClocksPanel_RECOMMENDED_CONSTRAINTS_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectTab_RELOAD" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="3" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
|
||||
<property name="RDIViews_WAVEFORM_VIEWER" value="112" type="GuiHandlerData"/>
|
||||
<property name="RDIViews_WAVEFORM_VIEWER" value="119" type="GuiHandlerData"/>
|
||||
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/>
|
||||
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="10" type="GuiHandlerData"/>
|
||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="25" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="18" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="13" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="6" type="GuiHandlerData"/>
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="10" type="GuiHandlerData"/>
|
||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="47" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="21" type="GuiHandlerData"/>
|
||||
<property name="TimingConstraintsWizard_CREATE_CHECK_TIMING_REPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="TimingConstraintsWizard_CREATE_METHODOLOGY_REPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="TimingConstraintsWizard_CREATE_TIMING_SUMMARY_REPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="TimingConstraintsWizard_VIEW_TIMING_CONSTRAINTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="51" type="GuiHandlerData"/>
|
||||
<property name="WaveformOptionsView_RESET_TO_DEFAULTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="WaveformOptionsView_SHOW_SIGNAL_INDICES" value="4" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_NEXT_MARKER" value="2" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_GOTO_LAST_TIME" value="4" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_GOTO_TIME_0" value="3" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_NEXT_MARKER" value="3" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="1" type="GuiMode"/>
|
||||
<property name="GuiMode" value="3" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="0" type="TclMode"/>
|
||||
<property name="TclMode" value="1" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
|
|
|||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_10.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_10.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_9.xml
Normal file
5
VHDL/ALU/ALU.runs/.jobs/vrs_config_9.xml
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="alejeune" Host="" Pid="846704">
|
||||
<Process Command="vivado" Owner="rlacroix" Host="" Pid="608282">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,52 +0,0 @@
|
|||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
create_project -in_memory -part xc7a35tcpg236-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project]
|
||||
set_property parent.project_path /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
|
||||
set_property ip_output_repo /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_vhdl -library xil_defaultlib /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 0
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top ALU -part xc7a35tcpg236-1
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef ALU.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
|
|
@ -1,238 +0,0 @@
|
|||
#-----------------------------------------------------------
|
||||
# Vivado v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:48:29 2023
|
||||
# Process ID: 846737
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
||||
# Command line: vivado -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.vds
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source ALU.tcl -notrace
|
||||
Command: synth_design -top ALU -part xc7a35tcpg236-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 846814
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcpg236-1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module ALU
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |CARRY4 | 18|
|
||||
|2 |LUT2 | 31|
|
||||
|3 |LUT3 | 6|
|
||||
|4 |LUT4 | 41|
|
||||
|5 |LUT5 | 12|
|
||||
|6 |LUT6 | 52|
|
||||
|7 |LD | 16|
|
||||
|8 |IBUF | 19|
|
||||
|9 |OBUF | 12|
|
||||
+------+-------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 207|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 16 instances were transformed.
|
||||
LD => LDCE: 16 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596
|
||||
WARNING: [Constraints 18-5210] No constraint will be written out.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023...
|
||||
Binary file not shown.
BIN
VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp
Normal file
BIN
VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp
Normal file
Binary file not shown.
67
VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl
Normal file
67
VHDL/ALU/ALU.runs/synth_1/Pipeline.tcl
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_msg_config -id {Common 17-41} -limit 10000000
|
||||
create_project -in_memory -part xc7a35tcpg236-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt} [current_project]
|
||||
set_property parent.project_path {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
|
||||
set_property ip_output_repo {/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip} [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_vhdl -library xil_defaultlib {
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd}
|
||||
{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd}
|
||||
}
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc {{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc}}
|
||||
set_property used_in_implementation false [get_files {{/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc}}]
|
||||
|
||||
set_param ips.enableIPCacheLiteLoad 0
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top Pipeline -part xc7a35tcpg236-1
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef Pipeline.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
593
VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
Normal file
593
VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
Normal file
|
|
@ -0,0 +1,593 @@
|
|||
#-----------------------------------------------------------
|
||||
# Vivado v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Tue May 30 00:39:32 2023
|
||||
# Process ID: 608313
|
||||
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
||||
# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
|
||||
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
|
||||
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Pipeline.tcl -notrace
|
||||
Command: synth_design -top Pipeline -part xc7a35tcpg236-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 608386
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 108497 ; free virtual = 138755
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
|
||||
INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
|
||||
INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
|
||||
INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
|
||||
INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187]
|
||||
INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
|
||||
INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
|
||||
INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
|
||||
INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
|
||||
INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
|
||||
INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
|
||||
INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229]
|
||||
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
|
||||
INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
|
||||
INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
|
||||
INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
|
||||
INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
|
||||
INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
|
||||
INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
|
||||
INFO: [Synth 8-637] synthesizing blackbox instance 'CU' of component 'ControlUnit' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
|
||||
WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50]
|
||||
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (10#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138756
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
|
||||
WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
|
||||
WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
|
||||
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1673.293 ; gain = 0.000 ; free physical = 108244 ; free virtual = 138510
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcpg236-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108339 ; free virtual = 138592
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[0]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[1]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[2]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[3]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[4]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[5]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[6]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[7]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[8]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[9]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[10]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[11]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[12]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[13]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[14]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[15]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[16]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[17]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[18]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[19]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[20]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[21]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[22]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[23]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[24]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[25]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[26]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[27]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[28]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[29]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[30]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[31]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[32]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[33]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[34]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[35]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[36]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[37]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[38]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[39]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[40]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[41]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[42]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[43]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[44]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[45]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[46]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[47]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[48]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[49]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[50]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[51]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[52]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[53]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[54]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[55]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[56]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[57]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[58]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[59]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[60]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[61]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[62]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[63]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[64]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[65]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[66]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[67]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[68]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[69]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[70]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[71]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[72]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[73]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[74]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[75]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[76]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[77]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[78]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[79]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[80]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[81]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[82]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[83]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[84]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[85]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[86]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[87]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[88]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[89]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[90]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[91]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[92]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[93]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[94]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[95]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108313 ; free virtual = 138566
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 9 Bit Adders := 1
|
||||
2 Input 8 Bit Adders := 2
|
||||
3 Input 8 Bit Adders := 1
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
8 Bit Registers := 288
|
||||
+---Muxes :
|
||||
257 Input 32 Bit Muxes := 1
|
||||
2 Input 8 Bit Muxes := 8
|
||||
2 Input 1 Bit Muxes := 279
|
||||
12 Input 1 Bit Muxes := 3
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module Pipeline
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 3
|
||||
2 Input 1 Bit Muxes := 2
|
||||
Module IP
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 8 Bit Adders := 1
|
||||
+---Registers :
|
||||
8 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module InstructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
+---Muxes :
|
||||
257 Input 32 Bit Muxes := 1
|
||||
Module Stage_Li_Di
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 4
|
||||
Module Registers
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 16
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 16
|
||||
Module Stage_Di_Ex
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 4
|
||||
Module ALU
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 9 Bit Adders := 1
|
||||
3 Input 8 Bit Adders := 1
|
||||
2 Input 8 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 4
|
||||
12 Input 1 Bit Muxes := 3
|
||||
Module Stage_Ex_Mem
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 3
|
||||
Module DataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 257
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 256
|
||||
Module Stage_Mem_Re
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 3
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55]
|
||||
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51]
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline.
|
||||
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108314 ; free virtual = 138572
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108174 ; free virtual = 138436
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+------+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+------+--------------+----------+
|
||||
|1 |ControlUnit | 1|
|
||||
+------+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------------------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------------------+------+
|
||||
|1 |ControlUnit_bbox_0 | 1|
|
||||
|2 |BUFG | 1|
|
||||
|3 |LUT1 | 2|
|
||||
|4 |LUT2 | 14|
|
||||
|5 |LUT3 | 2|
|
||||
|6 |LUT4 | 2|
|
||||
|7 |LUT5 | 4|
|
||||
|8 |LUT6 | 15|
|
||||
|9 |FDRE | 34|
|
||||
|10 |FDSE | 13|
|
||||
|11 |IBUF | 1|
|
||||
+------+-------------------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+-------------+------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+-------------+------------------+------+
|
||||
|1 |top | | 89|
|
||||
|2 | MemInst |InstructionMemory | 17|
|
||||
|3 | Stage1 |Stage_Li_Di | 11|
|
||||
|4 | Stage2 |Stage_Di_Ex | 11|
|
||||
|5 | inst_point |IP | 47|
|
||||
+------+-------------+------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 2292 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1673.293 ; gain = 142.434 ; free physical = 108225 ; free virtual = 138487
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108235 ; free virtual = 138498
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:54 . Memory (MB): peak = 1673.293 ; gain = 513.469 ; free physical = 108228 ; free virtual = 138491
|
||||
WARNING: [Constraints 18-5210] No constraint will be written out.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1697.305 ; gain = 0.000 ; free physical = 108229 ; free virtual = 138491
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue May 30 00:40:40 2023...
|
||||
BIN
VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb
Normal file
BIN
VHDL/ALU/ALU.runs/synth_1/Pipeline_utilization_synth.pb
Normal file
Binary file not shown.
|
|
@ -1,13 +1,13 @@
|
|||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
|
||||
| Date : Sun May 14 22:49:12 2023
|
||||
| Host : srv-tp06 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
|
||||
| Design : ALU
|
||||
| Date : Tue May 30 00:40:39 2023
|
||||
| Host : srv-tp04 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
|
||||
| Design : Pipeline
|
||||
| Device : 7a35tcpg236-1
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
|
|
@ -30,12 +30,12 @@ Table of Contents
|
|||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 120 | 0 | 20800 | 0.58 |
|
||||
| LUT as Logic | 120 | 0 | 20800 | 0.58 |
|
||||
| Slice LUTs* | 28 | 0 | 20800 | 0.13 |
|
||||
| LUT as Logic | 28 | 0 | 20800 | 0.13 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 16 | 0 | 41600 | 0.04 |
|
||||
| Register as Flip Flop | 0 | 0 | 41600 | 0.00 |
|
||||
| Register as Latch | 16 | 0 | 41600 | 0.04 |
|
||||
| Slice Registers | 47 | 0 | 41600 | 0.11 |
|
||||
| Register as Flip Flop | 47 | 0 | 41600 | 0.11 |
|
||||
| Register as Latch | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
|
|
@ -55,9 +55,9 @@ Table of Contents
|
|||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 16 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 13 | Yes | Set | - |
|
||||
| 34 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
|
|
@ -90,7 +90,7 @@ Table of Contents
|
|||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 31 | 0 | 106 | 29.25 |
|
||||
| Bonded IOB | 1 | 0 | 106 | 0.94 |
|
||||
| Bonded IPADs | 0 | 0 | 10 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 4 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
|
|
@ -115,7 +115,7 @@ Table of Contents
|
|||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
|
|
@ -149,24 +149,27 @@ Table of Contents
|
|||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 52 | LUT |
|
||||
| LUT4 | 41 | LUT |
|
||||
| LUT2 | 31 | LUT |
|
||||
| IBUF | 19 | IO |
|
||||
| CARRY4 | 18 | CarryLogic |
|
||||
| LDCE | 16 | Flop & Latch |
|
||||
| OBUF | 12 | IO |
|
||||
| LUT5 | 12 | LUT |
|
||||
| LUT3 | 6 | LUT |
|
||||
| FDRE | 34 | Flop & Latch |
|
||||
| LUT6 | 15 | LUT |
|
||||
| LUT2 | 14 | LUT |
|
||||
| FDSE | 13 | Flop & Latch |
|
||||
| LUT5 | 4 | LUT |
|
||||
| LUT4 | 2 | LUT |
|
||||
| LUT3 | 2 | LUT |
|
||||
| LUT1 | 2 | LUT |
|
||||
| IBUF | 1 | IO |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
+-------------+------+
|
||||
| Ref Name | Used |
|
||||
+-------------+------+
|
||||
| ControlUnit | 1 |
|
||||
+-------------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
|
|
@ -1,9 +1,14 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
|
||||
<File Type="RDS-DCP" Name="ALU.dcp"/>
|
||||
<File Type="PA-TCL" Name="ALU.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ALU.vds"/>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1685399970">
|
||||
<File Type="VDS-TIMING-PB" Name="Pipeline_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="Pipeline_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="Pipeline.dcp"/>
|
||||
<File Type="RDS-UTIL-PB" Name="Pipeline_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="Pipeline_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="Pipeline_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="Pipeline.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="Pipeline_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="Pipeline.tcl"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.vhd">
|
||||
|
|
@ -12,15 +17,76 @@
|
|||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/IP.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/InstructionMemory.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Memory.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Registers.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Di_Ex.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Ex_Mem.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Li_Di.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Stage_Mem_Re.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
<Option Name="TopModule" Val="Pipeline"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/cpu.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/cpu.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
|
|
|
|||
|
|
@ -6,4 +6,4 @@
|
|||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
vivado -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
|
|
@ -13,7 +13,7 @@ version:1
|
|||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3830:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
|
|
@ -28,4 +28,35 @@ version:1
|
|||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6165663336656633613064393464616339653630353862363536393037616664:506172656e742050412070726f6a656374204944:00
|
||||
eof:2773257219
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f7072696d6172795f636c6f636b73:31:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f7072696d6172795f636c6f636b73:31:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f67656e6572617465645f636c6f636b73:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f67656e6572617465645f636c6f636b73:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f666f727761726465645f636c6f636b73:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f666f727761726465645f636c6f636b73:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f65787465726e616c5f64656c617973:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f65787465726e616c5f64656c617973:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f696e7075745f64656c617973:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f696e7075745f64656c617973:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6f75747075745f64656c617973:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6f75747075745f64656c617973:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f636f6d62696e6174696f6e616c5f7061746873:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f636f6d62696e6174696f6e616c5f7061746873:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f7068795f6578636c5f636c6f636b5f67726f757073:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f7068795f6578636c5f636c6f636b5f67726f757073:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6c6f675f6578636c5f636c6f636b5f67726f757073:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6c6f675f6578636c5f636c6f636b5f67726f757073:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f6173796e635f636c6f636b5f67726f757073:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f6173796e635f636c6f636b5f67726f757073:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:6d697373696e675f66616c73655f7061746873:30:00:00
|
||||
74696d696e675f636f6e73747261696e74735f77697a617264:74696d696e675f636f6e73747261696e74735f77697a6172645c7573616765:61636365707465645f66616c73655f7061746873:30:00:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636865636b73:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:706f73745f77697a617264:00:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666f726d6174:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6661696c5f6f6e:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72657475726e5f737472696e67:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d65737361676573:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666f726365:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d776169766564:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f6d6574686f646f6c6f6779:7265706f72745f6d6574686f646f6c6f67795c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617070656e64:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
eof:2501282044
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ eval( EAInclude(ISEJScriptLib) );
|
|||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl" );
|
||||
"-log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl" );
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
*** Running vivado
|
||||
with args -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
with args -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
|
||||
|
||||
|
||||
****** Vivado v2018.2 (64-bit)
|
||||
|
|
@ -8,35 +8,219 @@
|
|||
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source ALU.tcl -notrace
|
||||
Command: synth_design -top ALU -part xc7a35tcpg236-1
|
||||
source Pipeline.tcl -notrace
|
||||
Command: synth_design -top Pipeline -part xc7a35tcpg236-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 846814
|
||||
INFO: Helper process launched with PID 608386
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 108497 ; free virtual = 138755
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
|
||||
INFO: [Synth 8-638] synthesizing module 'Pipeline' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
|
||||
INFO: [Synth 8-3491] module 'IP' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:36' bound to instance 'inst_point' of component 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
|
||||
INFO: [Synth 8-638] synthesizing module 'IP' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
|
||||
INFO: [Synth 8-256] done synthesizing module 'IP' (1#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd:45]
|
||||
INFO: [Synth 8-3491] module 'InstructionMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:35' bound to instance 'MemInst' of component 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:187]
|
||||
INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
|
||||
INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (2#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd:41]
|
||||
INFO: [Synth 8-3491] module 'Stage_Li_Di' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:34' bound to instance 'Stage1' of component 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:193]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Li_Di' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Li_Di' (3#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:47]
|
||||
INFO: [Synth 8-3491] module 'Registers' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:35' bound to instance 'StageRegisters' of component 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
|
||||
INFO: [Synth 8-638] synthesizing module 'Registers' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Registers' (4#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd:47]
|
||||
INFO: [Synth 8-3491] module 'Stage_Di_Ex' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:34' bound to instance 'Stage2' of component 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:217]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Di_Ex' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Di_Ex' (5#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd:47]
|
||||
INFO: [Synth 8-3491] module 'ALU' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:36' bound to instance 'Ual' of component 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:229]
|
||||
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
|
||||
INFO: [Synth 8-256] done synthesizing module 'ALU' (6#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:61]
|
||||
INFO: [Synth 8-3491] module 'Stage_Ex_Mem' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:34' bound to instance 'Stage3' of component 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:240]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Ex_Mem' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Ex_Mem' (7#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd:45]
|
||||
INFO: [Synth 8-3491] module 'DataMemory' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:35' bound to instance 'DataMem' of component 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
|
||||
INFO: [Synth 8-638] synthesizing module 'DataMemory' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
|
||||
INFO: [Synth 8-256] done synthesizing module 'DataMemory' (8#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd:44]
|
||||
INFO: [Synth 8-3491] module 'Stage_Mem_Re' declared at '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:34' bound to instance 'Stage4' of component 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:259]
|
||||
INFO: [Synth 8-638] synthesizing module 'Stage_Mem_Re' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Stage_Mem_Re' (9#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:45]
|
||||
INFO: [Synth 8-637] synthesizing blackbox instance 'CU' of component 'ControlUnit' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
|
||||
WARNING: [Synth 8-3848] Net Rst in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:50]
|
||||
WARNING: [Synth 8-3848] Net jump in module/entity Pipeline does not have driver. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:170]
|
||||
INFO: [Synth 8-256] done synthesizing module 'Pipeline' (10#1) [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:38]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138756
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst_point:LOAD to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:177]
|
||||
WARNING: [Synth 8-3295] tying undriven pin StageRegisters:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:205]
|
||||
WARNING: [Synth 8-3295] tying undriven pin DataMem:Rst to constant 0 [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:250]
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.902 ; gain = 142.434 ; free physical = 108498 ; free virtual = 138757
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
|
||||
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1673.293 ; gain = 0.000 ; free physical = 108244 ; free virtual = 138510
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcpg236-1
|
||||
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108337 ; free virtual = 138591
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108339 ; free virtual = 138592
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-5546] ROM "Mem" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[0]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[1]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[2]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[3]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[4]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[5]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[6]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[7]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[8]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[9]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[10]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[11]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[12]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[13]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[14]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "Regs_reg[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[0]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[1]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[2]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[3]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[4]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[5]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[6]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[7]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[8]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[9]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[10]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[11]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[12]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[13]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[14]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[15]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[16]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[17]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[18]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[19]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[20]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[21]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[22]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[23]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[24]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[25]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[26]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[27]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[28]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[29]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[30]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[31]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[32]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[33]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[34]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[35]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[36]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[37]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[38]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[39]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[40]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[41]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[42]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[43]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[44]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[45]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[46]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[47]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[48]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[49]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[50]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[51]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[52]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[53]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[54]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[55]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[56]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[57]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[58]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[59]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[60]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[61]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[62]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[63]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[64]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[65]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[66]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[67]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[68]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[69]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[70]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[71]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[72]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[73]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[74]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[75]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[76]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[77]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[78]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[79]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[80]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[81]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[82]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[83]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[84]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[85]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[86]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[87]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[88]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[89]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[90]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[91]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[92]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[93]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[94]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[95]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[96]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[97]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "Mem_reg[98]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'Mem_FinalB_reg' [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:261]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108313 ; free virtual = 138566
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
|
|
@ -44,16 +228,22 @@ Report RTL Partitions:
|
|||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
2 Input 9 Bit Adders := 1
|
||||
2 Input 8 Bit Adders := 2
|
||||
3 Input 8 Bit Adders := 1
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
8 Bit Registers := 288
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
257 Input 32 Bit Muxes := 1
|
||||
2 Input 8 Bit Muxes := 8
|
||||
2 Input 1 Bit Muxes := 279
|
||||
12 Input 1 Bit Muxes := 3
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
|
|
@ -61,13 +251,65 @@ Finished RTL Component Statistics
|
|||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module Pipeline
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 3
|
||||
2 Input 1 Bit Muxes := 2
|
||||
Module IP
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 8 Bit Adders := 1
|
||||
+---Registers :
|
||||
8 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module InstructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
+---Muxes :
|
||||
257 Input 32 Bit Muxes := 1
|
||||
Module Stage_Li_Di
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 4
|
||||
Module Registers
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 16
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 16
|
||||
Module Stage_Di_Ex
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 4
|
||||
Module ALU
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
3 Input 16 Bit Adders := 1
|
||||
2 Input 9 Bit Adders := 1
|
||||
3 Input 8 Bit Adders := 1
|
||||
2 Input 8 Bit Adders := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
2 Input 8 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 4
|
||||
12 Input 1 Bit Muxes := 3
|
||||
Module Stage_Ex_Mem
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 3
|
||||
Module DataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 257
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 256
|
||||
Module Stage_Mem_Re
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 3
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
|
|
@ -80,13 +322,115 @@ BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
|||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage1/Out_C_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd:55]
|
||||
WARNING: [Synth 8-3936] Found unconnected internal register 'Stage4/Out_A_reg' and it is trimmed from '8' to '4' bits. [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd:51]
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[0][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[1][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[2][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[3][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[4][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[5][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[6][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[7][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[8][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[9][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[10][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][4]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][3]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][2]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][1]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[11][0]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][7]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][6]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][5]) is unused and will be removed from module Pipeline.
|
||||
WARNING: [Synth 8-3332] Sequential element (DataMem/Mem_reg[12][4]) is unused and will be removed from module Pipeline.
|
||||
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108314 ; free virtual = 138572
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
|
|
@ -94,12 +438,17 @@ Report RTL Partitions:
|
|||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108174 ; free virtual = 138436
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
|
|
@ -111,7 +460,7 @@ Report RTL Partitions:
|
|||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:52 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138433
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
|
|
@ -135,7 +484,7 @@ Start Final Netlist Cleanup
|
|||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
|
|
@ -148,7 +497,7 @@ Report Check Netlist:
|
|||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
|
|
@ -160,78 +509,84 @@ Report RTL Partitions:
|
|||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
+------+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+------+--------------+----------+
|
||||
|1 |ControlUnit | 1|
|
||||
+------+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |CARRY4 | 18|
|
||||
|2 |LUT2 | 31|
|
||||
|3 |LUT3 | 6|
|
||||
|4 |LUT4 | 41|
|
||||
|5 |LUT5 | 12|
|
||||
|6 |LUT6 | 52|
|
||||
|7 |LD | 16|
|
||||
|8 |IBUF | 19|
|
||||
|9 |OBUF | 12|
|
||||
+------+-------+------+
|
||||
+------+-------------------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------------------+------+
|
||||
|1 |ControlUnit_bbox_0 | 1|
|
||||
|2 |BUFG | 1|
|
||||
|3 |LUT1 | 2|
|
||||
|4 |LUT2 | 14|
|
||||
|5 |LUT3 | 2|
|
||||
|6 |LUT4 | 2|
|
||||
|7 |LUT5 | 4|
|
||||
|8 |LUT6 | 15|
|
||||
|9 |FDRE | 34|
|
||||
|10 |FDSE | 13|
|
||||
|11 |IBUF | 1|
|
||||
+------+-------------------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 207|
|
||||
+------+---------+-------+------+
|
||||
+------+-------------+------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+-------------+------------------+------+
|
||||
|1 |top | | 89|
|
||||
|2 | MemInst |InstructionMemory | 17|
|
||||
|3 | Stage1 |Stage_Li_Di | 11|
|
||||
|4 | Stage2 |Stage_Di_Ex | 11|
|
||||
|5 | inst_point |IP | 47|
|
||||
+------+-------------+------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108171 ; free virtual = 138434
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 2292 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1673.293 ; gain = 142.434 ; free physical = 108225 ; free virtual = 138487
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:53 . Memory (MB): peak = 1673.293 ; gain = 501.824 ; free physical = 108235 ; free virtual = 138498
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 16 instances were transformed.
|
||||
LD => LDCE: 16 instances
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
159 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596
|
||||
synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:54 . Memory (MB): peak = 1673.293 ; gain = 513.469 ; free physical = 108228 ; free virtual = 138491
|
||||
WARNING: [Constraints 18-5210] No constraint will be written out.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023...
|
||||
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_synth.rpt -pb Pipeline_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1697.305 ; gain = 0.000 ; free physical = 108229 ; free virtual = 138491
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue May 30 00:40:40 2023...
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ else
|
|||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1'
|
||||
HD_PWD='/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
|
|
@ -36,4 +36,4 @@ EAStep()
|
|||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
EAStep vivado -log Pipeline.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@
|
|||
# Vivado v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Sun May 14 22:48:29 2023
|
||||
# Process ID: 846737
|
||||
# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
||||
# Command line: vivado -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.vds
|
||||
# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
||||
# Start of session at: Tue May 30 00:39:32 2023
|
||||
# Process ID: 608313
|
||||
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1
|
||||
# Command line: vivado -log Pipeline.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Pipeline.tcl
|
||||
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.vds
|
||||
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source ALU.tcl -notrace
|
||||
source Pipeline.tcl -notrace
|
||||
|
|
|
|||
Binary file not shown.
11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl
Normal file
11
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total.tcl
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb
Normal file
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_behav.wdb
Normal file
Binary file not shown.
16
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj
Normal file
16
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_total_vhdl.prj
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# compile vhdl design source files
|
||||
vhdl xil_defaultlib \
|
||||
"../../../../ALU.srcs/sources_1/new/ALU.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/IP.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/InstructionMemory.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Memory.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Pipeline.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Registers.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Stage_Li_Di.vhd" \
|
||||
"../../../../ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" \
|
||||
"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
|
|
@ -209,3 +209,11 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Pro
|
|||
INFO: [VRFC 10-307] analyzing entity Test_total
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_total
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity InstructionMemory
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Pipeline
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_total
|
||||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_total
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Script for compiling the simulation design source files
|
||||
#
|
||||
# Generated by Vivado on Mon May 29 21:56:43 CEST 2023
|
||||
# Generated by Vivado on Tue May 30 00:45:29 CEST 2023
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
#
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
|
|
|||
|
|
@ -3,26 +3,6 @@ Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
|||
Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log
|
||||
Using 8 slave threads.
|
||||
Starting static elaboration
|
||||
WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:325]
|
||||
WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:329]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling package std.standard
|
||||
Compiling package std.textio
|
||||
Compiling package ieee.std_logic_1164
|
||||
Compiling package ieee.std_logic_arith
|
||||
Compiling package ieee.std_logic_unsigned
|
||||
Compiling package ieee.numeric_std
|
||||
Compiling architecture behavioral of entity xil_defaultlib.IP [ip_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.InstructionMemory [instructionmemory_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.Stage_Li_Di [stage_li_di_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.Registers [registers_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.Stage_Di_Ex [stage_di_ex_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_ex_mem_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default]
|
||||
Compiling architecture behavioral of entity xil_defaultlib.test_total
|
||||
Built simulation snapshot Test_total_behav
|
||||
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Script for elaborating the compiled design
|
||||
#
|
||||
# Generated by Vivado on Mon May 29 21:56:45 CEST 2023
|
||||
# Generated by Vivado on Tue May 30 00:45:30 CEST 2023
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
#
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Script for simulating the design by launching the simulator
|
||||
#
|
||||
# Generated by Vivado on Mon May 29 21:56:47 CEST 2023
|
||||
# Generated by Vivado on Tue May 30 00:45:32 CEST 2023
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
#
|
||||
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
|
|
|||
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.jou
Normal file
12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.jou
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Mon May 29 21:49:02 2023
|
||||
# Process ID: 507565
|
||||
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/rlacroix/Bureau/4ir/syst -notrace
|
||||
14
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.log
Normal file
14
VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_507565.backup.log
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.2 (64-bit)
|
||||
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
# Start of session at: Mon May 29 21:49:02 2023
|
||||
# Process ID: 507565
|
||||
# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source /home/rlacroix/Bureau/4ir/syst -notrace
|
||||
couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory
|
||||
INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:49:02 2023...
|
||||
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
|||
1685381189
|
||||
1685382347
|
||||
77
|
||||
78
|
||||
1
|
||||
aef36ef3a0d94dac9e6058b656907afd
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Mon May 29 21:48:24 2023" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key date_generated -value "Mon May 29 23:52:36 2023" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
|
||||
|
|
@ -14,29 +14,19 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
|
|||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "76" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "77" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "1000.000 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key File_Counter -value "10" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Code -value "47 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Processes -value "5" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Instances -value "8" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Time -value "1.16_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Memory -value "200496_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 3254441618 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Memory -value "122616_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 1575937485 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
|
|
|
|||
|
|
@ -2,3 +2,6 @@ Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -sim
|
|||
Design successfully loaded
|
||||
Design Loading Memory Usage: 32680 KB (Peak: 32740 KB)
|
||||
Design Loading CPU Usage: 20 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 122616 KB (Peak: 179952 KB)
|
||||
Simulation CPU Usage: 30 ms
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
-wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Test_total_behav" "xil_defaultlib.Test_total" -log "elaborate.log"
|
||||
|
|
@ -0,0 +1 @@
|
|||
Breakpoint File Version 1.0
|
||||
Binary file not shown.
|
|
@ -0,0 +1,120 @@
|
|||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern void execute_84(char*, char *);
|
||||
extern void execute_76(char*, char *);
|
||||
extern void execute_77(char*, char *);
|
||||
extern void execute_78(char*, char *);
|
||||
extern void execute_79(char*, char *);
|
||||
extern void execute_80(char*, char *);
|
||||
extern void execute_81(char*, char *);
|
||||
extern void execute_82(char*, char *);
|
||||
extern void execute_83(char*, char *);
|
||||
extern void execute_51(char*, char *);
|
||||
extern void execute_52(char*, char *);
|
||||
extern void execute_58(char*, char *);
|
||||
extern void execute_60(char*, char *);
|
||||
extern void execute_62(char*, char *);
|
||||
extern void execute_63(char*, char *);
|
||||
extern void execute_64(char*, char *);
|
||||
extern void execute_66(char*, char *);
|
||||
extern void execute_68(char*, char *);
|
||||
extern void execute_69(char*, char *);
|
||||
extern void execute_71(char*, char *);
|
||||
extern void execute_73(char*, char *);
|
||||
extern void execute_75(char*, char *);
|
||||
extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
|
||||
extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[24] = {(funcp)execute_84, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_51, (funcp)execute_52, (funcp)execute_58, (funcp)execute_60, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_66, (funcp)execute_68, (funcp)execute_69, (funcp)execute_71, (funcp)execute_73, (funcp)execute_75, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
|
||||
const int NumRelocateId= 24;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/Test_total_behav/xsim.reloc", (void **)funcTab, 24);
|
||||
iki_vhdl_file_variable_register(dp + 23824);
|
||||
iki_vhdl_file_variable_register(dp + 23880);
|
||||
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/Test_total_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/Test_total_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/Test_total_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/Test_total_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/Test_total_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
|
|
@ -0,0 +1,5 @@
|
|||
1685389741
|
||||
1685390103
|
||||
17
|
||||
1
|
||||
aef36ef3a0d94dac9e6058b656907afd
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
version = "1.0";
|
||||
clients =
|
||||
(
|
||||
{ client_name = "project";
|
||||
rules = (
|
||||
{
|
||||
context="software_version_and_target_device";
|
||||
xml_map="software_version_and_target_device";
|
||||
html_map="software_version_and_target_device";
|
||||
html_format="UserEnvStyle";
|
||||
},
|
||||
{
|
||||
context="user_environment";
|
||||
xml_map="user_environment";
|
||||
html_map="user_environment";
|
||||
html_format="UserEnvStyle";
|
||||
}
|
||||
);
|
||||
},
|
||||
|
||||
{ client_name = "xsim";
|
||||
rules = (
|
||||
{
|
||||
context="xsim\\command_line_options";
|
||||
xml_map="xsim\\command_line_options";
|
||||
html_map="xsim\\command_line_options";
|
||||
html_format="UnisimStatsStyle";
|
||||
},
|
||||
{
|
||||
context="xsim\\usage";
|
||||
xml_map="xsim\\usage";
|
||||
html_map="xsim\\usage";
|
||||
html_format="UnisimStatsStyle";
|
||||
}
|
||||
);
|
||||
}
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Tue May 30 00:45:27 2023" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "16" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "900.000 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Memory -value "118556_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 2993264675 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,12 @@
|
|||
|
||||
{
|
||||
crc : 747761180757353282 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total" ,
|
||||
buildDate : "Jun 14 2018" ,
|
||||
buildTime : "20:07:38" ,
|
||||
linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Test_total_behav/xsimk\" \"xsim.dir/Test_total_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Test_total_behav/obj/xsim_1.lnx64.o\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simulator_kernel.so\" \"/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/lib/lnx64.o/librdi_simbridge_kernel.so\"" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,41 @@
|
|||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=1024
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=65536
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=75
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
|
||||
OBJECT_NAME_COLUMN_WIDTH=75
|
||||
OBJECT_VALUE_COLUMN_WIDTH=75
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=75
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk
Executable file
BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/xsimk
Executable file
Binary file not shown.
|
|
@ -0,0 +1,4 @@
|
|||
Running: xsim.dir/Test_total_behav/xsimk -simmode gui -wdb Test_total_behav.wdb -simrunnum 0 -socket 36415
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 32720 KB (Peak: 32772 KB)
|
||||
Design Loading CPU Usage: 60 ms
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -3,12 +3,11 @@
|
|||
Jun 14 2018
|
||||
20:07:38
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685389246,vhdl,,,,test_alu,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685390194,vhdl,,,,test_total,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685386043,vhdl,,,,ip,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685386043,vhdl,,,,instructionmemory,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685397138,vhdl,,,,instructionmemory,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685386043,vhdl,,,,datamemory,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685388854,vhdl,,,,pipeline,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685397138,vhdl,,,,pipeline,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685386043,vhdl,,,,registers,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,,
|
||||
/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,,
|
||||
|
|
|
|||
|
|
@ -1,2 +0,0 @@
|
|||
INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
|
||||
INFO: [VRFC 10-307] analyzing entity Test_total
|
||||
Binary file not shown.
1
VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc
Normal file
1
VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc
Normal file
|
|
@ -0,0 +1 @@
|
|||
create_clock -period 10.000 -name Clk -waveform {0.000 5.000} [get_ports Clk]
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12.05.2023 17:40:52
|
||||
-- Design Name:
|
||||
-- Module Name: Test_Alu - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Test_total is
|
||||
-- Port ( );
|
||||
end Test_total;
|
||||
|
||||
architecture Behavioral of test_total is
|
||||
|
||||
|
||||
component Pipeline
|
||||
Port ( Clk : in STD_LOGIC);
|
||||
end component;
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
signal clock : Std_logic := '0';
|
||||
signal A : Std_logic := '0';
|
||||
begin
|
||||
|
||||
-- instantiate
|
||||
Pl : Pipeline PORT MAP (
|
||||
Clk => clock
|
||||
);
|
||||
|
||||
Clock_process : process
|
||||
begin
|
||||
clock <= not(clock);
|
||||
wait for 100ns;
|
||||
end process;
|
||||
|
||||
A <= not A;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="73"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="82"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
|
|
@ -129,21 +129,21 @@
|
|||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/cpu.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/cpu.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sim_1/new/test_total.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/VHDL.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
|
|
@ -161,6 +161,7 @@
|
|||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/Test_Alu_behav.wcfg"/>
|
||||
<Option Name="NLNetlistMode" Val="funcsim"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
|
|
@ -191,9 +192,7 @@
|
|||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
|
|
@ -202,9 +201,7 @@
|
|||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
|
|
|||
|
|
@ -3,60 +3,188 @@
|
|||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="Test_Alu_behav.wdb" id="1">
|
||||
<db_ref path="Test_total_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="Test_Alu" />
|
||||
<top_module name="Test_total" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="207800001fs"></ZoomEndTime>
|
||||
<ZoomEndTime time="255688068fs"></ZoomEndTime>
|
||||
<Cursor1Time time="30600000fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="142"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="128"></ValueColumnWidth>
|
||||
<ValueColumnWidth column_width="124"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="8" />
|
||||
<WVObjectSize size="41" />
|
||||
<wave_markers>
|
||||
<marker label="" time="1000000000" />
|
||||
<marker label="" time="994959000" />
|
||||
</wave_markers>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_A">
|
||||
<obj_property name="ElementShortName">local_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_A[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/Clk">
|
||||
<obj_property name="ElementShortName">Clk</obj_property>
|
||||
<obj_property name="ObjectShortName">Clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_B">
|
||||
<obj_property name="ElementShortName">local_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_B[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/IP_out">
|
||||
<obj_property name="ElementShortName">IP_out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">IP_out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_Ctrl_Alu">
|
||||
<obj_property name="ElementShortName">local_Ctrl_Alu[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_Ctrl_Alu[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/Rst">
|
||||
<obj_property name="ElementShortName">Rst</obj_property>
|
||||
<obj_property name="ObjectShortName">Rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_Alu/local_S">
|
||||
<obj_property name="ElementShortName">local_S[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">local_S[7:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Li">
|
||||
<obj_property name="ElementShortName">Li[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Li[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_N">
|
||||
<obj_property name="ElementShortName">local_N</obj_property>
|
||||
<obj_property name="ObjectShortName">local_N</obj_property>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Li_A">
|
||||
<obj_property name="ElementShortName">Li_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Li_A[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_O">
|
||||
<obj_property name="ElementShortName">local_O</obj_property>
|
||||
<obj_property name="ObjectShortName">local_O</obj_property>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Li_Op">
|
||||
<obj_property name="ElementShortName">Li_Op[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Li_Op[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_Z">
|
||||
<obj_property name="ElementShortName">local_Z</obj_property>
|
||||
<obj_property name="ObjectShortName">local_Z</obj_property>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Li_B">
|
||||
<obj_property name="ElementShortName">Li_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Li_B[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_Alu/local_C">
|
||||
<obj_property name="ElementShortName">local_C</obj_property>
|
||||
<obj_property name="ObjectShortName">local_C</obj_property>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Li_C">
|
||||
<obj_property name="ElementShortName">Li_C[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Li_C[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_A">
|
||||
<obj_property name="ElementShortName">Di_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_A[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_Op">
|
||||
<obj_property name="ElementShortName">Di_Op[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_Op[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_B">
|
||||
<obj_property name="ElementShortName">Di_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_B[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_C">
|
||||
<obj_property name="ElementShortName">Di_C[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_C[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_RegB">
|
||||
<obj_property name="ElementShortName">Di_RegB[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_RegB[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_FinalB">
|
||||
<obj_property name="ElementShortName">Di_FinalB[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_FinalB[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Di_C2">
|
||||
<obj_property name="ElementShortName">Di_C2[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Di_C2[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_A">
|
||||
<obj_property name="ElementShortName">Ex_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_A[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_Op">
|
||||
<obj_property name="ElementShortName">Ex_Op[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_Op[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_B">
|
||||
<obj_property name="ElementShortName">Ex_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_B[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_C">
|
||||
<obj_property name="ElementShortName">Ex_C[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_C[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_Ctrl_ALu">
|
||||
<obj_property name="ElementShortName">Ex_Ctrl_ALu[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_Ctrl_ALu[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_Res_Alu">
|
||||
<obj_property name="ElementShortName">Ex_Res_Alu[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_Res_Alu[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Ex_FinalB">
|
||||
<obj_property name="ElementShortName">Ex_FinalB[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Ex_FinalB[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/S_NFlag">
|
||||
<obj_property name="ElementShortName">S_NFlag</obj_property>
|
||||
<obj_property name="ObjectShortName">S_NFlag</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/S_Oflag">
|
||||
<obj_property name="ElementShortName">S_Oflag</obj_property>
|
||||
<obj_property name="ObjectShortName">S_Oflag</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/S_CFlag">
|
||||
<obj_property name="ElementShortName">S_CFlag</obj_property>
|
||||
<obj_property name="ObjectShortName">S_CFlag</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/S_ZFlag">
|
||||
<obj_property name="ElementShortName">S_ZFlag</obj_property>
|
||||
<obj_property name="ObjectShortName">S_ZFlag</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Mem_A">
|
||||
<obj_property name="ElementShortName">Mem_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_A[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Mem_Op">
|
||||
<obj_property name="ElementShortName">Mem_Op[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_Op[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Mem_B">
|
||||
<obj_property name="ElementShortName">Mem_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_B[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/Mem_RW">
|
||||
<obj_property name="ElementShortName">Mem_RW</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_RW</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Mem_Addr">
|
||||
<obj_property name="ElementShortName">Mem_Addr[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_Addr[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Mem_Data_Out">
|
||||
<obj_property name="ElementShortName">Mem_Data_Out[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_Data_Out[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Mem_FinalB">
|
||||
<obj_property name="ElementShortName">Mem_FinalB[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Mem_FinalB[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Re_A">
|
||||
<obj_property name="ElementShortName">Re_A[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Re_A[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Re_Op">
|
||||
<obj_property name="ElementShortName">Re_Op[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Re_Op[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/Re_B">
|
||||
<obj_property name="ElementShortName">Re_B[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">Re_B[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/Re_W">
|
||||
<obj_property name="ElementShortName">Re_W</obj_property>
|
||||
<obj_property name="ObjectShortName">Re_W</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/addr_to_jump">
|
||||
<obj_property name="ElementShortName">addr_to_jump[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">addr_to_jump[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/jump">
|
||||
<obj_property name="ElementShortName">jump</obj_property>
|
||||
<obj_property name="ObjectShortName">jump</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/Test_total/Pl/nop_Cntrl">
|
||||
<obj_property name="ElementShortName">nop_Cntrl</obj_property>
|
||||
<obj_property name="ObjectShortName">nop_Cntrl</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/Test_total/Pl/OP_LI_DI">
|
||||
<obj_property name="ElementShortName">OP_LI_DI[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">OP_LI_DI[7:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
|
|
|||
Loading…
Reference in a new issue