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1
.gitignore vendored
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@ -3,7 +3,6 @@ Processeur.cache/*
Processeur.hw/* Processeur.hw/*
Processeur.runs/* Processeur.runs/*
Processeur.sim/* Processeur.sim/*
Binaires/*
vivado* vivado*
.Xil .Xil
*.log *.log

138
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
View file

@ -9,22 +9,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports CLK]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
## Switches ## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}] set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}] set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}] set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}] set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}] set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}] set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}] set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}] set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] #set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] # set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] #set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
@ -44,28 +44,28 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
## LEDs ## LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property PACKAGE_PIN U16 [get_ports {led[0]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}] #set_property PACKAGE_PIN V13 [get_ports {led[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}] #set_property PACKAGE_PIN V3 [get_ports {led[9]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}] #set_property PACKAGE_PIN W3 [get_ports {led[10]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}] #set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {flag[0]}] #set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
@ -233,34 +233,34 @@ set_property PACKAGE_PIN U18 [get_ports btnC]
##VGA Connector ##VGA Connector
set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
set_property PACKAGE_PIN P19 [get_ports Hsync] #set_property PACKAGE_PIN P19 [get_ports Hsync]
set_property IOSTANDARD LVCMOS33 [get_ports Hsync] #set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
set_property PACKAGE_PIN R19 [get_ports Vsync] #set_property PACKAGE_PIN R19 [get_ports Vsync]
set_property IOSTANDARD LVCMOS33 [get_ports Vsync] #set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface ##USB-RS232 Interface
@ -271,12 +271,12 @@ set_property PACKAGE_PIN R19 [get_ports Vsync]
##USB HID (PS/2) ##USB HID (PS/2)
set_property PACKAGE_PIN C17 [get_ports PS2Clk] #set_property PACKAGE_PIN C17 [get_ports PS2Clk]
set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
set_property PULLUP true [get_ports PS2Clk] #set_property PULLUP true [get_ports PS2Clk]
set_property PACKAGE_PIN B17 [get_ports PS2Data] #set_property PACKAGE_PIN B17 [get_ports PS2Data]
set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
set_property PULLUP true [get_ports PS2Data] #set_property PULLUP true [get_ports PS2Data]
##Quad SPI Flash ##Quad SPI Flash

87
Processeur.srcs/sim_1/new/TestScreenDriver.vhd
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@ -1,87 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.07.2021 11:39:21
-- Design Name:
-- Module Name: TestScreenDriver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestScreenDriver is
-- Port ( );
end TestScreenDriver;
architecture Behavioral of TestScreenDriver is
component ScreenDriver
Generic ( Nb_bits : Natural
);
Port ( CLK : in STD_LOGIC;
Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
ValueAv : in STD_LOGIC;
IsInt : in STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (0 to 6);
OutDataAv : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal Value : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ValueAv : STD_LOGIC := '0';
signal IsInt : STD_LOGIC := '0';
signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
signal OutDataAv : STD_LOGIC := '0';
constant CLK_period : time := 10 ns;
begin
instance : ScreenDriver
Generic map ( Nb_bits => 16)
Port map ( CLK => CLK ,
Value => Value ,
ValueAv => ValueAv ,
IsInt => IsInt ,
OutData => OutData ,
OutDataAv => OutDataAv );
CLK_process : process
begin
CLK <= '1';
wait for CLK_period/2;
CLK <= '0';
wait for CLK_period/2;
end process;
process
begin
Value <= "0000000001010101" after 10 ns, "11111111111111111" after 80 ns;
ValueAv <= '1' after 10 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns;
IsInt <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 80 ns, '0' after 90 ns;
wait;
end process;
end Behavioral;

90
Processeur.srcs/sim_1/new/TestSystem.vhd
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@ -1,90 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.07.2021 08:34:17
-- Design Name:
-- Module Name: TestSystem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestSystem is
-- Port ( );
end TestSystem;
architecture Behavioral of TestSystem is
component System is
Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
btnC : in STD_LOGIC;
CLK : STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal btnC : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal Hsync : STD_LOGIC := '0';
signal Vsync : STD_LOGIC := '0';
constant CLK_period : time := 10 ns;
begin
instance : System
port map (vgaRed => vgaRed,
vgaBlue => vgaBlue,
vgaGreen => vgaGreen,
Hsync => Hsync,
Vsync => Vsync,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
btnC => btnC,
CLK => CLK);
CLK_process :process
begin
CLK <= '1';
wait for CLK_period/2;
CLK <= '0';
wait for CLK_period/2;
end process;
process
begin
PS2Clk <= '1' after 3200 us, '0' after 3250 us, '1' after 3300 us, '0' after 3350 us, '1' after 3400 us, '0' after 3450 us, '1' after 3500 us, '0' after 3550 us, '1' after 3600 us, '0' after 3650 us, '1' after 3700 us, '0' after 3750 us, '1' after 3800 us, '0' after 3850 us, '1' after 3900 us, '0' after 3950 us, '1' after 4000 us, '0' after 4050 us, '1' after 4100 us, '0' after 4150 us, '1' after 4200 us, '0' after 4250 us, '1' after 5000 us, '0' after 5050 us, '1' after 5100 us, '0' after 5150 us, '1' after 5200 us, '0' after 5250 us, '1' after 5300 us, '0' after 5350 us, '1' after 5400 us, '0' after 5450 us, '1' after 5500 us, '0' after 5550 us, '1' after 5600 us, '0' after 5650 us, '1' after 5700 us, '0' after 5750 us, '1' after 5800 us, '0' after 5850 us, '1' after 5900 us, '0' after 5950 us, '1' after 6000 us, '0' after 6050 us;
PS2Data <= '0' after 3200 us, '1' after 3300 us, '0' after 3400 us, '1' after 3500 us, '0' after 3600 us, '1' after 3700 us, '1' after 3800 us, '1' after 3900 us, '0' after 4000 us, '0' after 4100 us, '1' after 4200 us, '0' after 4300 us, '0' after 5000 us, '0' after 5100 us, '1' after 5200 us, '0' after 5300 us, '1' after 5400 us, '1' after 5500 us, '0' after 5600 us, '1' after 5700 us, '0' after 5800 us, '1' after 5900 us, '1' after 6000 us, '0' after 6100 us;
wait;
end process;
end Behavioral;

63
Processeur.srcs/sim_1/new/TestTableASCII.vhd
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@ -1,63 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 29.06.2021 16:16:32
-- Design Name:
-- Module Name: TestTableASCII - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.font.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestTableASCII is
-- Port ( );
end TestTableASCII;
architecture Behavioral of TestTableASCII is
component TableASCII is
Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
end component;
signal my_CodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000";
signal my_Font : STD_LOGIC_VECTOR (0 to 63) := (others => '0');
begin
instance : TableASCII
port map( CodeASCII => my_CodeASCII,
Font => my_Font
);
process
begin
my_CodeASCII <= "0000000" after 5 ns, "0000000" after 10 ns, "1000001" after 15 ns, "1000011" after 25 ns;
wait;
end process;
end Behavioral;

97
Processeur.srcs/sim_1/new/Test_Compteur.vhd
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@ -1,97 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2021 16:38:12
-- Design Name:
-- Module Name: Test_Compteur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Compteur is
-- Port ( );
end Test_Compteur;
architecture Behavioral of Test_Compteur is
constant screen_width : natural := 1280;
constant screen_height : natural := 1040;
subtype X_T is Natural range 0 to screen_width - 1;
subtype Y_T is Natural range 0 to screen_height - 1;
component Compteur_X is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out X_T;
Carry : out STD_LOGIC);
end component;
component Compteur_Y is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Y_T);
end component;
signal my_Carry : STD_LOGIC := '0';
signal my_Value : X_T := 0;
signal my_Value_Y : X_T := 0;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
constant CLK_period : time := 10 ns;
begin
inst_Compteur_X : Compteur_X
Port map ( CLK => my_CLK,
RST => my_RST,
Value => my_Value,
Carry => my_Carry);
inst_Compteur_Y : Compteur_Y
Port map ( CLK => my_Carry,
RST => my_RST,
Value => my_Value_Y);
CLK_process : process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
wait;
end process;
end Behavioral;

93
Processeur.srcs/sim_1/new/Test_Ecran.vhd
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@ -1,93 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 11:25:08
-- Design Name:
-- Module Name: Test_Ecran - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Ecran is
-- Port ( );
end Test_Ecran;
architecture Behavioral of Test_Ecran is
component Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in Natural;
Y : in Natural;
OUT_ON : out STD_LOGIC);
end component;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
signal my_Data_Av : STD_LOGIC := '0';
signal my_Data_IN : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_OUT_ON : STD_LOGIC := '0';
constant CLK_period : time := 10 ns;
begin
instance : Ecran
generic map( HEIGHT => 50,
WIDTH => 68
)
port map( CLK => my_CLK,
RST => my_RST,
Data_Av => my_Data_Av,
Data_IN => my_Data_IN,
X => my_X,
Y => my_Y,
OUT_ON => my_OUT_ON);
CLK_process : process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_Data_Av <= '1' after 0 ns;
my_Data_IN <= "0000001" after 0 ns, "0000010" after 40 ns, "0000011" after 80 ns, "0000100" after 120 ns, "0001101" after 140 ns, "0000101" after 150 ns, "0000000" after 170 ns, "0000001" after 180 ns, "0000010" after 220 ns;
wait;
end process;
end Behavioral;

72
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
View file

@ -37,26 +37,25 @@ end Test_Etage4_Memoire;
architecture Behavioral of Test_Etage4_Memoire is architecture Behavioral of Test_Etage4_Memoire is
component Etage4_Memoire is component Etage4_Memoire is
Generic ( Nb_bits : Natural; -- Taille d'un mot binaire Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables) Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale) Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd) Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd) Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd) Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd) Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL Port ( CLK : in STD_LOGIC; -- Clock
Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET RST : in STD_LOGIC; -- Reset
Port ( CLK : in STD_LOGIC; -- Clock IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
RST : in STD_LOGIC; -- Reset IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
end component; end component;
signal my_CLK : STD_LOGIC := '0'; signal my_CLK : STD_LOGIC := '0';
@ -67,15 +66,31 @@ architecture Behavioral of Test_Etage4_Memoire is
signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0'); signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
signal my_OUT_AddrRetour : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111"; constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111110101111111111"; constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1101111110101111111111";
constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111011001111111111"; constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1001111011001111111111";
constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000"; constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011"; constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100"; constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant CNULL : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant CWR : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant CCALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant CRET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant C0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant C1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant C2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant C3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant C5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant C7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant C12 : STD_LOGIC_VECTOR (7 downto 0) := "00001100";
constant C36 : STD_LOGIC_VECTOR (7 downto 0) := "00100100";
constant C54 : STD_LOGIC_VECTOR (7 downto 0) := "00110110";
constant C77 : STD_LOGIC_VECTOR (7 downto 0) := "01001101";
constant C100 : STD_LOGIC_VECTOR (7 downto 0) := "01100100";
constant CLK_period : time := 10 ns; constant CLK_period : time := 10 ns;
begin begin
@ -85,8 +100,6 @@ begin
Mem_size => 16, Mem_size => 16,
Adresse_mem_size => 4, Adresse_mem_size => 4,
Instruction_bus_size => 5, Instruction_bus_size => 5,
Mem_EBP_size => 8,
Adresse_size_mem_EBP => 3,
Bits_Controle_LC => Bits_Controle_LC, Bits_Controle_LC => Bits_Controle_LC,
Bits_Controle_MUX_IN => Bits_Controle_MUX_IN, Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP, Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
@ -100,7 +113,8 @@ begin
IN_Instruction => my_IN_Instruction, IN_Instruction => my_IN_Instruction,
OUT_A => my_OUT_A, OUT_A => my_OUT_A,
OUT_B => my_OUT_B, OUT_B => my_OUT_B,
OUT_Instruction => my_OUT_Instruction); OUT_Instruction => my_OUT_Instruction,
OUT_AddrRetour => my_OUT_AddrRetour);
CLK_process :process CLK_process :process
begin begin
@ -112,9 +126,9 @@ begin
process process
begin begin
my_IN_A <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns; my_IN_A <= C0 after 0 ns, C0 after 5 ns, C1 after 15 ns, C2 after 25 ns, C77 after 35 ns, C0 after 45 ns, C54 after 55 ns, C0 after 65 ns, C0 after 75 ns;
my_IN_B <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns; my_IN_B <= C0 after 0 ns, C36 after 5 ns, C5 after 15 ns, C7 after 25 ns, C3 after 35 ns, C12 after 45 ns, C1 after 55 ns, C100 after 65 ns, C0 after 75 ns;
my_IN_Instruction <= "00000" after 0 ns, "01011" after 4 ns, "01011" after 14 ns; my_IN_Instruction <= CNULL after 0 ns, CWR after 5 ns, CWR after 15 ns, CWR after 25 ns, CCALL after 35 ns, CWR after 45 ns, CCALL after 55 ns, CWR after 65 ns, CRET after 75 ns, CRET after 85 ns, CNULL after 95 ns;
my_RST <= '0' after 125 ns; my_RST <= '0' after 125 ns;
wait; wait;
end process; end process;

93
Processeur.srcs/sim_1/new/Test_Keyboard.vhd
View file

@ -1,93 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 08:21:55
-- Design Name:
-- Module Name: Test_Keyboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Keyboard is
-- Port ( );
end Test_Keyboard;
architecture Behavioral of Test_Keyboard is
component Keyboard is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal Data_read : STD_LOGIC := '0';
signal Data_av : STD_LOGIC := '0';
signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
signal alert : STD_LOGIC := '0';
constant CLK_period : TIME := 10 ns;
begin
CLK_process : process
begin
CLK <= '1';
wait for CLK_period/2;
CLK <= '0';
wait for CLK_period/2;
end process;
instance : Keyboard
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_read => Data_read,
Data_av => Data_av,
Data => Data,
alert => alert);
process
begin
PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
Data_read <= '1' after 3000 ns;
wait;
end process;
end Behavioral;

88
Processeur.srcs/sim_1/new/Test_KeyboardControler.vhd
View file

@ -1,88 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 08:21:55
-- Design Name:
-- Module Name: Test_KeyboardControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_KeyboardControler is
-- Port ( );
end Test_KeyboardControler;
architecture Behavioral of Test_KeyboardControler is
component KeyboardControler
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal Data_av : STD_LOGIC := '0';
signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
signal alert : STD_LOGIC := '0';
constant CLK_period : TIME := 10 ns;
begin
CLK_process : process
begin
CLK <= '1';
wait for CLK_period/2;
CLK <= '0';
wait for CLK_period/2;
end process;
instance : KeyboardControler
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_av => Data_av,
Data => Data,
alert => alert);
process
begin
PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
wait;
end process;
end Behavioral;

2
Processeur.srcs/sim_1/new/Test_Pipeline.vhd
View file

@ -78,7 +78,7 @@ begin
process process
begin begin
my_STD_IN <= "00000001" after 2600 ns, "00000010" after 5600 ns, "00000011" after 8600 ns, "00000100" after 11600 ns, "00000101" after 14600 ns, "00000110" after 17600 ns, "00000111" after 20600 ns, "00001000" after 23600 ns, "00001001" after 26600 ns, "00000000" after 29600 ns; my_STD_IN <= "00000001" after 300 us, "00000010" after 710 us, "00000011" after 1120 us, "00000100" after 1530 us, "00000101" after 1940 us, "00000110" after 2350 us, "00000111" after 2760 us, "00001000" after 3170 us, "00001001" after 3580 us, "00000000" after 3990 us;
wait; wait;
end process; end process;
end Behavioral; end Behavioral;

95
Processeur.srcs/sim_1/new/Test_SystemKeyboardScreen.vhd
View file

@ -1,95 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.07.2021 18:57:39
-- Design Name:
-- Module Name: Test_SystemKeyboardScreen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_SystemKeyboardScreen is
-- Port ( );
end Test_SystemKeyboardScreen;
architecture Behavioral of Test_SystemKeyboardScreen is
component SystemKeyboardScreen
Port ( CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal Hsync : STD_LOGIC := '0';
signal Vsync : STD_LOGIC := '0';
signal CLK_period : Time := 10 ns;
begin
instance : SystemKeyboardScreen
port map ( CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
vgaRed => vgaRed,
vgaGreen => vgaGreen,
vgaBlue => vgaBlue,
Hsync => Hsync,
Vsync => Vsync);
CLK_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
PS2Data <= '0' after 1020 ns, '0' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '1' after 1420 ns, '0' after 1520 ns, '0' after 1620 ns, '1' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
wait;
end process;
end Behavioral;

113
Processeur.srcs/sim_1/new/Test_VGAControler.vhd
View file

@ -1,113 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 15:55:57
-- Design Name:
-- Module Name: Test_VGAControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Test_VGAControler is
-- Port ( );
end Test_VGAControler;
architecture Behavioral of Test_VGAControler is
constant Display_CaracterWidht : Natural := 16;
constant Display_CaracterHeight : Natural := 16;
constant screen_width : natural := 1280;
constant screen_height : natural := 1024;
constant X_PulseWidth : Natural := 112;
constant X_FrontPorch : Natural := 48;
constant X_BackPorch : Natural := 248;
constant Y_PulseWidth : Natural := 3;
constant Y_FrontPorch : Natural := 1;
constant Y_BackPorch : Natural := 38;
subtype X_T is Natural range 0 to screen_width - 1;
subtype Y_T is Natural range 0 to screen_height - 1;
constant C_Blocks : Natural := screen_width/Display_CaracterWidht;
constant L_Blocks : Natural := screen_height/Display_CaracterHeight;
subtype L_T is Natural range 0 to L_Blocks - 1;
subtype C_T is Natural range 0 to C_Blocks - 1;
component VGAControler is
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component;
signal my_VGA_RED : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_VGA_BLUE : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_VGA_GREEN : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal my_VGA_HS : STD_LOGIC := '0';
signal my_VGA_VS : STD_LOGIC := '0';
signal my_X : X_T := 0;
signal my_Y : Y_T := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
constant CLK_period : time := 10 ns;
begin
instance : VGAControler
port map( VGA_RED => my_VGA_RED,
VGA_BLUE => my_VGA_BLUE,
VGA_GREEN => my_VGA_GREEN,
VGA_HS => my_VGA_HS,
VGA_VS => my_VGA_VS,
X => my_X,
Y => my_Y,
PIXEL_ON => my_PIXEL_ON,
CLK => my_CLK,
RST => my_RST);
CLK_process : process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
my_PIXEL_ON <= '1' after 50 ns, '0' after 100 ns, '1' after 150 ns, '0' after 200 ns;
wait;
end process;
end Behavioral;

2
Processeur.srcs/sources_1/new/ALU.vhd
View file

@ -67,7 +67,7 @@ begin
(others => '0'); (others => '0');
intern_N <= SUB (Nb_bits-1); intern_N <= SUB (Nb_bits);
intern_Z <= '1' when (SUB = ZERO_N1) else intern_Z <= '1' when (SUB = ZERO_N1) else
'0'; '0';

55
Processeur.srcs/sources_1/new/Compteur_X.vhd
View file

@ -1,55 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 05.07.2021 15:20:28
-- Module Name: Compteur_X - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
-- Description: Compteur la coordonnée X du VGA
--
-- Dependencies:
-- - None
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
entity Compteur_X is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out X_T;
Carry : out STD_LOGIC);
end Compteur_X;
architecture Behavioral of Compteur_X is
signal current : X_T := 0;
signal intern_Carry : STD_LOGIC := '0';
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
current <= 0;
else
current <= current + 1;
if (current = screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1) then
intern_Carry <= '1';
current <= 0;
else
intern_Carry <= '0';
end if;
end if;
end process;
Value <= current;
Carry <= intern_Carry;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 05.07.2021 15:20:28
-- Module Name: Compteur_Y - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
-- Description: Compteur la coordonnée Y du VGA
--
-- Dependencies:
-- - None
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
entity Compteur_Y is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Y_T);
end Compteur_Y;
architecture Behavioral of Compteur_Y is
signal current : Y_T := 0;
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
current <= 0;
else
current <= current + 1;
if (current = screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1) then
current <= 0;
end if;
end if;
end process;
Value <= current;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 28.06.2021 09:20:00
-- Module Name: Ecran - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
-- Description: Tableau des caractères à afficher à l'écran
-- - Ajoute les caractère a la suite les un des autres (comme un fichier avec un curseur)
-- - Prends des coordonnées (X,Y) et renvoi l'état du pixel associé
--
-- Dependencies:
-- - TableASCII
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.font.all;
use work.ScreenProperties.all;
entity Ecran is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC; -- Un caractère doit être ajouté au tableau
Data_IN : in STD_LOGIC_VECTOR (0 to 6); -- Caractère à ajouter
X : in X_T; -- Position X
Y : in Y_T; -- Position Y
OUT_ON : out STD_LOGIC); -- Valeur du pixel (X,Y)
end Ecran;
architecture Behavioral of Ecran is
component TableASCII is
Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
end component;
constant Flush : STD_LOGIC_VECTOR (0 to 6) := "0000000"; -- Code ASCII du flush
constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001010"; -- Code ASCII du retour chariot
constant Delete : STD_LOGIC_VECTOR (0 to 6) := "1111111"; -- Code ASCII du Delete
signal Ecran : STD_LOGIC_VECTOR (0 to Ecran_Taille - 1) := (others => '0'); -- Tableau des caractères de l'écran
signal L : STD_LOGIC_VECTOR (0 to 6) := "0000000"; -- Ligne du tableau dans laquelle il faut écrire (position Y du curseur)
signal L_inc : STD_LOGIC_VECTOR (0 to 6); -- L+1 mod Nb_Lignes
signal C : STD_LOGIC_VECTOR (0 to 6) := "0000000"; -- Colone du tableau dans laquelle il faut écrire (position X du curseur)
signal InitialL : STD_LOGIC_VECTOR (0 to 6) := "0000000"; -- Le tableau fonctionne comme un buffer circulaire, il faut donc garder en mémoire la première ligne
signal InitialL_inc : STD_LOGIC_VECTOR (0 to 6); -- InitialL+1 mod Nb_Lignes
signal Full : STD_LOGIC := '0'; -- Si le tableau est plein
signal L_Lecture : L_T := 0; -- Ligne pour la lecture dans le tableau
signal point_dereferencement : Natural := 0; -- Index dans le tableau ou est stocké le code ASCII correspondant à (X,Y)
signal point_dereferencement_ecriture : Natural := 0; -- Index dans le tableau ou la valeur doit être écrite
signal CurrentCodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000"; -- Le code ASCII actuellement lu
signal CurrentFont : STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1) := (others => '0'); -- La font correspondante a ce Code
signal position_X : X_T := 0; -- Signal pour décaler X de manière a introduire une marge
signal position_Y : Y_T := 0; -- Signal pour décaler Y de manière a introduire une marge
signal active : Boolean := false; -- Nous sommes (ou non) dans la zone active de l'écran
begin
instance_TableASCII : TableASCII
port map (CodeASCII => CurrentCodeASCII,
Font => CurrentFont);
process
begin
wait until CLK'event and CLK='1';
if (RST = '0' or (Data_Av = '1' and Data_IN = Flush)) then
-- Reset ou FLUSH
Ecran <= (others => '0');
L <= "0000000";
C <= "0000000";
InitialL <= "0000000";
Full <= '0';
elsif (Data_Av = '1') then
-- Data disponible
if (Data_IN = Delete) then
-- Un Delete, on efface un caractère sur la ligne (Nb : on ne peut effacer que la ligne courante)
if (C > 0) then
C <= C - 1;
Ecran(7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)) - 1) to 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C))) - 1) <= "0000000";
end if;
elsif (Data_In /= RetourChariot) then
-- Un caractère lamda, on l'écrit
Ecran(point_dereferencement_ecriture to point_dereferencement_ecriture + 6) <= Data_IN;
C <= C + 1;
end if;
if (Data_IN = RetourChariot or (C + 1 = C_Blocks and Data_IN /= Delete)) then
-- Si besoin on saute a la ligne suivant
C <= "0000000";
L <= L_inc;
if (L_inc = "0000000" or Full = '1') then
Full <= '1';
InitialL <= InitialL_inc;
Ecran(7 * C_Blocks * to_integer(unsigned(L_inc)) to 7 * C_Blocks * (to_integer(unsigned(L_inc)) + 1) - 1) <= Zero_Line;
end if;
end if;
end if;
end process;
-- Gestion des signaux d'écriture
L_inc <= "0000000" when L + 1 = L_Blocks else L + 1;
InitialL_inc <= "0000000" when InitialL + 1 = L_Blocks else InitialL + 1;
point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)));
-- Gestion des signaux de lecture
position_X <= X - margin when X >= 0 + margin and X < screen_width - margin else 0; -- Prise en compte des marges
position_Y <= Y - margin when Y >= 0 + margin and Y < screen_height - margin else 0; -- Prise en compte des marges
active <= X >= 0 + margin and X < screen_width - margin and Y >= 0 + margin and Y < screen_height - margin; -- Fenetre active ?
L_Lecture <= position_Y/Display_CaracterHeight + to_integer(unsigned(InitialL)) - L_Blocks when (position_Y/Display_CaracterHeight + to_integer(unsigned(InitialL))) >= L_Blocks else position_Y/Display_CaracterHeight + to_integer(unsigned(InitialL)); -- Calcul de la ligne de lecture
point_dereferencement <= (7 * (C_Blocks * L_Lecture + (position_X/Display_CaracterWidht))); -- Calcul du point de déréférencement
CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6); -- Recupération du code ASCII
OUT_ON <= CurrentFont(((position_Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (position_X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width)) when active else '0'; -- Calcul de l'état du pixel
end Behavioral;

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----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 18.04.2021 21:19:41
-- Module Name: Etage1_LectureInstruction - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
-- Description: Etage 1 du processeur
-- - Gestion des instructions, lecture en mémoire
-- - Gestion des aléas sur les registres
-- - Gestion des sauts et appels de fonction
--
-- Dependencies:
-- - MemoireInstruction
-- - MemoireAdressesRetour
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Etage1_LectureInstruction is
Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
Nb_bits : Natural; -- Taille d'un mot binaire
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Nb_registres : Natural; -- Nombre de registres du processeurs
Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale)
Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA)
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB)
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC)
Instructions_critiques_ecriture : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques en écriture (toujours sur l'opérande A) (si le bit i est a un, l'instruction i ecrit une valeur dans le registre n°opérandeA)
-- Exemple 1 : Soit MUL i j k avec pour numéro d'instruction 7 avec le comportement Ri <- Rj*Rk
-- Instructions_critiques_lecture_A(7) = '0' --> MUL ne lit pas dans le registre de l'opérande A
-- Instructions_critiques_lecture_B(7) = '1' --> MUL lit dans le registre de l'opérande B
-- Instructions_critiques_lecture_C(7) = '1' --> MUL lit dans le registre de l'opérande C
-- Instructions_critiques_ecriture(7) = '1' --> MUL ecrit dans le registre de l'opérande A
-- Exemple 2 : Soit AFC i val avec pour numéro d'instruction 5 avec le comportement Ri <- val
-- Instructions_critiques_lecture_A(5) = '0' --> AFC ne lit pas dans le registre de l'opérande A
-- Instructions_critiques_lecture_B(5) = '0' --> AFC ne lit pas dans le registre de l'opérande B (pour AFC, B est directement la valeur, pas un numero de registre, il n'y a donc pas de lecture)
-- Instructions_critiques_lecture_C(5) = '0' --> AFC ne lit pas dans le registre de l'opérande C
-- Instructions_critiques_ecriture(5) = '1' --> AFC ecrit dans le registre de l'opérande A
Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP
Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ
Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI
Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC
Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET
Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP
Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset
Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ)
STD_IN_Request : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
end Etage1_LectureInstruction;
architecture Behavioral of Etage1_LectureInstruction is
component MemoireInstructions is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
-- Signaux pour récuperer l'instruction de la mémoire
signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
-- Tableau pour gérer les aléas des registres (lecture en étage 2 avant écriture en étage 5)
subtype Registre is integer range -1 to Nb_registres - 1;
type Tab_registres is array (1 to 3) of Registre;
signal Tableau : Tab_registres := (others => - 1);
-- Signaux de gestion pour la mémoire des adresses de retour
signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal E : STD_LOGIC;
signal F : STD_LOGIC;
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
-- constantes pour injecter des bulles dans le pipeline
constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
constant Argument_nul : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
-- condition pour detecter si une bulle doit être injectée
signal bulles : boolean := false;
-- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k
signal compteur : integer := 0;
-- Compteur de protection des collisions entre les prints
signal Compteur_PRI : integer range 0 to Nb_bits/4 + 1 := 0;
-- Signal d'arret (STOP 0)
signal locked : boolean := false;
begin
instance : MemoireInstructions
generic map (Nb_bits => Instruction_size_in_memory,
Addr_size => Addr_size_mem_instruction,
Mem_size => Mem_instruction_size)
port map (Addr => Pointeur_Instruction,
D_OUT => Instruction_courante);
instance_MemoireAdressesRetour : MemoireAdressesRetour
generic map (Nb_bits => Addr_size_mem_instruction,
Addr_size => Adresse_size_mem_adresse_retour,
Mem_size => Mem_adresse_retour_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => Pointeur_instruction_next,
RST => RST,
CLK => CLK,
D_OUT => Adresse_Retour,
E => E,
F => F
);
process
begin
-- Synchronisation
wait until CLK'event and CLK = '1';
if (RST = '0') then
-- Reset de l'étage
Tableau <= (others => -1);
Pointeur_Instruction <= (others => '0');
compteur <= 0;
Compteur_PRI <= 0;
locked <= false;
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
elsif (STD_IN_Request = '0') then
-- Avancement des instructions en écritures dans le pipeline
Tableau(3) <= Tableau(2);
Tableau(2) <= Tableau(1);
Tableau(1) <= -1;
if (Compteur_PRI > 0) then
Compteur_PRI <= Compteur_PRI - 1;
end if;
if (not bulles) then
-- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
-- CAS PARTICULIER : CALL ou JMP, on transmet et on saute
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
-- CAS PARTICULIER : RET, on transmet et on revient
Pointeur_Instruction <= Adresse_Retour;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
-- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement
compteur <= compteur + 1;
if (compteur = 2) then
if (Z = '1') then
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
else
Pointeur_Instruction <= Pointeur_Instruction + 1;
end if;
compteur <= 0;
end if;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_STOP) then
-- CAS PARTICULIER : STOP, si on est bloqué, on ne fait rien, programme arrété
-- sinon, on regarde si l'on doit se bloquer
-- sinon, on incremente le compteur et on attends
if (not locked) then
if (Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits) = Argument_nul) then
locked <= true;
end if;
compteur <= compteur + 1;
if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) * 1000) then
Pointeur_Instruction <= Pointeur_Instruction + 1;
compteur <= 0;
end if;
end if;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) then
-- CAS PARTICULIER : PRI, on transmet l'instruction et fixe le compteur pour proteger des collisions
Compteur_PRI <= Nb_bits/4 + 1;
Pointeur_Instruction <= Pointeur_Instruction + 1;
else
-- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau
if (Instructions_critiques_ecriture(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1') then
Tableau(1) <= to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)));
end if;
Pointeur_Instruction <= Pointeur_Instruction + 1;
end if;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
else
-- Si besoin de bulle, on l'injecte
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
end if;
end if;
end process;
-- Condition horrible -> Instruction critique en lecture sur A qui lit dans A=i et Ri dans tableau ou instruction critique en lecture sur B qui lit dans B=j et Rj dans tableau ou instruction critique en lecture sur C qui lit dans C=k et Rk dans tableau
bulles <=
(
(
Instructions_critiques_lecture_A(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1' -- Intruction critique sur A
)
and
(
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(1)) -- A est
or
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(2)) -- dans le
or
(to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) = Tableau(3)) -- tableau
)
)
or
(
(
Instructions_critiques_lecture_B(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits))) = Tableau(3))
)
)
or
(
(
Instructions_critiques_lecture_C(to_integer(unsigned(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits)))) = '1'
)
and
(
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(1))
or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(2))
or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
)
)
or
(
(
(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI)
or
(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRIC)
)
and
(
not (Compteur_PRI = 0)
)
);
-- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET and STD_IN_Request = '0' else
'0';
W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL and STD_IN_Request = '0' else
'0';
Pointeur_instruction_next <= Pointeur_instruction + 1;
end Behavioral;

37
Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd
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@ -7,13 +7,14 @@
-- Project Name: Processeur sécurisé -- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7 -- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4 -- Tool Versions: Vivado 2016.4
-- Description: Etage 1 du processeur (version non sécurisée) -- Description: Etage 1 du processeur
-- - Gestion des instructions, lecture en mémoire -- - Gestion des instructions, lecture en mémoire
-- - Gestion des aléas sur les registres -- - Gestion des aléas sur les registres
-- - Gestion des sauts et appels de fonction -- - Gestion des sauts et appels de fonction
-- --
-- Dependencies: -- Dependencies:
-- - MemoireInstruction -- - MemoireInstruction
-- - MemoireAdressesRetour
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
@ -49,15 +50,12 @@ entity Etage1_LectureInstruction_NS is
Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP Code_Instruction_JMP : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMP
Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ Code_Instruction_JMZ : STD_LOGIC_VECTOR; -- Numéro de l'instruction JMZ
Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI
Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC
Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET Code_Instruction_RET : STD_LOGIC_VECTOR; -- Numéro de l'instruction RET
Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP Code_Instruction_STOP : STD_LOGIC_VECTOR); -- Numéro de l'instruction STOP
Port ( CLK : in STD_LOGIC; -- Clock Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset RST : in STD_LOGIC; -- Reset
Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ) Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ)
STD_IN_Request : in STD_LOGIC;
Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4 Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
@ -96,9 +94,6 @@ architecture Behavioral of Etage1_LectureInstruction_NS is
-- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k -- Compteur pour attendre lors d'un JMZ que l'instruction d'avant soit a l'ALU, ou lors d'un STOP k
signal compteur : integer := 0; signal compteur : integer := 0;
-- Compteur de protection des collisions entre les prints
signal Compteur_PRI : integer range 0 to Nb_bits/4 + 1 := 0;
-- Signal d'arret (STOP 0) -- Signal d'arret (STOP 0)
signal locked : boolean := false; signal locked : boolean := false;
@ -120,20 +115,16 @@ begin
Tableau <= (others => -1); Tableau <= (others => -1);
Pointeur_Instruction <= (others => '0'); Pointeur_Instruction <= (others => '0');
compteur <= 0; compteur <= 0;
Compteur_PRI <= 0;
locked <= false; locked <= false;
C <= Argument_nul; C <= Argument_nul;
B <= Argument_nul; B <= Argument_nul;
A <= Argument_nul; A <= Argument_nul;
Instruction <= Instruction_nulle; Instruction <= Instruction_nulle;
elsif (STD_IN_Request = '0') then else
-- Avancement des instructions en écritures dans le pipeline -- Avancement des instructions en écritures dans le pipeline
Tableau(3) <= Tableau(2); Tableau(3) <= Tableau(2);
Tableau(2) <= Tableau(1); Tableau(2) <= Tableau(1);
Tableau(1) <= -1; Tableau(1) <= -1;
if (Compteur_PRI > 0) then
Compteur_PRI <= Compteur_PRI - 1;
end if;
if (not bulles) then if (not bulles) then
-- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if) -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
@ -193,14 +184,6 @@ begin
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI) then
-- CAS PARTICULIER : PRI, on transmet l'instruction et fixe le compteur pour proteger des collisions
Compteur_PRI <= Nb_bits/4 + 1;
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Pointeur_Instruction + 1;
else else
-- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau -- CAS GENERAL : On transmet l'instruction et les opérandes, si elle est critique en ecriture, on enregistre le registre associé dans le tableau
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
@ -223,7 +206,7 @@ begin
end process; end process;
-- Condition horrible -> Instruction critique en lecture sur A qui lit dans A=i et Ri dans tableau ou instruction critique en lecture sur B qui lit dans B=j et Rj dans tableau ou instruction critique en lecture sur C qui lit dans C=k et Rk dans tableau ou PRI en cours et un PRI ou un PRIC arrive -- Condition horrible -> Instruction critique en lecture sur A qui lit dans A=i et Ri dans tableau ou instruction critique en lecture sur B qui lit dans B=j et Rj dans tableau ou instruction critique en lecture sur C qui lit dans C=k et Rk dans tableau
bulles <= bulles <=
( (
( (
@ -265,18 +248,6 @@ begin
or or
(to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3)) (to_integer(unsigned(Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits))) = Tableau(3))
) )
)
or
(
(
(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRI)
or
(Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_PRIC)
)
and
(
not (Compteur_PRI = 0)
)
); );

38
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd
View file

@ -29,17 +29,12 @@ entity Etage2_5_Registres is
Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd) Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd)
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd) Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd)
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd) Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd)
Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI
Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
Port ( CLK : in STD_LOGIC; -- Clock Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset RST : in STD_LOGIC; -- Reset
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
STD_IN_Av : in STD_LOGIC; -- Donnée depuis l'exterieur du processeur disponible
STD_IN_Request : out STD_LOGIC; -- Donnée depuis l'exterieur du processeur demandée
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
STD_OUT_Av : out STD_LOGIC; -- Donnée vers l'exterieur du processeur disponible
STD_OUT_Int : out STD_LOGIC; -- Type de la donnée (int ou char)
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2 IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2 IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2 IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2
@ -100,9 +95,7 @@ architecture Behavioral of Etage2_5_Registres is
signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_A : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal intern_OUT_2_C : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_STD_OUT : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Request_Stopped : BOOLEAN := false;
begin begin
instance_LC : LC instance_LC : LC
@ -155,22 +148,23 @@ begin
OUT_2_Instruction <= (others => '0') when RST = '0' else OUT_2_Instruction <= (others => '0') when RST = '0' else
IN_2_Instruction; IN_2_Instruction;
STD_OUT <= (others => '0') when RST = '0' else -- Gestion de STD_OU (peut être améliorée)
intern_OUT_2_A;
STD_OUT_Av <= '0' when RST = '0' else
'1' when IN_2_Instruction = Code_Instruction_PRI or IN_2_Instruction = Code_Instruction_PRIC else
'0';
STD_OUT_Int <= '0' when RST = '0' else
'1' when IN_2_Instruction = Code_Instruction_PRI else
'0';
process process
begin begin
wait until CLK'event and CLK='1'; -- Synchronisation sur la clock
Request_Stopped <= (STD_IN_Av = '1') and (RST = '1'); wait until CLK'event and CLK = '1';
if (RST = '0') then
intern_STD_OUT <= (others => '0');
else
if (IN_2_Instruction = Code_Instruction_PRI) then
intern_STD_OUT <= intern_OUT_2_A;
end if;
end if;
end process; end process;
STD_OUT <= intern_STD_OUT when RST = '1' else
(others => '0');
STD_IN_Request <= '1' when not(Request_Stopped) and IN_5_Instruction = Code_Instruction_GET and not(RST='0') else '0';
-- Un multiplexeur pourrait être utilisé ici, mais cela n'a pas été jugé pertinent -- Un multiplexeur pourrait être utilisé ici, mais cela n'a pas été jugé pertinent
Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else

208
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
View file

@ -1,208 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 18.04.2021 21:19:41
-- Module Name: Etage4_Memoire - Structural
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Etage 4 du processeur
-- - Gestion de la mémoire
-- - Gestion de la sauvegarde du contexte lors des appels de fonction
--
-- Dependencies:
-- - MemoireDonnees
-- - MemoireAdressesRetour
-- - LC
-- - MUX
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Etage4_Memoire is
Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
end Etage4_Memoire;
architecture Structural of Etage4_Memoire is
component MemoireDonnees is
Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire
Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire
Mem_size : Natural); -- Nombre de mot stockables
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
CALL : in STD_LOGIC; -- '1' -> CALL en cours
IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
RET : in STD_LOGIC; -- '1' -> RET en cours
OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
RST : in STD_LOGIC; -- Reset
CLK : in STD_LOGIC; -- Clock
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
component LC is
Generic (Instruction_Vector_Size : Natural;
Command_size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
Commande : out STD_LOGIC_VECTOR (Command_size - 1 downto 0));
end component;
component MUX is
Generic (Nb_bits : Natural;
Instruction_Vector_Size : Natural;
Bits_Controle : STD_LOGIC_VECTOR);
Port ( Instruction : in STD_LOGIC_VECTOR (Instruction_Vector_Size - 1 downto 0);
IN1 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN2 : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse)
signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd)
signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees
signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B
signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse avec EBP ajouté (IN_Addr_MemoireDonnees + BP)
signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0"; -- Sortie du Link Controler, signal de commande de la mémoire
signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Sortie de la mémoire (a multiplexer)
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne
-- Signaux de la memoire de contexte
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
signal E : STD_LOGIC;
signal F : STD_LOGIC;
-- Signaux inutiles
signal OUT_EBP : STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
signal OUT_AddrRet : STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
begin
instance_LC : LC -- Link controleur sur la mémoire de donnees
generic map (Instruction_Vector_Size => Instruction_bus_size,
Command_size => 1,
Bits_Controle => Bits_Controle_LC)
port map ( Instruction => IN_Instruction,
Commande => Commande_MemoireDonnees);
instance_MUX_IN : MUX -- Multiplexeur selectionnant A ou B pour adresse
generic map (Nb_bits => Adresse_mem_size,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_IN)
port map ( Instruction => IN_Instruction,
IN1 => IN_A (Adresse_mem_size - 1 downto 0),
IN2 => IN_B (Adresse_mem_size - 1 downto 0),
OUTPUT => IN_Addr_MemoireDonnees);
instance_MUX_IN_EBP : MUX -- Multiplexeur selectionnant l'adresse plus EBP ou l'adresse de base
generic map (Nb_bits => Adresse_mem_size,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_IN_EBP)
port map ( Instruction => IN_Instruction,
IN1 => IN_Addr_MemoireDonnees,
IN2 => Addr_MemoireDonnees_EBP,
OUTPUT => Addr_MemoireDonnees);
instance_MUX_OUT : MUX -- Multiplexeur selectionnant la sortie de l'étage (sur B)
generic map (Nb_bits => Nb_bits,
Instruction_Vector_Size => Instruction_bus_size,
Bits_Controle => Bits_Controle_MUX_OUT)
port map ( Instruction => IN_Instruction,
IN1 => Sortie_MemoireDonnees,
IN2 => IN_B,
OUTPUT => intern_OUT_B);
instance_MemoireDonnees : MemoireDonnees
generic map (Nb_bits => Nb_bits,
Addr_size => Adresse_mem_size,
Mem_size => Mem_size)
port map ( Addr => Addr_MemoireDonnees,
RW => Commande_MemoireDonnees(0),
D_IN => IN_B,
CALL => '0',
IN_EBP => (others => '0'),
IN_AddrRet => (others => '0'),
RET => '0',
OUT_EBP => OUT_EBP,
OUT_AddrRet => OUT_AddrRet,
RST => RST,
CLK => CLK,
D_OUT => Sortie_MemoireDonnees);
instance_MemoireEBP : MemoireAdressesRetour
generic map (Nb_bits => Adresse_mem_size,
Addr_size => Adresse_size_mem_EBP,
Mem_size => Mem_EBP_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => New_EBP,
RST => RST,
CLK => CLK,
D_OUT => EBP,
E => E,
F => F
);
OUT_A <= (others => '0') when RST = '0' else
IN_A;
OUT_B <= (others => '0') when RST = '0' else
intern_OUT_B;
OUT_Instruction <= (others => '0') when RST = '0' else
IN_Instruction;
-- Controle de la mémoire de contexte (ici aussi un LC aurait été disproportionné)
R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
'0';
W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
'0';
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
end Structural;

10
Processeur.srcs/sources_1/new/Etage4_Memoire_NS.vhd
View file

@ -8,12 +8,13 @@
-- Target Devices: Basys 3 ARTIX7 -- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4 -- Tool Versions: Vivado 2016.4
-- --
-- Description: Etage 4 du processeur (non sécurisé) -- Description: Etage 4 du processeur
-- - Gestion de la mémoire -- - Gestion de la mémoire
-- - Gestion de la sauvegarde du contexte et de l'adresse de retour lors des appels de fonction -- - Gestion de la sauvegarde du contexte lors des appels de fonction
-- --
-- Dependencies: -- Dependencies:
-- - MemoireDonnees -- - MemoireDonnees
-- - MemoireAdressesRetour
-- - LC -- - LC
-- - MUX -- - MUX
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
@ -168,7 +169,6 @@ begin
CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
'0'; '0';
-- Gestion d'EBP
process process
begin begin
wait until CLK'event and CLK = '1'; wait until CLK'event and CLK = '1';
@ -181,9 +181,7 @@ begin
end if; end if;
end process; end process;
-- Calcul de la nouvelle valeur d'EBP New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
-- Valeur de EBP à stocker (bourré avec des '0')
IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP; IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP; Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;

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@ -1,93 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 01.07.2021 09:09:30
-- Module Name: Keyboard - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Composant clavier, intègre le controleur du clavier pour en faire un composant bufferisé
--
-- Dependencies:
-- - KeyboardControler
-- - KeyboardToASCII
--
-- Comments : Transforme aussi la keycode en code ASCII
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Keyboard is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 6);
alert : out STD_LOGIC);
end Keyboard;
architecture Behavioral of Keyboard is
component KeyboardControler
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end component;
component KeyboardToASCII
Port ( KeyCode : in STD_LOGIC_VECTOR (0 to 7);
CodeASCII : out STD_LOGIC_VECTOR (0 to 6));
end component;
signal buffer_Data : STD_LOGIC_VECTOR (0 to 7);
signal kbCtrl_Data_av : STD_LOGIC;
signal intern_Data_av : STD_LOGIC := '0';
signal intern_Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
begin
instance_KeyboardControler : KeyboardControler
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_av => kbCtrl_Data_av,
Data => buffer_Data,
alert => alert);
instance_KeyboardToASCII : KeyboardToASCII
port map ( KeyCode => buffer_Data,
CodeASCII => intern_Data);
process
begin
wait until CLK'event and CLK = '1';
if (intern_Data_av = '0') then
if (kbCtrl_Data_av = '1') then
Data <= intern_Data;
intern_Data_av <= '1';
end if;
elsif (Data_read = '1') then
intern_Data_av <= '0';
end if;
end process;
Data_av <= intern_Data_av;
end Behavioral;

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@ -1,138 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 01.07.2021 09:09:30
-- Module Name: KeyboardControler - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: ALU
--
-- Dependencies: Fait le lien avec le BUS PS2 du clavier, récupère la touche tapée et la renvoi
--
-- Comments : Il n'y a pas de bufferisation
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity KeyboardControler is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end KeyboardControler;
architecture Behavioral of KeyboardControler is
-- Compteur pour récupérer la trame PS2
subtype compteur_T is Natural range 0 to 10;
signal compteur : compteur_T := 0;
-- Trame en cours de lecture
signal current_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
-- Denière trame lue
signal previous_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
-- Signaux pour controler le bit de parité de la trame
signal parity : STD_LOGIC := '0';
signal intern_alert : STD_LOGIC := '0';
-- Signaux pour signaler qu'une touche a été préssée
signal intern_Data_av : STD_LOGIC := '0';
signal dejaSignale : boolean := false;
begin
-- process de récupération de la trame, synchronisé sur la CLK du bus PS2
-- A chaque front montant on lit ce qu'il y a a lire et on avance le compteur
process
begin
wait until PS2Clk'event and PS2Clk = '1';
case compteur is
when 0 =>
-- Bit de start : on réinitialise tout
parity <= '1';
intern_alert <= '0';
intern_Data_av <= '0';
when 1 =>
-- Lecture et MAJ de la parité
current_data(7) <= PS2Data;
parity <= parity XOR PS2Data;
when 2 =>
-- Lecture et MAJ de la parité
current_data(6) <= PS2Data;
parity <= parity XOR PS2Data;
when 3 =>
-- Lecture et MAJ de la parité
current_data(5) <= PS2Data;
parity <= parity XOR PS2Data;
when 4 =>
-- Lecture et MAJ de la parité
current_data(4) <= PS2Data;
parity <= parity XOR PS2Data;
when 5 =>
-- Lecture et MAJ de la parité
current_data(3) <= PS2Data;
parity <= parity XOR PS2Data;
when 6 =>
-- Lecture et MAJ de la parité
current_data(2) <= PS2Data;
parity <= parity XOR PS2Data;
when 7 =>
-- Lecture et MAJ de la parité
current_data(1) <= PS2Data;
parity <= parity XOR PS2Data;
when 8 =>
-- Lecture et MAJ de la parité
current_data(0) <= PS2Data;
parity <= parity XOR PS2Data;
when 9 =>
-- Check de la parité
if (parity = PS2Data) then
intern_alert <= '0';
else
intern_alert <= '1';
end if;
when 10 =>
-- Envoi de la touche
if (intern_alert = '0') then
previous_data <= current_data;
-- Elimination des touches non classiques
if (not (previous_data = "11110000" or current_data = "11110000" or previous_data = "11100000")) then
Data <= current_data;
intern_Data_av <= '1';
end if;
end if;
end case;
compteur <= (compteur + 1) mod 11;
end process;
-- Gestion de l'avertissement de touche
process
begin
wait until CLK'event and CLK = '1';
if (intern_Data_av = '1' and not dejaSignale) then
Data_av <= '1';
dejaSignale <= true;
else
Data_av <= '0';
end if;
if (intern_Data_av = '0') then
dejaSignale <= false;
end if;
end process;
alert <= intern_alert;
end Behavioral;

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@ -1,86 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 13.07.2021 09:30:08
-- Module Name: KeyboardDriver - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Driver pour interfacer le clavier avec les besoins du processeur
--
-- Dependencies: None
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity KeyboardDriver is
Generic (Nb_Bits : Natural);
Port (CLK : in STD_LOGIC;
Data_read : out STD_LOGIC; -- ******************************
Data_av : in STD_LOGIC; -- ***** Signaux du clavier *****
Data : in STD_LOGIC_VECTOR (0 to 6); -- ******************************
STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); -- ******************************
STD_IN_Av : out STD_LOGIC; -- *** Signaux du processeur ***
STD_IN_Request : in STD_LOGIC; -- ******************************
STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);-- ******************************
STD_OUT_Av : out STD_LOGIC); -- **** Signaux d'affichage ****
end KeyboardDriver;
architecture Behavioral of KeyboardDriver is
signal intern_value : Natural := 0;
signal work_in_progress : BOOLEAN := false;
signal Zeros : STD_LOGIC_Vector (Nb_bits - 1 downto 7) := (others => '0');
begin
process
begin
wait until CLK'event and CLK = '1';
STD_IN_Av <= '0';
STD_OUT_Av <= '0';
if not(work_in_progress) then
intern_value <= 0;
end if;
if STD_IN_Request = '1' then
-- Si on nous demande une valeur
work_in_progress <= true;
if Data_av = '1' then
-- Si une touche a été appuyée
if (Data = "1111111") then
-- Si c'est un Delete, on divide la valeur actuelle par 10
intern_value <= intern_value / 10;
STD_OUT <= Zeros & Data;
STD_OUT_Av <= '1';
elsif (Data = "0001010") then
-- Si c'est un Enter, on envoi la velaue au processeur
STD_IN <= std_logic_vector(to_unsigned(intern_value, Nb_bits));
STD_IN_Av <= '1';
work_in_progress <= false;
STD_OUT <= Zeros & Data;
STD_OUT_Av <= '1';
elsif (Data >= "0110000" and Data <= "0111001") then
-- Si c'est un nombre, on décale la valeur d'un chiffre a gauche puis un insere la touche saisie
intern_value <= intern_value * 10 + to_integer(unsigned(Data(3 to 6)));
STD_OUT <= Zeros & Data;
STD_OUT_Av <= '1';
end if;
-- Toute autre touche est ignorée
end if;
end if;
end process;
Data_read <= '0' when STD_IN_Request = '0' else Data_av;
end Behavioral;

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@ -1,72 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 02.07.2021 10:43:18
-- Module Name: KeyboardToASCII - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Associe le code ASCII au keycode de la touche
--
-- Dependencies: None
--
-- Comments : Assynchrone
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity KeyboardToASCII is
Port ( KeyCode : in STD_LOGIC_VECTOR (0 to 7);
CodeASCII : out STD_LOGIC_VECTOR (0 to 6));
end KeyboardToASCII;
architecture Behavioral of KeyboardToASCII is
begin
CodeASCII <= "0000000" when (KeyCode = x"05") else -- F1 -> flush
"0001010" when (KeyCode = x"5a") else -- Enter
"1111111" when (KeyCode = x"66") else -- Del
"1000001" when (KeyCode = x"15") else -- A
"1000010" when (KeyCode = x"32") else -- B
"1000011" when (KeyCode = x"21") else -- C
"1000100" when (KeyCode = x"23") else -- D
"1000101" when (KeyCode = x"24") else -- E
"1000110" when (KeyCode = x"2b") else -- F
"1000111" when (KeyCode = x"34") else -- G
"1001000" when (KeyCode = x"33") else -- H
"1001001" when (KeyCode = x"43") else -- I
"1001010" when (KeyCode = x"3b") else -- J
"1001011" when (KeyCode = x"42") else -- K
"1001100" when (KeyCode = x"4b") else -- L
"1001101" when (KeyCode = x"4c") else -- M
"1001110" when (KeyCode = x"31") else -- N
"1001111" when (KeyCode = x"44") else -- O
"1010000" when (KeyCode = x"4d") else -- P
"1010001" when (KeyCode = x"1c") else -- Q
"1010010" when (KeyCode = x"2d") else -- R
"1010011" when (KeyCode = x"1b") else -- S
"1010100" when (KeyCode = x"2c") else -- T
"1010101" when (KeyCode = x"3c") else -- U
"1010110" when (KeyCode = x"2a") else -- V
"1010111" when (KeyCode = x"1a") else -- W
"1011000" when (KeyCode = x"22") else -- X
"1011001" when (KeyCode = x"35") else -- Y
"1011010" when (KeyCode = x"1d") else -- Z
"0110000" when (KeyCode = x"70") else -- 0
"0110001" when (KeyCode = x"69") else -- 1
"0110010" when (KeyCode = x"72") else -- 2
"0110011" when (KeyCode = x"7a") else -- 3
"0110100" when (KeyCode = x"6b") else -- 4
"0110101" when (KeyCode = x"73") else -- 5
"0110110" when (KeyCode = x"74") else -- 6
"0110111" when (KeyCode = x"6c") else -- 7
"0111000" when (KeyCode = x"75") else -- 8
"0111001" when (KeyCode = x"7d") else -- 9
"0000001"; -- Rien
end Behavioral;

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@ -23,12 +23,12 @@ entity MemoireDonnees is
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write) RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0) D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
CALL : in STD_LOGIC; -- '1' -> CALL en cours (INUTILE POUR LA VERSION SECURISEE) CALL : in STD_LOGIC; -- '1' -> CALL en cours
IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL (INUTILE POUR LA VERSION SECURISEE) IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL (INUTILE POUR LA VERSION SECURISEE) IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
RET : in STD_LOGIC; -- '1' -> RET en cours (INUTILE POUR LA VERSION SECURISEE) RET : in STD_LOGIC; -- '1' -> RET en cours
OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET (INUTILE POUR LA VERSION SECURISEE) OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET (INUTILE POUR LA VERSION SECURISEE) OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
RST : in STD_LOGIC; -- Reset RST : in STD_LOGIC; -- Reset
CLK : in STD_LOGIC; -- Clock CLK : in STD_LOGIC; -- Clock
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire

5
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97
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@ -1,97 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 13.07.2021 09:30:08
-- Module Name: PeripheriqueClavier - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Assemble les composants du clavier pour faire un composant périphérique que l'on peut connecter au processeur
-- - Le clavier (controleur intégré)
-- - Le driver
--
-- Dependencies:
-- - Keyboard
-- - KeyboardDriver
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PeripheriqueClavier is
Generic (Nb_Bits : Natural);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_IN_Av : out STD_LOGIC;
STD_IN_Request : in STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC);
end PeripheriqueClavier;
architecture Behavioral of PeripheriqueClavier is
component KeyboardDriver
Generic (Nb_Bits : Natural);
Port (CLK : in STD_LOGIC;
Data_read : out STD_LOGIC;
Data_av : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (0 to 6);
STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_IN_Av : out STD_LOGIC;
STD_IN_Request : in STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC);
end component;
component Keyboard
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 6);
alert : out STD_LOGIC);
end component;
signal Data_read : STD_LOGIC := '0';
signal Data_av : STD_LOGIC := '0';
signal Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
signal nothing : STD_LOGIC := '0';
begin
instance_Keyboard : Keyboard
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_read => Data_read,
Data_av => Data_av,
Data => Data,
alert => nothing);
instance_KeyboardDriver : KeyboardDriver
generic map (Nb_Bits => Nb_Bits)
port map (CLK => CLK,
Data_read => Data_read,
Data_av => Data_av,
Data => Data,
STD_IN => STD_IN,
STD_IN_Av => STD_IN_Av,
STD_IN_Request => STD_IN_Request,
STD_OUT => STD_OUT,
STD_OUT_Av => STD_OUT_Av);
end Behavioral;

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@ -1,145 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 09.07.2021 15:25:56
-- Module Name: PeripheriqueEcran - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Assemble les composants de l'écran pour faire un composant périphérique que l'on peut connecter au processeur
-- - Le controleur
-- - L'écran
-- - Le driver
--
-- Dependencies:
-- - VGAControler
-- - Ecran
-- - ScreenDriver
-- - clk_wiz_0
--
-- Comments : la clock doit être accélérée pour atteindre 108Mhz pour le VGA
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
entity PeripheriqueEcran is
Generic ( Nb_Bits : Natural);
Port ( CLK : in STD_LOGIC;
CLK_VGA : in STD_LOGIC;
RST : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_OUT_Av : in STD_LOGIC;
STD_OUT_Int : in STD_LOGIC);
end PeripheriqueEcran;
architecture Behavioral of PeripheriqueEcran is
component VGAControler is
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component;
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end component;
component Ecran is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in X_T;
Y : in Y_T;
OUT_ON : out STD_LOGIC);
end component;
component ScreenDriver
Generic ( Nb_bits : Natural
);
Port ( CLK : in STD_LOGIC;
Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
ValueAv : in STD_LOGIC;
IsInt : in STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (0 to 6);
OutDataAv : out STD_LOGIC);
end component;
signal my_X : X_T := 0;
signal my_Y : Y_T := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
signal OutDataAv : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
begin
instanceVGA : VGAControler
port map( VGA_RED => vgaRed,
VGA_BLUE => vgaBlue,
VGA_GREEN => vgaGreen,
VGA_HS => Hsync,
VGA_VS => Vsync,
X => my_X,
Y => my_Y,
PIXEL_ON => my_PIXEL_ON,
CLK => my_CLK,
RST => RST);
clk_wiz_0_inst : clk_wiz_0
port map (
clk_in1 => CLK_VGA,
clk_out1 => my_CLK
);
instance_Ecran : Ecran
port map ( CLK => CLK,
RST => RST,
Data_Av => OutDataAv,
Data_IN => OutData,
X => my_X,
Y => my_Y,
OUT_ON => my_PIXEL_ON);
instance_ScreenDriver : ScreenDriver
Generic map ( Nb_bits => Nb_Bits
)
Port map ( CLK => CLK,
Value => STD_OUT,
ValueAv => STD_OUT_Av,
IsInt => STD_OUT_Int,
OutData => OutData,
OutDataAv => OutDataAv);
end Behavioral;

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----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 19.04.2021 16:57:41
-- Module Name: Pipeline - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
-- Description: Version sécurisée du pipeline, connecte les étages et fait avancer les signaux sur le pipeline
--
-- Dependencies:
-- - Etage1_LectureInstruction
-- - Etage2_5_Registres
-- - Etage3_Calcul
-- - Etage4_Memoire
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Pipeline is
Generic (Nb_bits : Natural := 8; -- Taille d'un mot binaire
Instruction_En_Memoire_Size : Natural := 29; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
Addr_Memoire_Instruction_Size : Natural := 3; -- Nombre de bits pour adresser la mémoire d'instruction
Memoire_Instruction_Size : Natural := 8; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
Instruction_Bus_Size : Natural := 5; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Nb_Instructions : Natural := 32; -- Nombre d'instructions dans le processeur
Nb_Registres : Natural := 16; -- Nombre de registres du processeurs
Addr_registres_size : Natural := 4; -- Nombre de bits pour adresser les registres
Memoire_Size : Natural := 32; -- Taille de la mémoire de données
Adresse_mem_size : Natural := 5; -- Nombre de bits pour adresser la mémoire
Memoire_Adresses_Retour_Size : Natural := 16; -- Profondeur d'appel maximale
Adresse_Memoire_Adresses_Retour_Size : Natural := 4); -- log2(Profondeur d'appel maximale)
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_IN_Av : in STD_LOGIC;
STD_IN_Request : out STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC;
STD_OUT_Int : out STD_LOGIC);
end Pipeline;
architecture Behavioral of Pipeline is
component Etage1_LectureInstruction is
Generic (Instruction_size_in_memory : Natural;
Addr_size_mem_instruction : Natural;
Mem_instruction_size : Natural;
Nb_bits : Natural;
Instruction_bus_size : Natural;
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_PRIC : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR;
Code_Instruction_STOP : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
STD_IN_Request : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
component Etage2_5_Registres is
Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Nb_registres : Natural; -- Nombre de registres du processeurs
Addr_registres_size : Natural; -- Nombre de bits pour adresser les registres
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Bits_Controle_LC_5 : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler de l'étage 5 (cf LC.vhd)
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur A (cf MUX.vhd)
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexeur de l'étage 2 sur B (cf MUX.vhd)
Code_Instruction_PRI : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRI
Code_Instruction_PRIC : STD_LOGIC_VECTOR; -- Numéro de l'instruction PRIC
Code_Instruction_GET : STD_LOGIC_VECTOR); -- Numéro de l'instruction GET
Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur
STD_IN_Av : in STD_LOGIC;
STD_IN_Request : out STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
STD_OUT_Av : out STD_LOGIC;
STD_OUT_Int : out STD_LOGIC;
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 2
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 2
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande C de l'étage 2
IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction de l'étage 2
OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A de l'étage 2
OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B de l'étage 2
OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C de l'étage 2
OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction de l'étage 2
IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A de l'étage 5
IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B de l'étage 5
IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Entrée de l'instruction de l'étage 5
end component;
component Etage3_Calcul is
Generic ( Nb_bits : Natural;
Instruction_bus_size : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX : STD_LOGIC_VECTOR);
Port ( RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end component;
component Etage4_Memoire is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Adresse_mem_size : Natural;
Instruction_bus_size : Natural;
Mem_EBP_size : Natural;
Adresse_size_mem_EBP : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
end component;
-- Signaux reliant les étages
signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
-- Sorties de l'ALU
signal N : STD_LOGIC := '0';
signal Z : STD_LOGIC := '0';
signal O : STD_LOGIC := '0';
signal C : STD_LOGIC := '0';
signal intern_STD_IN_Request : STD_LOGIC := '0';
-- Constantes de contrôle des MUX et LC
constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111";
constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001";
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111";
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111";
constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111011001111111111";
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000";
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
-- Code de certaines instructions
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110";
-- Constantes de contrôle des bulles
constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000";
constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110";
constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
begin
instance_Etage1 : Etage1_LectureInstruction
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
Mem_instruction_size => Memoire_Instruction_Size,
Nb_bits => Nb_bits,
Instruction_bus_size => Instruction_Bus_Size,
Nb_registres => Nb_Registres,
Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
Instructions_critiques_ecriture => Instructions_critiques_ecriture,
Code_Instruction_JMP => Code_Instruction_JMP,
Code_Instruction_JMZ => Code_Instruction_JMZ,
Code_Instruction_PRI => Code_Instruction_PRI,
Code_Instruction_PRIC => Code_Instruction_PRIC,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET,
Code_Instruction_STOP => Code_Instruction_STOP
)
port map (
CLK => CLK,
RST => RST,
Z => Z,
STD_IN_Request => intern_STD_IN_Request,
A => A_from_1,
B => B_from_1,
C => C_from_1,
Instruction => Instruction_from_1
);
instance_Etage2_5 : Etage2_5_Registres
generic map( Nb_bits => Nb_bits,
Nb_Registres => Nb_Registres,
Addr_registres_size => Addr_registres_size,
Instruction_bus_size => Instruction_Bus_Size,
Bits_Controle_LC_5 => Bits_Controle_LC_5,
Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
Code_Instruction_PRI => Code_Instruction_PRI,
Code_Instruction_PRIC => Code_Instruction_PRIC,
Code_Instruction_GET => Code_Instruction_GET
)
port map( CLK => CLK,
RST => RST,
STD_IN => STD_IN,
STD_IN_Av => STD_IN_Av,
STD_IN_Request => intern_STD_IN_Request,
STD_OUT => STD_OUT,
STD_OUT_Av => STD_OUT_Av,
STD_OUT_Int => STD_OUT_Int,
IN_2_A => A_to_2,
IN_2_B => B_to_2,
IN_2_C => C_to_2,
IN_2_Instruction => Instruction_to_2,
OUT_2_A => A_from_2,
OUT_2_B => B_from_2,
OUT_2_C => C_from_2,
OUT_2_Instruction => Instruction_from_2,
IN_5_A => A_to_5,
IN_5_B => B_to_5,
IN_5_Instruction => Instruction_to_5
);
instance_Etage3 : Etage3_Calcul
generic map( Nb_bits => Nb_bits,
Instruction_bus_size => Instruction_Bus_Size,
Bits_Controle_LC => Bits_Controle_LC_3,
Bits_Controle_MUX => Bits_Controle_MUX_3
)
port map( RST => RST,
IN_A => A_to_3,
IN_B => B_to_3,
IN_C => C_to_3,
IN_Instruction => Instruction_to_3,
OUT_A => A_from_3,
OUT_B => B_from_3,
OUT_Instruction => Instruction_from_3,
N => N,
O => O,
Z => Z,
C => C
);
instance_Etage4 : Etage4_Memoire
generic map( Nb_bits => Nb_bits,
Mem_size => Memoire_Size,
Adresse_mem_size => Adresse_mem_size,
Instruction_bus_size => Instruction_Bus_Size,
Mem_EBP_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
Bits_Controle_LC => Bits_Controle_LC_4,
Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET
)
port map( CLK => CLK,
RST => RST,
IN_A => A_to_4,
IN_B => B_to_4,
IN_Instruction => Instruction_to_4,
OUT_A => A_from_4,
OUT_B => B_from_4,
OUT_Instruction => Instruction_from_4
);
STD_IN_Request <= intern_STD_IN_Request;
process
begin
wait until CLK'event and CLK = '1';
if (intern_STD_IN_Request = '0') then
A_to_2 <= A_from_1;
B_to_2 <= B_from_1;
C_to_2 <= C_from_1;
Instruction_to_2 <= Instruction_from_1;
A_to_3 <= A_from_2;
B_to_3 <= B_from_2;
C_to_3 <= C_from_2;
Instruction_to_3 <= Instruction_from_2;
A_to_4 <= A_from_3;
B_to_4 <= B_from_3;
Instruction_to_4 <= Instruction_from_3;
A_to_5 <= A_from_4;
B_to_5 <= B_from_4;
Instruction_to_5 <= Instruction_from_4;
end if;
end process;
end Behavioral;

157
Processeur.srcs/sources_1/new/Pipeline_NS.vhd
View file

@ -1,44 +1,51 @@
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Company: INSA-Toulouse -- Company:
-- Engineer: Paul Faure -- Engineer:
-- --
-- Create Date: 19.04.2021 16:57:41 -- Create Date: 19.04.2021 16:57:41
-- Design Name:
-- Module Name: Pipeline_NS - Behavioral -- Module Name: Pipeline_NS - Behavioral
-- Project Name: Processeur sécurisé -- Project Name:
-- Target Devices: Basys 3 ARTIX7 -- Target Devices:
-- Tool Versions: Vivado 2016.4 -- Tool Versions:
-- Description: Version non sécurisée du pipeline, connecte les étages et fait avancer les signaux sur le pipeline -- Description:
-- --
-- Dependencies: -- Dependencies:
-- - Etage1_LectureInstruction_NS --
-- - Etage2_5_Registres -- Revision:
-- - Etage3_Calcul -- Revision 0.01 - File Created
-- - Etage4_Memoire_NS -- Additional Comments:
--
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Pipeline_NS is entity Pipeline_NS is
Generic (Nb_bits : Natural := 8; -- Taille d'un mot binaire Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire) Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3; -- Nombre de bits pour adresser la mémoire d'instruction Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8; -- Taille de la mémoire d'instruction (nombre d'instructions stockées) Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 5; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32; -- Nombre d'instructions dans le processeur Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16; -- Nombre de registres du processeurs Nb_Registres : Natural := 16;
Addr_registres_size : Natural := 4; -- Nombre de bits pour adresser les registres Addr_registres_size : Natural := 4;
Memoire_Size : Natural := 32; -- Taille de la mémoire de données Memoire_Size : Natural := 32;
Adresse_mem_size : Natural := 5); -- Nombre de bits pour adresser la mémoire Adresse_mem_size : Natural := 5);
Port (CLK : STD_LOGIC; Port (CLK : STD_LOGIC;
RST : STD_LOGIC; RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_IN_Av : in STD_LOGIC; STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
STD_IN_Request : out STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC;
STD_OUT_Int : out STD_LOGIC);
end Pipeline_NS; end Pipeline_NS;
architecture Behavioral of Pipeline_NS is architecture Behavioral of Pipeline_NS is
@ -56,15 +63,12 @@ architecture Behavioral of Pipeline_NS is
Instructions_critiques_ecriture : STD_LOGIC_VECTOR; Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
Code_Instruction_JMP : STD_LOGIC_VECTOR; Code_Instruction_JMP : STD_LOGIC_VECTOR;
Code_Instruction_JMZ : STD_LOGIC_VECTOR; Code_Instruction_JMZ : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_PRIC : STD_LOGIC_VECTOR;
Code_Instruction_CALL : STD_LOGIC_VECTOR; Code_Instruction_CALL : STD_LOGIC_VECTOR;
Code_Instruction_RET : STD_LOGIC_VECTOR; Code_Instruction_RET : STD_LOGIC_VECTOR;
Code_Instruction_STOP : STD_LOGIC_VECTOR); Code_Instruction_STOP : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC; Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; RST : in STD_LOGIC;
Z : in STD_LOGIC; Z : in STD_LOGIC;
STD_IN_Request : in STD_LOGIC;
Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4 Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -81,16 +85,11 @@ architecture Behavioral of Pipeline_NS is
Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR; Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR; Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
Code_Instruction_PRI : STD_LOGIC_VECTOR; Code_Instruction_PRI : STD_LOGIC_VECTOR;
Code_Instruction_PRIC : STD_LOGIC_VECTOR;
Code_Instruction_GET : STD_LOGIC_VECTOR); Code_Instruction_GET : STD_LOGIC_VECTOR);
Port ( CLK : in STD_LOGIC; Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC; RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de données depuis l'exterieur du processeur STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_IN_Av : in STD_LOGIC; STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_IN_Request : out STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de données vers l'exterieur du processeur
STD_OUT_Av : out STD_LOGIC;
STD_OUT_Int : out STD_LOGIC;
IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -145,7 +144,6 @@ architecture Behavioral of Pipeline_NS is
OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component; end component;
-- Signaux reliant les étages
signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
@ -174,42 +172,33 @@ architecture Behavioral of Pipeline_NS is
signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0'); signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0'); signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0'); signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
-- Sorties de l'ALU
signal N : STD_LOGIC := '0'; signal N : STD_LOGIC := '0';
signal Z : STD_LOGIC := '0'; signal Z : STD_LOGIC := '0';
signal O : STD_LOGIC := '0'; signal O : STD_LOGIC := '0';
signal C : STD_LOGIC := '0'; signal C : STD_LOGIC := '0';
-- Sortie de l'adresse de retour de l'étage 4 vers le 1
signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
signal intern_STD_IN_Request : STD_LOGIC := '0'; constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
-- Constantes de contrôle des MUX et LC
constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11110011101111111111111";
constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111000011000000001";
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000"; constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111111111100000001"; constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111001011111111111"; constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "11111111110101111111111"; constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111";
constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "10011111011001111111111"; constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000001010000000000"; constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110"; constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
-- Code de certaines instructions
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111"; constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000"; constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001"; constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
constant Code_Instruction_PRIC : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010"; constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011"; constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100"; constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101"; constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10110";
-- Constantes de contrôle des bulles constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00001100010000000000000"; constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000111100111111110"; constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00000000000000011111110"; constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "111111111" & "00010000001011111111110";
begin begin
instance_Etage1 : Etage1_LectureInstruction_NS instance_Etage1 : Etage1_LectureInstruction_NS
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size, generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
@ -224,8 +213,6 @@ begin
Instructions_critiques_ecriture => Instructions_critiques_ecriture, Instructions_critiques_ecriture => Instructions_critiques_ecriture,
Code_Instruction_JMP => Code_Instruction_JMP, Code_Instruction_JMP => Code_Instruction_JMP,
Code_Instruction_JMZ => Code_Instruction_JMZ, Code_Instruction_JMZ => Code_Instruction_JMZ,
Code_Instruction_PRI => Code_Instruction_PRI,
Code_Instruction_PRIC => Code_Instruction_PRIC,
Code_Instruction_CALL => Code_Instruction_CALL, Code_Instruction_CALL => Code_Instruction_CALL,
Code_Instruction_RET => Code_Instruction_RET, Code_Instruction_RET => Code_Instruction_RET,
Code_Instruction_STOP => Code_Instruction_STOP Code_Instruction_STOP => Code_Instruction_STOP
@ -234,7 +221,6 @@ begin
CLK => CLK, CLK => CLK,
RST => RST, RST => RST,
Z => Z, Z => Z,
STD_IN_Request => intern_STD_IN_Request,
Addr_Retour => AdresseRetour, Addr_Retour => AdresseRetour,
A => A_from_1, A => A_from_1,
B => B_from_1, B => B_from_1,
@ -251,17 +237,12 @@ begin
Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A, Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B, Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
Code_Instruction_PRI => Code_Instruction_PRI, Code_Instruction_PRI => Code_Instruction_PRI,
Code_Instruction_PRIC => Code_Instruction_PRIC,
Code_Instruction_GET => Code_Instruction_GET Code_Instruction_GET => Code_Instruction_GET
) )
port map( CLK => CLK, port map( CLK => CLK,
RST => RST, RST => RST,
STD_IN => STD_IN, STD_IN => STD_IN,
STD_IN_Av => STD_IN_Av, STD_OUT => STD_OUT,
STD_IN_Request => intern_STD_IN_Request,
STD_OUT => STD_OUT,
STD_OUT_Av => STD_OUT_Av,
STD_OUT_Int => STD_OUT_Int,
IN_2_A => A_to_2, IN_2_A => A_to_2,
IN_2_B => B_to_2, IN_2_B => B_to_2,
IN_2_C => C_to_2, IN_2_C => C_to_2,
@ -318,30 +299,26 @@ begin
OUT_AddrRetour => AdresseRetour OUT_AddrRetour => AdresseRetour
); );
STD_IN_Request <= intern_STD_IN_Request;
process process
begin begin
wait until CLK'event and CLK = '1'; wait until CLK'event and CLK = '1';
if (intern_STD_IN_Request = '0') then A_to_2 <= A_from_1;
A_to_2 <= A_from_1; B_to_2 <= B_from_1;
B_to_2 <= B_from_1; C_to_2 <= C_from_1;
C_to_2 <= C_from_1; Instruction_to_2 <= Instruction_from_1;
Instruction_to_2 <= Instruction_from_1;
A_to_3 <= A_from_2; A_to_3 <= A_from_2;
B_to_3 <= B_from_2; B_to_3 <= B_from_2;
C_to_3 <= C_from_2; C_to_3 <= C_from_2;
Instruction_to_3 <= Instruction_from_2; Instruction_to_3 <= Instruction_from_2;
A_to_4 <= A_from_3; A_to_4 <= A_from_3;
B_to_4 <= B_from_3; B_to_4 <= B_from_3;
Instruction_to_4 <= Instruction_from_3; Instruction_to_4 <= Instruction_from_3;
A_to_5 <= A_from_4; A_to_5 <= A_from_4;
B_to_5 <= B_from_4; B_to_5 <= B_from_4;
Instruction_to_5 <= Instruction_from_4; Instruction_to_5 <= Instruction_from_4;
end if;
end process; end process;
end Behavioral; end Behavioral;

114
Processeur.srcs/sources_1/new/ScreenDriver.vhd
View file

@ -1,114 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 09.07.2021 09:54:12
-- Module Name: ScreenDriver - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Fait le lien entre le processeur et l'écran
--
-- Dependencies: None
--
-- Comments: Gère la conversion des entiers en hexa pour l'affichage
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ScreenDriver is
Generic ( Nb_bits : Natural
);
Port ( CLK : in STD_LOGIC;
Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); -- ********************************
ValueAv : in STD_LOGIC; -- ***** Depuis le processeur *****
IsInt : in STD_LOGIC; -- ********************************
OutData : out STD_LOGIC_VECTOR (0 to 6); -- ********************************
OutDataAv : out STD_LOGIC); -- ********* Vers l'écran *********
end ScreenDriver;
architecture Behavioral of ScreenDriver is
-- Signal pour récupérer la valeur entière
signal intern_value : STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0) := (others => '0');
-- 4 bits actuellement en cours de conversion
signal current_hexa : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
-- Type pour gérer l'avancement dans la conversion
subtype compteur_T is Integer range -2 to Nb_bits/4 - 1;
-- Signal comptant l'avancement dans la conversion (début a -2, affichage de "0x" puis début de la conversion avec compteur = 0)
signal compteur : compteur_T := -2;
-- Si un digit non nul a été detecté
signal first_detected : BOOLEAN := false;
constant Code_ASCII_Zero : STD_LOGIC_VECTOR (0 to 6) := "0110000";
begin
-- Récupération des 4 bits en cours de conversion
current_hexa <= intern_value(Nb_Bits - 1 - compteur * 4 downto Nb_Bits - compteur * 4 - 4) when compteur >= 0 and compteur < Nb_Bits else "0000";
process
begin
wait until CLK'event and CLK = '1';
if ValueAv = '1' then
-- Si on a une donnée en entier
if IsInt = '0' then
-- Si c'est un char on la répercute juste
OutData <= Value (6 downto 0);
else
-- Si c'est un entier, on récupère la valeur et affiche le 0
intern_value <= Value;
OutData <= Code_ASCII_Zero;
compteur <= compteur + 1;
end if;
-- On signal a l'écran qu'il faut afficher
OutDataAv <= '1';
elsif compteur = -1 then
-- Si une conversion est en cours a l'étape -1, on affiche x
OutData <= "1111000";
compteur <= compteur + 1;
elsif compteur >= 0 then
-- Si on est en phase de conversion
if (current_hexa >= "0000" and current_hexa <= "1001") then
-- Si on est sur un chiffre (0-9)
if (not(current_hexa = "0000") or first_detected or compteur = Nb_bits/4 - 1 ) then
-- On l'affiche si ce n'est pas 0, ou qu'un digit a déjà été detecté, ou qu'il s'agit du dernier digit de l'entier
OutData <= "011" & current_hexa;
OutDataAv <= '1';
first_detected <= true;
else
-- Sinon, le digit est un 0 inutile, on ne l'affiche pas
OutDataAv <= '0';
end if;
else
-- Si on est sur une lettre (A-F), on l'affiche
OutData <= ("000" & current_hexa) + "0110111";
OutDataAv <= '1';
first_detected <= true;
end if;
if (compteur = Nb_bits/4 - 1) then
-- Si la conversion est finie on réinitialise
compteur <= -2;
first_detected <= false;
else
-- Sinon on avance le compteur
compteur <= compteur + 1;
end if;
else
OutDataAv <= '0';
end if;
end process;
end Behavioral;

48
Processeur.srcs/sources_1/new/ScreenProperties.vhd
View file

@ -1,48 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 02.07.2021 10:07:41
-- Package Name: ScreenProperties
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Rassemble les propriétés de l'écran et du VGA
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package ScreenProperties is
constant margin : Natural := 64; -- Marge laissée de tous les cotés de l'écran
constant Display_CaracterWidht : Natural := 64; -- Taille d'affichage d'un caractère (en pixels)
constant Display_CaracterHeight : Natural := 64; -- Taille d'affichage d'un caractère (en pixels)
constant screen_width : natural := 1280; -- Largeur de l'écran (en pixels)
constant screen_height : natural := 1024; -- Longueur de l'écran (en pixels)
constant X_PulseWidth : Natural := 112; -- Taille de la pulsation de synchronisation horizontale (en pixels)
constant X_FrontPorch : Natural := 48; -- Taille du temps avant la pulsation (en pixels)
constant X_BackPorch : Natural := 248; -- Taille du temps après la pulsation (en pixels)
constant Y_PulseWidth : Natural := 3; -- Taille de la pulsation de synchronisation verticale (en lignes)
constant Y_FrontPorch : Natural := 1; -- Taille du temps avant la pulsation (en lignes)
constant Y_BackPorch : Natural := 38; -- Taille du temps après la pulsation (en lignes)
subtype X_T is Natural range 0 to screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1; -- Type pour les coordonnées
subtype Y_T is Natural range 0 to screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1; -- Type pour les coordonnées
constant C_Blocks : Natural := (screen_width - (2 * margin))/Display_CaracterWidht; -- Nombre de cases par ligne dans l'écran (Nombre de colonnes)
constant L_Blocks : Natural := (screen_height - (2 * margin))/Display_CaracterHeight; -- Nombre de cases par colonne dans l'écran (Nombre de lignes)
constant Ecran_Taille : Natural := C_Blocks * L_Blocks * 7; -- Nombre de bits dans l'écran (Nombre cases dans l'écran * 7)
constant L_Size : Natural := C_Blocks * 7; -- Taille en bits d'une ligne
constant Zero_Line : STD_LOGIC_VECTOR (0 to L_Size - 1) := (others => '0'); -- Constante, ligne de '0'
subtype L_T is Natural range 0 to L_Blocks - 1; -- Type pour les coordonnées
subtype C_T is Natural range 0 to C_Blocks - 1; -- Type pour les coordonnées
end package;

194
Processeur.srcs/sources_1/new/System.vhd
View file

@ -7,14 +7,11 @@
-- Project Name: Processeur sécurisé -- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7 -- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4 -- Tool Versions: Vivado 2016.4
-- Description: Environnement du processeur, mapping entre le processeur et les periphériques, affectation des ports la carte -- Description: Environnement du processeur, mapping entre le processeur et la carte
-- --
-- Dependencies: -- Dependencies:
-- - Clock_Divider -- - Clock_Divider
-- - Pipeline -- - Pipeline
-- - Pipeline_NS
-- - PeripheriqueEcran
-- - PeripheriqueClavier
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
@ -22,47 +19,18 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
-- Lien avec le fichier de contraintes -- Lien avec le fichier de contraintes
-- Récupération du VGA -- Récupération des leds pour STD_OUT
-- Récupération du PS2 -- Récupération des switchs pour STD_IN
-- Récupération d'un bouton pour RST -- Récupération d'un bouton pour RST
-- Récupération de la clock -- Récupération de la clock
entity System is entity System is
Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0); Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); sw : in STD_LOGIC_VECTOR (7 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
btnC : in STD_LOGIC; btnC : in STD_LOGIC;
CLK : STD_LOGIC); CLK : STD_LOGIC);
end System; end System;
architecture Structural of System is architecture Structural of System is
component Pipeline is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
Memoire_Instruction_Size : Natural := 8;
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Addr_registres_size : Natural := 4;
Memoire_Size : Natural := 32;
Adresse_mem_size : Natural := 5;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_IN_Av : in STD_LOGIC;
STD_IN_Request : out STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC;
STD_OUT_Int : out STD_LOGIC);
end component;
component Pipeline_NS is component Pipeline_NS is
Generic (Nb_bits : Natural := 8; Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29; Instruction_En_Memoire_Size : Natural := 29;
@ -71,47 +39,11 @@ architecture Structural of System is
Instruction_Bus_Size : Natural := 5; Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32; Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16; Nb_Registres : Natural := 16;
Addr_registres_size : Natural := 4; Memoire_Size : Natural := 32);
Memoire_Size : Natural := 32;
Adresse_mem_size : Natural := 5);
Port (CLK : STD_LOGIC; Port (CLK : STD_LOGIC;
RST : STD_LOGIC; RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_IN_Av : in STD_LOGIC; STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
STD_IN_Request : out STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC;
STD_OUT_Int : out STD_LOGIC);
end component;
component PeripheriqueEcran
Generic ( Nb_Bits : Natural);
Port ( CLK : in STD_LOGIC;
CLK_VGA : in STD_LOGIC;
RST : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_OUT_Av : in STD_LOGIC;
STD_OUT_Int : in STD_LOGIC);
end component;
component PeripheriqueClavier
Generic (Nb_Bits : Natural);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_IN_Av : out STD_LOGIC;
STD_IN_Request : in STD_LOGIC;
STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
STD_OUT_Av : out STD_LOGIC);
end component; end component;
component Clock_Divider is component Clock_Divider is
@ -120,116 +52,26 @@ architecture Structural of System is
end component; end component;
-- signaux auxiliaires -- signaux auxiliaires
signal my_RST : STD_LOGIC; -- Signal de RST (inversion par rapport au btnC) signal my_RST : STD_LOGIC;
signal my_CLK : STD_LOGIC; -- Signal de clock (divisée par rapport CLK) signal my_CLK : STD_LOGIC;
-- signaux de gestion de l'entrée
signal STD_IN : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Entrée
signal STD_IN_Av : STD_LOGIC := '0'; -- Entrée disponible en lecture sur le clavier
signal STD_IN_Request : STD_LOGIC := '0'; -- Demande d'une entrée au clavier
-- signaux de gestion de la sortie
signal STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie vers l'écran
signal STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible pour l'écran
signal STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) pour l'écran
signal pipeline_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie depuis le Pipeline
signal pipeline_STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible depuis le Pipeline
signal pipeline_STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) depuis le pipeline
signal clavier_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie depuis le Clavier
signal clavier_STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible depuis le Clavier
signal clavier_STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) depuis le Clavier
constant SECURED : boolean := true; -- Booléen de sélection entre la version sécurisée et non sécurisée
begin begin
-- Diviseur de clock -- Diviseur de clock
clk_div : Clock_Divider clk_div : Clock_Divider
port map (CLK_IN => CLK, port map (CLK_IN => CLK,
CLK_OUT => my_CLK); CLK_OUT => my_CLK);
-- Le processeur, augmentation de la taille de la mémoire d'instruction
-- Generation du pipeline en fonction de la condition sécurisé ou non instance : Pipeline_NS
instance: if (SECURED) generate generic map (Addr_Memoire_Instruction_Size => 8,
instance_securisee : entity work.Pipeline Memoire_Instruction_Size => 256)
generic map (Nb_bits => 16, port map (CLK => my_CLK,
Instruction_En_Memoire_Size => 53, RST => my_RST,
Addr_Memoire_Instruction_Size => 9, STD_IN => sw,
Memoire_Instruction_Size => 512, STD_OUT => led);
Instruction_Bus_Size => 5,
Nb_Instructions => 32,
Nb_Registres => 16,
Addr_registres_size => 4,
Memoire_Size => 64,
Adresse_mem_size => 6,
Memoire_Adresses_Retour_Size => 4,
Adresse_Memoire_Adresses_Retour_Size => 2)
port map (CLK => my_CLK,
RST => my_RST,
STD_IN => STD_IN,
STD_IN_Av => STD_IN_Av,
STD_IN_Request => STD_IN_Request,
STD_OUT => pipeline_STD_OUT,
STD_OUT_Av => pipeline_STD_OUT_Av,
STD_OUT_Int => pipeline_STD_OUT_Int);
else generate
instance_non_securisee : entity work.Pipeline_NS
generic map (Nb_bits => 16,
Instruction_En_Memoire_Size => 53,
Addr_Memoire_Instruction_Size => 9,
Memoire_Instruction_Size => 512,
Instruction_Bus_Size => 5,
Nb_Instructions => 32,
Nb_Registres => 16,
Addr_registres_size => 4,
Memoire_Size => 64,
Adresse_mem_size => 6)
port map (CLK => my_CLK,
RST => my_RST,
STD_IN => STD_IN,
STD_IN_Av => STD_IN_Av,
STD_IN_Request => STD_IN_Request,
STD_OUT => pipeline_STD_OUT,
STD_OUT_Av => pipeline_STD_OUT_Av,
STD_OUT_Int => pipeline_STD_OUT_Int);
end generate;
instance_perif_ecran : PeripheriqueEcran
generic map ( Nb_Bits => 16)
port map ( CLK => my_CLK,
CLK_VGA => CLK,
RST => my_RST,
vgaRed => vgaRed,
vgaBlue => vgaBlue,
vgaGreen => vgaGreen,
Hsync => Hsync,
Vsync => Vsync,
STD_OUT => STD_OUT,
STD_OUT_Av => STD_OUT_Av,
STD_OUT_Int => STD_OUT_Int);
instance_perif_clavier : PeripheriqueClavier
generic map (Nb_Bits => 16)
port map ( CLK => my_CLK,
RST => my_RST,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
STD_IN => STD_IN,
STD_IN_Av => STD_IN_Av,
STD_IN_Request => STD_IN_Request,
STD_OUT => clavier_STD_OUT,
STD_OUT_Av => clavier_STD_OUT_Av);
-- Gestion du RST (inversion d'état) -- Gestion du RST (inversion d'état)
my_RST <= '1' when btnC = '0' else my_RST <= '1' when btnC = '0' else
'0'; '0';
-- Gestion de l'affichage sur l'écran lors d'une demande d'entrée le clavier affiche sur l'écran
STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT;
STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av;
STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int;
end Structural; end Structural;

231
Processeur.srcs/sources_1/new/SystemKeyboardScreen.vhd
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@ -1,231 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 10:04:44
-- Design Name:
-- Module Name: SystemKeyboardScreen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SystemKeyboardScreen is
Port ( CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC);
end SystemKeyboardScreen;
architecture Behavioral of SystemKeyboardScreen is
component Keyboard
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 6);
alert : out STD_LOGIC);
end component;
component VGAControler is
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component;
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end component;
component Ecran is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in X_T;
Y : in Y_T;
OUT_ON : out STD_LOGIC);
end component;
signal my_X : X_T := 0;
signal my_Y : Y_T := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal Keyboard_Data_read : STD_LOGIC := '0';
signal Keyboard_Data_av : STD_LOGIC := '0';
signal Keyboard_Data : STD_LOGIC_VECTOR (0 to 6);
signal Screen_Data_av : STD_LOGIC := '0';
signal alert : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
signal RST : STD_LOGIC := '1';
begin
instanceVGA : VGAControler
port map( VGA_RED => vgaRed,
VGA_BLUE => vgaBlue,
VGA_GREEN => vgaGreen,
VGA_HS => Hsync,
VGA_VS => Vsync,
X => my_X,
Y => my_Y,
PIXEL_ON => my_PIXEL_ON,
CLK => my_CLK,
RST => RST);
clk_wiz_0_inst : clk_wiz_0
port map (
clk_in1 => CLK,
clk_out1 => my_CLK
);
instance_Ecran : Ecran
port map ( CLK => CLK,
RST => RST,
Data_Av => Screen_Data_av,
Data_IN => Keyboard_Data,
X => my_X,
Y => my_Y,
OUT_ON => my_PIXEL_ON);
instance_Keyboard : Keyboard
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_read => Keyboard_Data_av,
Data_av => Keyboard_Data_av,
Data => Keyboard_Data,
alert => alert);
process
begin
wait until CLK'event and CLK = '1';
if (Keyboard_Data_av = '1') then
Screen_Data_av <= '1';
else
Screen_Data_av <= '0';
end if;
end process;
end Behavioral;
--entity SystemKeyboardScreen is
-- Port ( CLK : in STD_LOGIC;
-- led : out STD_LOGIC_VECTOR (0 to 0);
-- btnC : in STD_LOGIC;
-- sw : in STD_LOGIC_VECTOR (0 to 6));
--end SystemKeyboardScreen;
--architecture Behavioral of SystemKeyboardScreen is
-- component Ecran is
-- Port ( CLK : in STD_LOGIC;
-- RST : in STD_LOGIC;
-- Data_Av : in STD_LOGIC;
-- Data_IN : in STD_LOGIC_VECTOR (0 to 6);
-- X : in X_T;
-- Y : in Y_T;
-- OUT_ON : out STD_LOGIC);
-- end component;
-- component Compteur_X is
-- Port ( CLK : in STD_LOGIC;
-- RST : in STD_LOGIC;
-- Value : out X_T;
-- Carry : out STD_LOGIC);
-- end component;
-- component Compteur_Y is
-- Port ( CLK : in STD_LOGIC;
-- RST : in STD_LOGIC;
-- Value : out Y_T);
-- end component;
-- signal my_X : X_T := 0;
-- signal my_Y : Y_T := 0;
-- signal Y_CLK : STD_LOGIC := '0';
-- signal RST : STD_LOGIC := '1';
--begin
-- X_Compteur : Compteur_X
-- port map (CLK => CLK,
-- RST => RST,
-- Value => my_X,
-- Carry => Y_CLK);
-- Y_Compteur : Compteur_Y
-- port map (CLK => Y_CLK,
-- RST => RST,
-- Value => my_Y);
-- instance_Ecran : Ecran
-- port map ( CLK => CLK,
-- RST => RST,
-- Data_Av => btnC,
-- Data_IN => sw,
-- X => my_X,
-- Y => my_Y,
-- OUT_ON => led(0));
--end Behavioral;

41
Processeur.srcs/sources_1/new/TableASCII.vhd
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@ -1,41 +0,0 @@
-----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 28.06.2021 09:20:00
-- Module Name: TableASCII - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Table indexée sur le code ascii contenant la font de chaque caractère
--
-- Dependencies: None
--
-- Comments : Assynchrone
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.font.all;
entity TableASCII is
Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
end TableASCII;
architecture Behavioral of TableASCII is
signal FontMemory : STD_LOGIC_VECTOR (0 to (128 * font_width * font_height) - 1) := (x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000183C3C1818001800363600000000000036367F367F3636000C3E031E301F0C00006333180C6663001C361C6E3B336E000606030000000000180C0606060C1800060C1818180C060000663CFF3C660000000C0C3F0C0C000000000000000C0C060000003F0000000000000000000C0C006030180C060301003E63737B6F673E000C0E0C0C0C0C3F001E33301C06333F001E33301C30331E00383C36337F3078003F031F3030331E001C06031F33331E003F3330180C0C0C001E33331E33331E001E33333E30180E00000C0C00000C0C00000C0C00000C0C06180C0603060C180000003F00003F0000060C1830180C06001E3330180C000C003E637B7B7B031E000C1E33333F3333003F66663E66663F003C66030303663C001F36666666361F007F46161E16467F007F46161E16060F003C66030373667C003333333F333333001E0C0C0C0C0C1E007830303033331E006766361E366667000F06060646667F0063777F7F6B63630063676F7B736363001C36636363361C003F66663E06060F001E3333333B1E38003F66663E366667001E33070E38331E003F2D0C0C0C0C1E003333333333333F0033333333331E0C006363636B7F7763006363361C1C3663003333331E0C0C1E007F6331184C667F001E06060606061E0003060C18306040001E18181818181E00081C36630000000000000000000000FF0C0C18000000000000001E303E336E000706063E66663B0000001E3303331E003830303e33336E0000001E333f031E001C36060f06060F0000006E33333E301F0706366E666667000C000E0C0C0C1E00300030303033331E070666361E3667000E0C0C0C0C0C1E000000337F7F6B630000001F333333330000001E3333331E0000003B66663E060F00006E33333E307800003B6E66060F0000003E031E301F00080C3E0C0C2C18000000333333336E0000003333331E0C000000636B7F7F3600000063361C36630000003333333E301F00003F190C263F00380C0C070C0C38001818180018181800070C0C380C0C07006E3B0000000000000000000000000000");
begin
Font <= FontMemory(font_height * font_width * to_integer(unsigned(CodeASCII)) to font_height * font_width * (to_integer(unsigned(CodeASCII)) + 1) - 1);
end Behavioral;

97
Processeur.srcs/sources_1/new/VGAControler.vhd
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@ -1,97 +0,0 @@
----------------------------------------------------------------------------------
-- Company: INSA-Toulouse
-- Engineer: Paul Faure
--
-- Create Date: 28.06.2021 09:20:00
-- Module Name: VGAControler - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
--
-- Description: Controleur du VGA
-- - Crée les signaux VGA
-- - Demande si le pixel (X,Y) doit être allumé
--
-- Dependencies: Compteur_X et Compteur_Y
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
entity VGAControler is
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end VGAControler;
architecture Behavioral of VGAControler is
component Compteur_X is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out X_T;
Carry : out STD_LOGIC);
end component;
component Compteur_Y is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Y_T);
end component;
signal X_pos : X_T := 0;
signal Y_pos : Y_T := 0;
signal Y_CLK : STD_LOGIC := '0';
signal active : BOOLEAN := false;
begin
X_Compteur : Compteur_X
port map (CLK => CLK,
RST => RST,
Value => X_pos,
Carry => Y_CLK);
Y_Compteur : Compteur_Y
port map (CLK => Y_CLK,
RST => RST,
Value => Y_pos);
-- Test si on est dans l'écran et non dans les zones de FP, BP, SP
active <= ((X_pos < screen_width) and (Y_pos < screen_height));
-- Affectation des couleurs et fonction du pixel (0 hors champs, gris si inactif, blanc si actif)
VGA_RED <= "0000" when ((RST = '0') or (not active)) else
"1000" when (PIXEL_ON = '0') else
"1111";
VGA_BLUE <= "0000" when ((RST = '0') or (not active)) else
"1000" when (PIXEL_ON = '0') else
"1111";
VGA_GREEN <= "0000" when ((RST = '0') or (not active)) else
"1000" when (PIXEL_ON = '0') else
"1111";
-- Création des signaux de synchronisation
VGA_HS <= '0' when ((RST = '0') or (X_pos < screen_width + X_FrontPorch) or (X_pos >= screen_width + X_FrontPorch + X_PulseWidth)) else
'1';
VGA_VS <= '0' when ((RST = '0') or (Y_pos < screen_height + Y_FrontPorch) or (Y_pos >= screen_height + Y_FrontPorch + Y_PulseWidth)) else
'1';
X <= X_pos;
Y <= Y_pos;
end Behavioral;

107
Processeur.srcs/sources_1/new/clk_wiz_0.vhd
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@ -1,107 +0,0 @@
-- file: clk_wiz_0.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_0 is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end clk_wiz_0;
architecture xilinx of clk_wiz_0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_wiz_0_clk_wiz
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end component;
begin
U0: clk_wiz_0_clk_wiz
port map (
-- Clock in ports
clk_in1 => clk_in1,
-- Clock out ports
clk_out1 => clk_out1
);
end xilinx;

201
Processeur.srcs/sources_1/new/clk_wiz_0_clk_wiz.vhd
View file

@ -1,201 +0,0 @@
-- file: clk_wiz_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_0_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic
);
end clk_wiz_0_clk_wiz;
architecture xilinx of clk_wiz_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_clk_wiz_0 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_wiz_0 : std_logic;
signal clkfbout_buf_clk_wiz_0 : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_clk_wiz_0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clk_in1_clk_wiz_0 <= clk_in1;
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_wiz_0,
I => clkfbout_clk_wiz_0);
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_out1_clk_wiz_0);
end xilinx;

6
Processeur.srcs/sources_1/new/font.vhd
View file

@ -1,6 +0,0 @@
package font is
constant font_width : natural := 8;
constant font_height : natural := 8;
end package;

255
Processeur.xpr
View file

@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.2 (64-bit) --> <!-- Product Version: Vivado v2016.4 (64-bit) -->
<!-- --> <!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="38" Path="/home/pfaure/Documents/PSI/Processeur/Processeur.xpr"> <Project Version="7" Minor="17" Path="/home/paulfaure/Documents/4A/PSI/Processeur/Processeur.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/> <Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
@ -13,7 +13,6 @@
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
@ -23,38 +22,35 @@
<Option Name="SourceMgmtMode" Val="DisplayOnly"/> <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/> <Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/> <Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/> <Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> <Option Name="IPUserFilesDir" Val="$PPRDIR/Processeur.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PPRDIR/Processeur.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/> <Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="603"/> <Option Name="WTXSimLaunchSim" Val="339"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="2"/> <Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="2"/> <Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="2"/> <Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="2"/> <Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="2"/> <Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="2"/> <Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="2"/> <Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="64"/> <Option Name="XSimArrayDisplayLimit" Val="64"/>
<Option Name="XSimTraceLimit" Val="65536"/> <Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration> </Configuration>
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@ -65,6 +61,12 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/System.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd"> <File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -101,18 +103,6 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@ -125,13 +115,13 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd"> <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
@ -143,121 +133,7 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd"> <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clk_wiz_0_clk_wiz.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clk_wiz_0.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ScreenProperties.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/VGAControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/font.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/TableASCII.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Ecran.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/System.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="simulation"/>
<Attr Name="UsedIn" Val="synthesis"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Keyboard.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/KeyboardControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/SystemKeyboardScreen.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/KeyboardToASCII.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Compteur_Y.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Compteur_X.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ScreenDriver.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/PeripheriqueEcran.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/PeripheriqueClavier.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/KeyboardDriver.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
@ -266,6 +142,7 @@
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System"/> <Option Name="TopModule" Val="System"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@ -361,68 +238,9 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sim_1/new/Test_Ecran.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_VGAControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestTableASCII.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_KeyboardControler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Keyboard.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_Compteur.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/Test_SystemKeyboardScreen.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestScreenDriver.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TestSystem.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/SimulationsConfig/TestSystem_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="TestSystem"/> <Option Name="TopModule" Val="Test_Pipeline"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
@ -431,7 +249,6 @@
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/TestSystem_behav.wcfg"/>
</Config> </Config>
</FileSet> </FileSet>
</FileSets> </FileSets>
@ -449,9 +266,6 @@
<Simulator Name="IES"> <Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/> <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator> </Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS"> <Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator> </Simulator>
@ -460,38 +274,29 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="10"> <Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Spread logic throughout the device to avoid creating congested regions. (medium setting)" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="false"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Congestion_SpreadLogic_medium" Flow="Vivado Implementation 2018"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
<Step Id="place_design"> <Step Id="place_design"/>
<Option Id="Directive">5</Option>
</Step>
<Step Id="post_place_power_opt_design"/> <Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"> <Step Id="phys_opt_design"/>
<Option Id="Directive">0</Option> <Step Id="route_design"/>
</Step>
<Step Id="route_design">
<Option Id="Directive">7</Option>
</Step>
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
</Runs> </Runs>
<Board/>
</Project> </Project>

576
SimulationsConfig/TestSystem_behav.wcfg
View file

@ -1,576 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="TestSystem_behav.wdb" id="1">
<top_modules>
<top_module name="TestSystem" />
<top_module name="font" />
<top_module name="screenproperties" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="10606008000000fs"></ZoomStartTime>
<ZoomEndTime time="10825655309273fs"></ZoomEndTime>
<Cursor1Time time="6077804260000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="251"></NameColumnWidth>
<ValueColumnWidth column_width="173"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="7" />
<wvobject type="logic" fp_name="/TestSystem/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="group" fp_name="group135">
<obj_property name="label">Pipeline</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/Instruction_from_1">
<obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/A_from_1">
<obj_property name="ElementShortName">A_from_1[15:0]</obj_property>
<obj_property name="ObjectShortName">A_from_1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/B_from_1">
<obj_property name="ElementShortName">B_from_1[15:0]</obj_property>
<obj_property name="ObjectShortName">B_from_1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/C_from_1">
<obj_property name="ElementShortName">C_from_1[15:0]</obj_property>
<obj_property name="ObjectShortName">C_from_1[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/Instruction_from_2">
<obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/A_from_2">
<obj_property name="ElementShortName">A_from_2[15:0]</obj_property>
<obj_property name="ObjectShortName">A_from_2[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/B_from_2">
<obj_property name="ElementShortName">B_from_2[15:0]</obj_property>
<obj_property name="ObjectShortName">B_from_2[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/C_from_2">
<obj_property name="ElementShortName">C_from_2[15:0]</obj_property>
<obj_property name="ObjectShortName">C_from_2[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/Instruction_from_3">
<obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/A_from_3">
<obj_property name="ElementShortName">A_from_3[15:0]</obj_property>
<obj_property name="ObjectShortName">A_from_3[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/B_from_3">
<obj_property name="ElementShortName">B_from_3[15:0]</obj_property>
<obj_property name="ObjectShortName">B_from_3[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/Instruction_from_4">
<obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/A_from_4">
<obj_property name="ElementShortName">A_from_4[15:0]</obj_property>
<obj_property name="ObjectShortName">A_from_4[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/B_from_4">
<obj_property name="ElementShortName">B_from_4[15:0]</obj_property>
<obj_property name="ObjectShortName">B_from_4[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group133">
<obj_property name="label">Gestion Instructions</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/Z">
<obj_property name="ElementShortName">Z</obj_property>
<obj_property name="ObjectShortName">Z</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/STD_IN_Request">
<obj_property name="ElementShortName">STD_IN_Request</obj_property>
<obj_property name="ObjectShortName">STD_IN_Request</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/Addr_Retour">
<obj_property name="ElementShortName">Addr_Retour[15:0]</obj_property>
<obj_property name="ObjectShortName">Addr_Retour[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/A">
<obj_property name="ElementShortName">A[15:0]</obj_property>
<obj_property name="ObjectShortName">A[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/B">
<obj_property name="ElementShortName">B[15:0]</obj_property>
<obj_property name="ObjectShortName">B[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/C">
<obj_property name="ElementShortName">C[15:0]</obj_property>
<obj_property name="ObjectShortName">C[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/Instruction">
<obj_property name="ElementShortName">Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">Instruction[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/Pointeur_instruction">
<obj_property name="ElementShortName">Pointeur_instruction[8:0]</obj_property>
<obj_property name="ObjectShortName">Pointeur_instruction[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/bulles">
<obj_property name="ElementShortName">bulles</obj_property>
<obj_property name="ObjectShortName">bulles</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/compteur">
<obj_property name="ElementShortName">compteur</obj_property>
<obj_property name="ObjectShortName">compteur</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/Compteur_PRI">
<obj_property name="ElementShortName">Compteur_PRI</obj_property>
<obj_property name="ObjectShortName">Compteur_PRI</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/locked">
<obj_property name="ElementShortName">locked</obj_property>
<obj_property name="ObjectShortName">locked</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage1/Tableau">
<obj_property name="ElementShortName">Tableau[1:3]</obj_property>
<obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group132">
<obj_property name="label">Registres</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/STD_IN">
<obj_property name="ElementShortName">STD_IN[15:0]</obj_property>
<obj_property name="ObjectShortName">STD_IN[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/STD_IN_Av">
<obj_property name="ElementShortName">STD_IN_Av</obj_property>
<obj_property name="ObjectShortName">STD_IN_Av</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/STD_IN_Request">
<obj_property name="ElementShortName">STD_IN_Request</obj_property>
<obj_property name="ObjectShortName">STD_IN_Request</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/STD_OUT">
<obj_property name="ElementShortName">STD_OUT[15:0]</obj_property>
<obj_property name="ObjectShortName">STD_OUT[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/STD_OUT_Av">
<obj_property name="ElementShortName">STD_OUT_Av</obj_property>
<obj_property name="ObjectShortName">STD_OUT_Av</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/STD_OUT_Int">
<obj_property name="ElementShortName">STD_OUT_Int</obj_property>
<obj_property name="ObjectShortName">STD_OUT_Int</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_2_A">
<obj_property name="ElementShortName">IN_2_A[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_2_A[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_2_B">
<obj_property name="ElementShortName">IN_2_B[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_2_B[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_2_C">
<obj_property name="ElementShortName">IN_2_C[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_2_C[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_2_Instruction">
<obj_property name="ElementShortName">IN_2_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">IN_2_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/OUT_2_A">
<obj_property name="ElementShortName">OUT_2_A[15:0]</obj_property>
<obj_property name="ObjectShortName">OUT_2_A[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/OUT_2_B">
<obj_property name="ElementShortName">OUT_2_B[15:0]</obj_property>
<obj_property name="ObjectShortName">OUT_2_B[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/OUT_2_C">
<obj_property name="ElementShortName">OUT_2_C[15:0]</obj_property>
<obj_property name="ObjectShortName">OUT_2_C[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/OUT_2_Instruction">
<obj_property name="ElementShortName">OUT_2_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">OUT_2_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_5_A">
<obj_property name="ElementShortName">IN_5_A[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_5_A[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_5_B">
<obj_property name="ElementShortName">IN_5_B[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_5_B[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/IN_5_Instruction">
<obj_property name="ElementShortName">IN_5_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">IN_5_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/Commande_BancRegistres">
<obj_property name="ElementShortName">Commande_BancRegistres[0:0]</obj_property>
<obj_property name="ObjectShortName">Commande_BancRegistres[0:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/Entree_BancRegistre_DATA">
<obj_property name="ElementShortName">Entree_BancRegistre_DATA[15:0]</obj_property>
<obj_property name="ObjectShortName">Entree_BancRegistre_DATA[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/Sortie_BancRegistres_A">
<obj_property name="ElementShortName">Sortie_BancRegistres_A[15:0]</obj_property>
<obj_property name="ObjectShortName">Sortie_BancRegistres_A[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage2_5/Sortie_BancRegistres_B">
<obj_property name="ElementShortName">Sortie_BancRegistres_B[15:0]</obj_property>
<obj_property name="ObjectShortName">Sortie_BancRegistres_B[15:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group134">
<obj_property name="label">Memoire</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="group" fp_name="group197">
<obj_property name="label">MemoireDonnees</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="group" fp_name="group198">
<obj_property name="label">MemoireAdressesRetour</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/IN_A">
<obj_property name="ElementShortName">IN_A[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_A[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/IN_B">
<obj_property name="ElementShortName">IN_B[15:0]</obj_property>
<obj_property name="ObjectShortName">IN_B[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/IN_Instruction">
<obj_property name="ElementShortName">IN_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">IN_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/OUT_A">
<obj_property name="ElementShortName">OUT_A[15:0]</obj_property>
<obj_property name="ObjectShortName">OUT_A[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/OUT_B">
<obj_property name="ElementShortName">OUT_B[15:0]</obj_property>
<obj_property name="ObjectShortName">OUT_B[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/OUT_Instruction">
<obj_property name="ElementShortName">OUT_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">OUT_Instruction[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/OUT_AddrRetour">
<obj_property name="ElementShortName">OUT_AddrRetour[15:0]</obj_property>
<obj_property name="ObjectShortName">OUT_AddrRetour[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/EBP">
<obj_property name="ElementShortName">EBP[5:0]</obj_property>
<obj_property name="ObjectShortName">EBP[5:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/Addr_MemoireDonnees">
<obj_property name="ElementShortName">Addr_MemoireDonnees[5:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees[5:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/IN_Addr_MemoireDonnees">
<obj_property name="ElementShortName">IN_Addr_MemoireDonnees[5:0]</obj_property>
<obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[5:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/Addr_MemoireDonnees_EBP">
<obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[5:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[5:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/Commande_MemoireDonnees">
<obj_property name="ElementShortName">Commande_MemoireDonnees[0:0]</obj_property>
<obj_property name="ObjectShortName">Commande_MemoireDonnees[0:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance/instance_non_securisee/instance_Etage4/Sortie_MemoireDonnees">
<obj_property name="ElementShortName">Sortie_MemoireDonnees[15:0]</obj_property>
<obj_property name="ObjectShortName">Sortie_MemoireDonnees[15:0]</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group136">
<obj_property name="label">PeripheriqueEcran</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="group" fp_name="group216">
<obj_property name="label">VGAControleur</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_RED">
<obj_property name="ElementShortName">VGA_RED[3:0]</obj_property>
<obj_property name="ObjectShortName">VGA_RED[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_BLUE">
<obj_property name="ElementShortName">VGA_BLUE[3:0]</obj_property>
<obj_property name="ObjectShortName">VGA_BLUE[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_GREEN">
<obj_property name="ElementShortName">VGA_GREEN[3:0]</obj_property>
<obj_property name="ObjectShortName">VGA_GREEN[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_HS">
<obj_property name="ElementShortName">VGA_HS</obj_property>
<obj_property name="ObjectShortName">VGA_HS</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/VGA_VS">
<obj_property name="ElementShortName">VGA_VS</obj_property>
<obj_property name="ObjectShortName">VGA_VS</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/X">
<obj_property name="ElementShortName">X</obj_property>
<obj_property name="ObjectShortName">X</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/Y">
<obj_property name="ElementShortName">Y</obj_property>
<obj_property name="ObjectShortName">Y</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/PIXEL_ON">
<obj_property name="ElementShortName">PIXEL_ON</obj_property>
<obj_property name="ObjectShortName">PIXEL_ON</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instanceVGA/active">
<obj_property name="ElementShortName">active</obj_property>
<obj_property name="ObjectShortName">active</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group217">
<obj_property name="label">Ecran</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Data_Av">
<obj_property name="ElementShortName">Data_Av</obj_property>
<obj_property name="ObjectShortName">Data_Av</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Data_IN">
<obj_property name="ElementShortName">Data_IN[0:6]</obj_property>
<obj_property name="ObjectShortName">Data_IN[0:6]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/X">
<obj_property name="ElementShortName">X</obj_property>
<obj_property name="ObjectShortName">X</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Y">
<obj_property name="ElementShortName">Y</obj_property>
<obj_property name="ObjectShortName">Y</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/OUT_ON">
<obj_property name="ElementShortName">OUT_ON</obj_property>
<obj_property name="ObjectShortName">OUT_ON</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Ecran">
<obj_property name="ElementShortName">Ecran[0:559]</obj_property>
<obj_property name="ObjectShortName">Ecran[0:559]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/L">
<obj_property name="ElementShortName">L[0:6]</obj_property>
<obj_property name="ObjectShortName">L[0:6]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/C">
<obj_property name="ElementShortName">C[0:6]</obj_property>
<obj_property name="ObjectShortName">C[0:6]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/InitialL">
<obj_property name="ElementShortName">InitialL[0:6]</obj_property>
<obj_property name="ObjectShortName">InitialL[0:6]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/Full">
<obj_property name="ElementShortName">Full</obj_property>
<obj_property name="ObjectShortName">Full</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/point_dereferencement">
<obj_property name="ElementShortName">point_dereferencement</obj_property>
<obj_property name="ObjectShortName">point_dereferencement</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/point_dereferencement_ecriture">
<obj_property name="ElementShortName">point_dereferencement_ecriture</obj_property>
<obj_property name="ObjectShortName">point_dereferencement_ecriture</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CurrentCodeASCII">
<obj_property name="ElementShortName">CurrentCodeASCII[0:6]</obj_property>
<obj_property name="ObjectShortName">CurrentCodeASCII[0:6]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_Ecran/CurrentFont">
<obj_property name="ElementShortName">CurrentFont[0:63]</obj_property>
<obj_property name="ObjectShortName">CurrentFont[0:63]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group218">
<obj_property name="label">ScreenDriver</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/Value">
<obj_property name="ElementShortName">Value[15:0]</obj_property>
<obj_property name="ObjectShortName">Value[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/ValueAv">
<obj_property name="ElementShortName">ValueAv</obj_property>
<obj_property name="ObjectShortName">ValueAv</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/IsInt">
<obj_property name="ElementShortName">IsInt</obj_property>
<obj_property name="ObjectShortName">IsInt</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/OutData">
<obj_property name="ElementShortName">OutData[0:6]</obj_property>
<obj_property name="ObjectShortName">OutData[0:6]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/OutDataAv">
<obj_property name="ElementShortName">OutDataAv</obj_property>
<obj_property name="ObjectShortName">OutDataAv</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/intern_value">
<obj_property name="ElementShortName">intern_value[15:0]</obj_property>
<obj_property name="ObjectShortName">intern_value[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/current_hexa">
<obj_property name="ElementShortName">current_hexa[3:0]</obj_property>
<obj_property name="ObjectShortName">current_hexa[3:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/compteur">
<obj_property name="ElementShortName">compteur</obj_property>
<obj_property name="ObjectShortName">compteur</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_ecran/instance_ScreenDriver/first_detected">
<obj_property name="ElementShortName">first_detected</obj_property>
<obj_property name="ObjectShortName">first_detected</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group159">
<obj_property name="label">Peripherique Clavier</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="group" fp_name="group160">
<obj_property name="label">Keyboard</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/PS2Clk">
<obj_property name="ElementShortName">PS2Clk</obj_property>
<obj_property name="ObjectShortName">PS2Clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/PS2Data">
<obj_property name="ElementShortName">PS2Data</obj_property>
<obj_property name="ObjectShortName">PS2Data</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data_read">
<obj_property name="ElementShortName">Data_read</obj_property>
<obj_property name="ObjectShortName">Data_read</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data_av">
<obj_property name="ElementShortName">Data_av</obj_property>
<obj_property name="ObjectShortName">Data_av</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/Data">
<obj_property name="ElementShortName">Data[0:6]</obj_property>
<obj_property name="ObjectShortName">Data[0:6]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_Keyboard/alert">
<obj_property name="ElementShortName">alert</obj_property>
<obj_property name="ObjectShortName">alert</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group161">
<obj_property name="label">KeyboardDriver</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/CLK">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data_read">
<obj_property name="ElementShortName">Data_read</obj_property>
<obj_property name="ObjectShortName">Data_read</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data_av">
<obj_property name="ElementShortName">Data_av</obj_property>
<obj_property name="ObjectShortName">Data_av</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/Data">
<obj_property name="ElementShortName">Data[0:6]</obj_property>
<obj_property name="ObjectShortName">Data[0:6]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN">
<obj_property name="ElementShortName">STD_IN[15:0]</obj_property>
<obj_property name="ObjectShortName">STD_IN[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN_Av">
<obj_property name="ElementShortName">STD_IN_Av</obj_property>
<obj_property name="ObjectShortName">STD_IN_Av</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_IN_Request">
<obj_property name="ElementShortName">STD_IN_Request</obj_property>
<obj_property name="ObjectShortName">STD_IN_Request</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_OUT">
<obj_property name="ElementShortName">STD_OUT[15:0]</obj_property>
<obj_property name="ObjectShortName">STD_OUT[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/STD_OUT_Av">
<obj_property name="ElementShortName">STD_OUT_Av</obj_property>
<obj_property name="ObjectShortName">STD_OUT_Av</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TestSystem/instance/instance_perif_clavier/instance_KeyboardDriver/intern_value">
<obj_property name="ElementShortName">intern_value</obj_property>
<obj_property name="ObjectShortName">intern_value</obj_property>
</wvobject>
</wvobject>
</wvobject>
</wave_config>

59
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg
View file

@ -11,14 +11,14 @@
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime> <ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="19120001fs"></ZoomEndTime> <ZoomEndTime time="79200001fs"></ZoomEndTime>
<Cursor1Time time="8460000fs"></Cursor1Time> <Cursor1Time time="50600000fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="146"></NameColumnWidth> <NameColumnWidth column_width="146"></NameColumnWidth>
<ValueColumnWidth column_width="193"></ValueColumnWidth> <ValueColumnWidth column_width="327"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="25" /> <WVObjectSize size="18" />
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_CLK"> <wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_CLK">
<obj_property name="ElementShortName">my_CLK</obj_property> <obj_property name="ElementShortName">my_CLK</obj_property>
<obj_property name="ObjectShortName">my_CLK</obj_property> <obj_property name="ObjectShortName">my_CLK</obj_property>
@ -31,6 +31,7 @@
<obj_property name="ElementShortName">my_IN_A[7:0]</obj_property> <obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property> <obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B"> <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
<obj_property name="ElementShortName">my_IN_B[7:0]</obj_property> <obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property> <obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
@ -79,56 +80,24 @@
<obj_property name="ObjectShortName">MEMORY[127:0]</obj_property> <obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property> <obj_property name="Radix">HEXRADIX</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Addr_MemoireDonnees"> <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">Addr_MemoireDonnees[3:0]</obj_property> <obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees[3:0]</obj_property> <obj_property name="ObjectShortName">RW</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/IN_Addr_MemoireDonnees">
<obj_property name="ElementShortName">IN_Addr_MemoireDonnees[3:0]</obj_property>
<obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Addr_MemoireDonnees_EBP">
<obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[3:0]</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr"> <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
<obj_property name="ElementShortName">Addr[3:0]</obj_property> <obj_property name="ElementShortName">Addr[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr[3:0]</obj_property> <obj_property name="ObjectShortName">Addr[3:0]</obj_property>
</wvobject> </wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">RW</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN"> <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property> <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property> <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
</wvobject> </wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RST"> <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/CALL">
<obj_property name="ElementShortName">RST</obj_property> <obj_property name="ElementShortName">CALL</obj_property>
<obj_property name="ObjectShortName">RST</obj_property> <obj_property name="ObjectShortName">CALL</obj_property>
</wvobject> </wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/CLK"> <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RET">
<obj_property name="ElementShortName">CLK</obj_property> <obj_property name="ElementShortName">RET</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property> <obj_property name="ObjectShortName">RET</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_OUT">
<obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
<obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
<obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
<obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Nb_bits">
<obj_property name="ElementShortName">Nb_bits</obj_property>
<obj_property name="ObjectShortName">Nb_bits</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr_size">
<obj_property name="ElementShortName">Addr_size</obj_property>
<obj_property name="ObjectShortName">Addr_size</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Mem_size">
<obj_property name="ElementShortName">Mem_size</obj_property>
<obj_property name="ObjectShortName">Mem_size</obj_property>
</wvobject> </wvobject>
</wave_config> </wave_config>

2
SimulationsConfig/Test_Pipeline_behav1.wcfg
View file

@ -30,12 +30,10 @@
<wvobject type="array" fp_name="/Test_Pipeline/my_STD_IN"> <wvobject type="array" fp_name="/Test_Pipeline/my_STD_IN">
<obj_property name="ElementShortName">my_STD_IN[7:0]</obj_property> <obj_property name="ElementShortName">my_STD_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">my_STD_IN[7:0]</obj_property> <obj_property name="ObjectShortName">my_STD_IN[7:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/my_STD_OUT"> <wvobject type="array" fp_name="/Test_Pipeline/my_STD_OUT">
<obj_property name="ElementShortName">my_STD_OUT[7:0]</obj_property> <obj_property name="ElementShortName">my_STD_OUT[7:0]</obj_property>
<obj_property name="ObjectShortName">my_STD_OUT[7:0]</obj_property> <obj_property name="ObjectShortName">my_STD_OUT[7:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject> </wvobject>
<wvobject type="other" fp_name="/Test_Pipeline/CLK_period"> <wvobject type="other" fp_name="/Test_Pipeline/CLK_period">
<obj_property name="ElementShortName">CLK_period</obj_property> <obj_property name="ElementShortName">CLK_period</obj_property>