49 lines
1.2 KiB
VHDL
49 lines
1.2 KiB
VHDL
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-- Company: INSA-Toulouse
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-- Engineer: Paul Faure
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--
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-- Create Date: 05.07.2021 15:20:28
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-- Module Name: Compteur_Y - Behavioral
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-- Project Name: Processeur sécurisé
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-- Target Devices: Basys 3 ARTIX7
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-- Tool Versions: Vivado 2016.4
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-- Description: Compteur la coordonnée Y du VGA
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--
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-- Dependencies:
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-- - None
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.ScreenProperties.all;
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entity Compteur_Y is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Value : out Y_T);
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end Compteur_Y;
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architecture Behavioral of Compteur_Y is
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signal current : Y_T := 0;
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begin
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process
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begin
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wait until CLK'event and CLK = '1';
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if (RST = '0') then
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current <= 0;
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else
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current <= current + 1;
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if (current = screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1) then
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current <= 0;
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end if;
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end if;
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end process;
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Value <= current;
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end Behavioral;
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