97 lines
No EOL
2.2 KiB
VHDL
97 lines
No EOL
2.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 05.07.2021 16:38:12
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-- Design Name:
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-- Module Name: Test_Compteur - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_Compteur is
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-- Port ( );
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end Test_Compteur;
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architecture Behavioral of Test_Compteur is
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constant screen_width : natural := 1280;
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constant screen_height : natural := 1040;
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subtype X_T is Natural range 0 to screen_width - 1;
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subtype Y_T is Natural range 0 to screen_height - 1;
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component Compteur_X is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Value : out X_T;
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Carry : out STD_LOGIC);
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end component;
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component Compteur_Y is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Value : out Y_T);
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end component;
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signal my_Carry : STD_LOGIC := '0';
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signal my_Value : X_T := 0;
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signal my_Value_Y : X_T := 0;
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signal my_CLK : STD_LOGIC := '0';
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signal my_RST : STD_LOGIC := '1';
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constant CLK_period : time := 10 ns;
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begin
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inst_Compteur_X : Compteur_X
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Port map ( CLK => my_CLK,
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RST => my_RST,
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Value => my_Value,
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Carry => my_Carry);
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inst_Compteur_Y : Compteur_Y
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Port map ( CLK => my_Carry,
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RST => my_RST,
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Value => my_Value_Y);
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CLK_process : process
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begin
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my_CLK <= '0';
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wait for CLK_period/2;
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my_CLK <= '1';
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wait for CLK_period/2;
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end process;
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process
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begin
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wait;
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end process;
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end Behavioral; |