Screen et Keyboard Okkkkkkkkk (enfin) (TAF : i ne s'affiche pas, bug DELETE, changer taille police, petits bugs affichage)

This commit is contained in:
Faure Paul 2021-07-07 20:22:32 +02:00
parent 0ad8e7fd55
commit 8fc5ea8d5f
23 changed files with 1367 additions and 387 deletions

View file

@ -61,11 +61,11 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
@ -108,8 +108,8 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN U18 [get_ports btnC]
# set_property IOSTANDARD LVCMOS33 [get_ports btnC]
##set_property PACKAGE_PIN T18 [get_ports btnU]
# #set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
@ -271,12 +271,12 @@ set_property PACKAGE_PIN R19 [get_ports Vsync]
##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
#set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
#set_property PULLUP true [get_ports PS2Data]
set_property PACKAGE_PIN C17 [get_ports PS2Clk]
set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
set_property PULLUP true [get_ports PS2Clk]
set_property PACKAGE_PIN B17 [get_ports PS2Data]
set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
set_property PULLUP true [get_ports PS2Data]
##Quad SPI Flash

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@ -40,12 +40,12 @@ end TestTableASCII;
architecture Behavioral of TestTableASCII is
component TableASCII is
port ( CodeASCII : in Natural;
Font : out font_T);
Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
end component;
signal my_CodeASCII : Natural := 0;
signal my_Font : font_T := (others => (others => '0'));
signal my_CodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000";
signal my_Font : STD_LOGIC_VECTOR (0 to 63) := (others => '0');
begin
@ -56,7 +56,7 @@ begin
process
begin
my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
my_CodeASCII <= "0000000" after 5 ns, "0000000" after 10 ns, "1000001" after 15 ns, "1000011" after 25 ns;
wait;
end process;

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@ -0,0 +1,97 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2021 16:38:12
-- Design Name:
-- Module Name: Test_Compteur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Compteur is
-- Port ( );
end Test_Compteur;
architecture Behavioral of Test_Compteur is
constant screen_width : natural := 1280;
constant screen_height : natural := 1040;
subtype X_T is Natural range 0 to screen_width - 1;
subtype Y_T is Natural range 0 to screen_height - 1;
component Compteur_X is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out X_T;
Carry : out STD_LOGIC);
end component;
component Compteur_Y is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Y_T);
end component;
signal my_Carry : STD_LOGIC := '0';
signal my_Value : X_T := 0;
signal my_Value_Y : X_T := 0;
signal my_CLK : STD_LOGIC := '0';
signal my_RST : STD_LOGIC := '1';
constant CLK_period : time := 10 ns;
begin
inst_Compteur_X : Compteur_X
Port map ( CLK => my_CLK,
RST => my_RST,
Value => my_Value,
Carry => my_Carry);
inst_Compteur_Y : Compteur_Y
Port map ( CLK => my_Carry,
RST => my_RST,
Value => my_Value_Y);
CLK_process : process
begin
my_CLK <= '0';
wait for CLK_period/2;
my_CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
wait;
end process;
end Behavioral;

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@ -38,18 +38,17 @@ end Test_Ecran;
architecture Behavioral of Test_Ecran is
component Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
CaracterHeight : Natural;
CaracterWidht : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (6 downto 0);
X : in Natural;
Y : in Natural;
OUT_ON : out STD_LOGIC_VECTOR (6 downto 0));
Generic ( HEIGHT : Natural;
WIDTH : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in Natural;
Y : in Natural;
OUT_ON : out STD_LOGIC);
end component;
@ -59,16 +58,14 @@ architecture Behavioral of Test_Ecran is
signal my_Data_IN : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_OUT_ON : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
signal my_OUT_ON : STD_LOGIC := '0';
constant CLK_period : time := 10 ns;
begin
instance : Ecran
generic map( HEIGHT => 14,
WIDTH => 22,
CaracterHeight => 4,
CaracterWidht => 5
generic map( HEIGHT => 50,
WIDTH => 68
)
port map( CLK => my_CLK,
RST => my_RST,

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@ -0,0 +1,93 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 08:21:55
-- Design Name:
-- Module Name: Test_Keyboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Keyboard is
-- Port ( );
end Test_Keyboard;
architecture Behavioral of Test_Keyboard is
component Keyboard is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal Data_read : STD_LOGIC := '0';
signal Data_av : STD_LOGIC := '0';
signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
signal alert : STD_LOGIC := '0';
constant CLK_period : TIME := 10 ns;
begin
CLK_process : process
begin
CLK <= '1';
wait for CLK_period/2;
CLK <= '0';
wait for CLK_period/2;
end process;
instance : Keyboard
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_read => Data_read,
Data_av => Data_av,
Data => Data,
alert => alert);
process
begin
PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
Data_read <= '1' after 3000 ns;
wait;
end process;
end Behavioral;

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@ -0,0 +1,88 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 08:21:55
-- Design Name:
-- Module Name: Test_KeyboardControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_KeyboardControler is
-- Port ( );
end Test_KeyboardControler;
architecture Behavioral of Test_KeyboardControler is
component KeyboardControler
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal Data_av : STD_LOGIC := '0';
signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
signal alert : STD_LOGIC := '0';
constant CLK_period : TIME := 10 ns;
begin
CLK_process : process
begin
CLK <= '1';
wait for CLK_period/2;
CLK <= '0';
wait for CLK_period/2;
end process;
instance : KeyboardControler
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_av => Data_av,
Data => Data,
alert => alert);
process
begin
PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
wait;
end process;
end Behavioral;

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@ -60,7 +60,7 @@ architecture Behavioral of Test_ScreenSystem is
signal my_btnC : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
constant CLK_period : time := 10 ns;
constant CLK_period : time := 9.26 ns;
begin
instance : ScreenSystem

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@ -0,0 +1,95 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.07.2021 18:57:39
-- Design Name:
-- Module Name: Test_SystemKeyboardScreen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_SystemKeyboardScreen is
-- Port ( );
end Test_SystemKeyboardScreen;
architecture Behavioral of Test_SystemKeyboardScreen is
component SystemKeyboardScreen
Port ( CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC := '0';
signal PS2Clk : STD_LOGIC := '0';
signal PS2Data : STD_LOGIC := '0';
signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal Hsync : STD_LOGIC := '0';
signal Vsync : STD_LOGIC := '0';
signal CLK_period : Time := 10 ns;
begin
instance : SystemKeyboardScreen
port map ( CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
vgaRed => vgaRed,
vgaGreen => vgaGreen,
vgaBlue => vgaBlue,
Hsync => Hsync,
Vsync => Vsync);
CLK_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
wait;
end process;
end Behavioral;

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@ -28,24 +28,37 @@ end Test_VGAControler;
architecture Behavioral of Test_VGAControler is
constant Display_CaracterWidht : Natural := 16;
constant Display_CaracterHeight : Natural := 16;
constant screen_width : natural := 1280;
constant screen_height : natural := 1024;
constant X_PulseWidth : Natural := 112;
constant X_FrontPorch : Natural := 48;
constant X_BackPorch : Natural := 248;
constant Y_PulseWidth : Natural := 3;
constant Y_FrontPorch : Natural := 1;
constant Y_BackPorch : Natural := 38;
subtype X_T is Natural range 0 to screen_width - 1;
subtype Y_T is Natural range 0 to screen_height - 1;
constant C_Blocks : Natural := screen_width/Display_CaracterWidht;
constant L_Blocks : Natural := screen_height/Display_CaracterHeight;
subtype L_T is Natural range 0 to L_Blocks - 1;
subtype C_T is Natural range 0 to C_Blocks - 1;
component VGAControler is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
X_PulseWidth : Natural;
X_FrontPorch : Natural;
X_BackPorch : Natural;
Y_PulseWidth : Natural;
Y_FrontPorch : Natural;
Y_BackPorch : Natural
);
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out Natural;
Y : out Natural;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
@ -59,8 +72,8 @@ architecture Behavioral of Test_VGAControler is
signal my_VGA_HS : STD_LOGIC := '0';
signal my_VGA_VS : STD_LOGIC := '0';
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_X : X_T := 0;
signal my_Y : Y_T := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal my_CLK : STD_LOGIC := '0';
@ -70,14 +83,6 @@ architecture Behavioral of Test_VGAControler is
begin
instance : VGAControler
generic map( HEIGHT => 4,
WIDTH =>10,
X_PulseWidth => 2,
X_FrontPorch => 1,
X_BackPorch => 3,
Y_PulseWidth => 1,
Y_FrontPorch => 1,
Y_BackPorch => 1)
port map( VGA_RED => my_VGA_RED,
VGA_BLUE => my_VGA_BLUE,
VGA_GREEN => my_VGA_GREEN,

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@ -2,9 +2,9 @@
-- Company:
-- Engineer:
--
-- Create Date: 28.06.2021 14:59:39
-- Create Date: 05.07.2021 15:20:28
-- Design Name:
-- Module Name: Compteur - Behavioral
-- Module Name: Compteur_X - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
@ -22,20 +22,19 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Compteur is
Generic (Min : Natural;
Max : Natural
);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Natural;
Carry : out STD_LOGIC);
end Compteur;
use work.ScreenProperties.all;
architecture Behavioral of Compteur is
entity Compteur_X is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out X_T;
Carry : out STD_LOGIC);
end Compteur_X;
signal current : Natural := Min;
signal InternCarry : STD_LOGIC := '0';
architecture Behavioral of Compteur_X is
signal current : X_T := 0;
signal intern_Carry : STD_LOGIC := '0';
begin
@ -43,19 +42,19 @@ begin
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
current <= Min;
current <= 0;
else
current <= current + 1;
if (current = Max) then
InternCarry <= '1';
current <= Min;
if (current = screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1) then
intern_Carry <= '1';
current <= 0;
else
InternCarry <= '0';
intern_Carry <= '0';
end if;
end if;
end process;
Value <= current;
Carry <= InternCarry;
Carry <= intern_Carry;
end Behavioral;
end Behavioral;

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@ -0,0 +1,54 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2021 15:20:28
-- Design Name:
-- Module Name: Compteur_Y - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
entity Compteur_Y is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Value : out Y_T);
end Compteur_Y;
architecture Behavioral of Compteur_Y is
signal current : Y_T := 0;
begin
process
begin
wait until CLK'event and CLK = '1';
if (RST = '0') then
current <= 0;
else
current <= current + 1;
if (current = screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1) then
current <= 0;
end if;
end if;
end process;
Value <= current;
end Behavioral;

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@ -21,48 +21,51 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.font.all;
use work.ScreenProperties.all;
entity Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in Natural;
X : in Natural;
Y : in Natural;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in X_T;
Y : in Y_T;
OUT_ON : out STD_LOGIC);
end Ecran;
architecture Behavioral of Ecran is
component TableASCII is
Port ( CodeASCII : Natural;
Font : out font_T);
Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
end component;
constant Flush : Natural := 0;
constant RetourChariot : Natural := 13;
constant CaracterHeight : Natural := 16;
constant CaracterWidht : Natural := 16;
constant HeightSize : Natural := HEIGHT/CaracterHeight;
constant WidthSize : Natural := WIDTH/CaracterWidht;
constant Flush : STD_LOGIC_VECTOR (0 to 6) := "0000000";
constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001101";
constant Delete : STD_LOGIC_VECTOR (0 to 6) := "1111111";
type T_Ligne is array (0 to WidthSize - 1) of Natural;
type T_Ecran is array (0 to HeightSize - 1) of T_Ligne;
signal Ecran : STD_LOGIC_VECTOR (0 to Ecran_Taille - 1) := (others => '0'); --(0 => '1', 1 => '0', 2 => '0', 3 => '1', 4 => '0', 5 => '0', 6 => '0', others => '0');
signal Ecran : T_Ecran := (others => (0 => 72, 1 => 101, 2 => 108, 3 => 108, 4 => 111, 5 => 32, 6 => 87, 7 => 111, 8 => 114, 9 => 108, 10 => 100, others => 0));
signal L : Natural := 0;
signal C : Natural := 0;
signal InitialL : Natural := 0;
signal Full : BOOLEAN := false;
signal L : STD_LOGIC_VECTOR (0 to 6) := "0000000";
signal L_inc : STD_LOGIC_VECTOR (0 to 6);
signal C : STD_LOGIC_VECTOR (0 to 6) := "0000000";
signal CurrentCodeASCII : Natural := 0;
signal CurrentFont : font_T;
signal InitialL : STD_LOGIC_VECTOR (0 to 6) := "0000000";
signal InitialL_inc : STD_LOGIC_VECTOR (0 to 6);
signal Full : STD_LOGIC := '0';
signal L_Lecture : L_T := 0;
signal point_dereferencement : Natural := 0;
signal point_dereferencement_ecriture : Natural := 0;
signal CurrentCodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000";
signal CurrentFont : STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1) := (others => '0');
begin
@ -74,45 +77,57 @@ begin
begin
wait until CLK'event and CLK='1';
if (RST = '0') then
Ecran <= (others => (others => 0));
L <= 0;
C <= 0;
InitialL <= 0;
Full <= false;
Ecran <= (others => '0');
L <= "0000000";
C <= "0000000";
InitialL <= "0000000";
Full <= '0';
elsif (Data_Av = '1') then
if (Data_IN = Flush) then
Ecran <= (others => (others => 0));
L <= 0;
C <= 0;
InitialL <= 0;
Full <= false;
Ecran <= (others => '0');
L <= "0000000";
C <= "0000000";
InitialL <= "0000000";
Full <= '0';
elsif (Data_IN = RetourChariot) then
C <= 0;
L <= (L + 1) mod HeightSize;
if ((L + 1) mod HeightSize = 0 or Full) then
Full <= true;
InitialL <= (InitialL + 1) mod HeightSize;
Ecran((L + 1) mod HeightSize) <= (others => 0);
end if;
C <= "0000000";
L <= L_inc;
if (L_inc = "0000000" or Full = '1') then
Full <= '1';
InitialL <= InitialL_inc;
Ecran(7 * C_Blocks * to_integer(unsigned(L_inc)) to 7 * C_Blocks * (to_integer(unsigned(L_inc)) + 1) - 1) <= Zero_Line;
end if;
elsif (Data_IN = Delete) then
if (C > 0) then
C <= C - 1;
Ecran(7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C))) to 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)) + 1) - 1) <= "0000000";
end if;
else
Ecran(L)(C) <= Data_IN;
Ecran(point_dereferencement_ecriture to point_dereferencement_ecriture + 6) <= Data_IN;
C <= C + 1;
if (C + 1 = WidthSize) then
C <= 0;
L <= (L + 1) mod HeightSize;
if ((L + 1) mod HeightSize = 0 or Full) then
Full <= true;
InitialL <= (InitialL + 1) mod HeightSize;
Ecran((L + 1) mod HeightSize) <= (others => 0);
if (C + 1 = C_Blocks) then
C <= "0000000";
L <= L_inc;
if (L_inc = 0 or Full = '1') then
Full <= '1';
InitialL <= InitialL_inc;
Ecran(7 * C_Blocks * to_integer(unsigned(L_inc)) to 7 * C_Blocks * (to_integer(unsigned(L_inc)) + 1) - 1) <= Zero_Line;
end if;
end if;
end if;
end if;
end process;
CurrentCodeASCII <= Ecran((Y/CaracterHeight + InitialL) mod HeightSize)(X/CaracterWidht) when (Y/CaracterHeight < HeightSize and X/CaracterWidht < WidthSize and RST='1') else
0;
L_inc <= "0000000" when L + 1 = L_Blocks else L + 1;
InitialL_inc <= "0000000" when InitialL + 1 = L_Blocks else InitialL + 1;
L_Lecture <= Y/Display_CaracterHeight + to_integer(unsigned(InitialL)) - L_Blocks when (Y/Display_CaracterHeight + to_integer(unsigned(InitialL))) >= L_Blocks else Y/Display_CaracterHeight + to_integer(unsigned(InitialL));
point_dereferencement <= (7 * (C_Blocks * L_Lecture + (X/Display_CaracterWidht)));
point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)));
CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y/Display_CaracterHeight < L_Blocks and X/Display_CaracterWidht < C_Blocks and RST='1') else
"0000000";
OUT_ON <= CurrentFont((Y mod CaracterHeight) / (CaracterHeight / font_height), (X mod CaracterWidht) / (CaracterWidht / font_width));
OUT_ON <= CurrentFont(((Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width));
end Behavioral;

View file

@ -0,0 +1,104 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.07.2021 09:09:30
-- Design Name:
-- Module Name: Keyboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Keyboard is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 6);
alert : out STD_LOGIC);
end Keyboard;
architecture Behavioral of Keyboard is
component KeyboardControler
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end component;
component KeyboardToASCII
Port ( KeyCode : in STD_LOGIC_VECTOR (0 to 7);
CodeASCII : out STD_LOGIC_VECTOR (0 to 6));
end component;
signal buffer_Data : STD_LOGIC_VECTOR (0 to 7);
signal keyboardControleur_Data_av : STD_LOGIC;
signal intern_Data_av : STD_LOGIC := '0';
signal intern_Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
begin
instance_KeyboardControler : KeyboardControler
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_av => keyboardControleur_Data_av,
Data => buffer_Data,
alert => alert);
instance_KeyboardToASCII : KeyboardToASCII
port map ( KeyCode => buffer_Data,
CodeASCII => intern_Data);
process
begin
wait until CLK'event and CLK = '1';
if (intern_Data_av = '0') then
if (keyboardControleur_Data_av = '1') then
Data <= intern_Data;
intern_Data_av <= '1';
end if;
elsif (Data_read = '1') then
intern_Data_av <= '0';
end if;
end process;
Data_av <= intern_Data_av;
end Behavioral;

View file

@ -0,0 +1,126 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.07.2021 09:09:30
-- Design Name:
-- Module Name: KeyboardControler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity KeyboardControler is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 7);
alert : out STD_LOGIC);
end KeyboardControler;
architecture Behavioral of KeyboardControler is
subtype compteur_T is Natural range 0 to 10;
signal compteur : compteur_T := 0;
signal current_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
signal previous_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
signal parity : STD_LOGIC := '0';
signal intern_alert : STD_LOGIC := '0';
signal intern_Data_av : STD_LOGIC := '0';
signal dejaSignale : boolean := false;
begin
process
begin
wait until PS2Clk'event and PS2Clk = '1';
case compteur is
when 0 =>
parity <= '1';
intern_alert <= '0';
intern_Data_av <= '0';
when 1 =>
current_data(7) <= PS2Data;
parity <= parity XOR PS2Data;
when 2 =>
current_data(6) <= PS2Data;
parity <= parity XOR PS2Data;
when 3 =>
current_data(5) <= PS2Data;
parity <= parity XOR PS2Data;
when 4 =>
current_data(4) <= PS2Data;
parity <= parity XOR PS2Data;
when 5 =>
current_data(3) <= PS2Data;
parity <= parity XOR PS2Data;
when 6 =>
current_data(2) <= PS2Data;
parity <= parity XOR PS2Data;
when 7 =>
current_data(1) <= PS2Data;
parity <= parity XOR PS2Data;
when 8 =>
current_data(0) <= PS2Data;
parity <= parity XOR PS2Data;
when 9 =>
if (parity = PS2Data) then
intern_alert <= '0';
else
intern_alert <= '1';
end if;
when 10 =>
if (intern_alert = '0') then
previous_data <= current_data;
if (not (previous_data = "11110000" or current_data = "11110000" or previous_data = "11100000")) then
Data <= current_data;
intern_Data_av <= '1';
end if;
end if;
end case;
compteur <= (compteur + 1) mod 11;
end process;
process
begin
wait until CLK'event and CLK = '1';
if (intern_Data_av = '1' and not dejaSignale) then
Data_av <= '1';
dejaSignale <= true;
else
Data_av <= '0';
end if;
if (intern_Data_av = '0') then
dejaSignale <= false;
end if;
end process;
alert <= intern_alert;
end Behavioral;

View file

@ -0,0 +1,75 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.07.2021 10:43:18
-- Design Name:
-- Module Name: KeyboardToASCII - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity KeyboardToASCII is
Port ( KeyCode : in STD_LOGIC_VECTOR (0 to 7);
CodeASCII : out STD_LOGIC_VECTOR (0 to 6));
end KeyboardToASCII;
architecture Behavioral of KeyboardToASCII is
begin
CodeASCII <= "0000000" when (KeyCode = x"05") else -- F1 -> flush
"0001101" when (KeyCode = x"5a") else -- Enter
"1111111" when (KeyCode = x"66") else -- Del
"1000001" when (KeyCode = x"15") else -- A
"1000010" when (KeyCode = x"32") else -- B
"1000011" when (KeyCode = x"21") else -- C
"1000100" when (KeyCode = x"23") else -- D
"1000101" when (KeyCode = x"24") else -- E
"1000110" when (KeyCode = x"2b") else -- F
"1000111" when (KeyCode = x"34") else -- G
"1001000" when (KeyCode = x"33") else -- H
"1001001" when (KeyCode = x"83") else -- I
"1001010" when (KeyCode = x"3b") else -- J
"1001011" when (KeyCode = x"42") else -- K
"1001100" when (KeyCode = x"4b") else -- L
"1001101" when (KeyCode = x"4c") else -- M
"1001110" when (KeyCode = x"31") else -- N
"1001111" when (KeyCode = x"44") else -- O
"1010000" when (KeyCode = x"4d") else -- P
"1010001" when (KeyCode = x"1c") else -- Q
"1010010" when (KeyCode = x"2d") else -- R
"1010011" when (KeyCode = x"1b") else -- S
"1010100" when (KeyCode = x"2c") else -- T
"1010101" when (KeyCode = x"3c") else -- U
"1010110" when (KeyCode = x"2a") else -- V
"1010111" when (KeyCode = x"1a") else -- W
"1011000" when (KeyCode = x"22") else -- X
"1011001" when (KeyCode = x"35") else -- Y
"1011010" when (KeyCode = x"1d") else -- Z
"0110000" when (KeyCode = x"70") else -- 0
"0110001" when (KeyCode = x"69") else -- 1
"0110010" when (KeyCode = x"72") else -- 2
"0110011" when (KeyCode = x"7a") else -- 3
"0110100" when (KeyCode = x"6b") else -- 4
"0110101" when (KeyCode = x"73") else -- 5
"0110110" when (KeyCode = x"74") else -- 6
"0110111" when (KeyCode = x"6c") else -- 7
"0111000" when (KeyCode = x"75") else -- 8
"0111001" when (KeyCode = x"7d") else -- 9
"0000001"; -- Rien
end Behavioral;

View file

@ -0,0 +1,33 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package ScreenProperties is
constant Display_CaracterWidht : Natural := 64;
constant Display_CaracterHeight : Natural := 64;
constant screen_width : natural := 1280;
constant screen_height : natural := 1024;
constant X_PulseWidth : Natural := 112;
constant X_FrontPorch : Natural := 48;
constant X_BackPorch : Natural := 248;
constant Y_PulseWidth : Natural := 3;
constant Y_FrontPorch : Natural := 1;
constant Y_BackPorch : Natural := 38;
subtype X_T is Natural range 0 to screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1;
subtype Y_T is Natural range 0 to screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1;
constant C_Blocks : Natural := screen_width/Display_CaracterWidht;
constant L_Blocks : Natural := screen_height/Display_CaracterHeight;
constant Ecran_Taille : Natural := C_Blocks * L_Blocks * 7;
constant L_Size : Natural := C_Blocks * 7;
constant Zero_Line : STD_LOGIC_VECTOR (0 to L_Size - 1) := (others => '0');
subtype L_T is Natural range 0 to L_Blocks - 1;
subtype C_T is Natural range 0 to C_Blocks - 1;
end package;

View file

@ -22,6 +22,8 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ScreenProperties.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
@ -47,23 +49,14 @@ end ScreenSystem;
architecture Behavioral of ScreenSystem is
component VGAControler is
Generic ( HEIGHT : Natural;
WIDTH : Natural;
X_PulseWidth : Natural;
X_FrontPorch : Natural;
X_BackPorch : Natural;
Y_PulseWidth : Natural;
Y_FrontPorch : Natural;
Y_BackPorch : Natural
);
Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
X : out Natural;
Y : out Natural;
X : out X_T;
Y : out Y_T;
PIXEL_ON : in STD_LOGIC;
CLK : in STD_LOGIC;
@ -80,45 +73,25 @@ architecture Behavioral of ScreenSystem is
end component;
component Ecran is
Generic ( HEIGHT : Natural;
WIDTH : Natural
);
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Data_Av : in STD_LOGIC;
Data_IN : in Natural;
X : in Natural;
Y : in Natural;
Data_IN : in STD_LOGIC_VECTOR (0 to 6);
X : in X_T;
Y : in Y_T;
OUT_ON : out STD_LOGIC);
end component;
signal my_X : Natural := 0;
signal my_Y : Natural := 0;
signal my_X : X_T := 0;
signal my_Y : Y_T := 0;
signal my_PIXEL_ON : STD_LOGIC := '0';
signal compteur : natural := 0;
signal my_CLK : STD_LOGIC := '0';
signal RST : STD_LOGIC;
begin
instanceVGA : VGAControler
-- generic map( HEIGHT => 480,
-- WIDTH => 640,
-- X_PulseWidth => 96,
-- X_FrontPorch => 16,
-- X_BackPorch => 48,
-- Y_PulseWidth => 2,
-- Y_FrontPorch => 10,
-- Y_BackPorch => 33)
generic map( HEIGHT => 1024,
WIDTH => 1280,
X_PulseWidth => 112,
X_FrontPorch => 48,
X_BackPorch => 248,
Y_PulseWidth => 3,
Y_FrontPorch => 1,
Y_BackPorch => 38)
port map( VGA_RED => vgaRed,
VGA_BLUE => vgaBlue,
VGA_GREEN => vgaGreen,
@ -138,26 +111,13 @@ begin
clk_in1 => CLK,
clk_out1 => my_CLK
);
-- process
-- begin
-- wait until CLK'event and CLK = '1';
-- compteur <= (compteur + 1) mod 4;
-- if (compteur = 0) then
-- my_CLK <= '1';
-- elsif (compteur = 2) then
-- my_CLK <= '0';
-- end if;
-- end process;
instance_Ecran : Ecran
generic map ( HEIGHT => 1024,
WIDTH => 1280
)
port map ( CLK => CLK,
RST => RST,
Data_Av => '0',
Data_IN => 0,
Data_IN => "0000000",
X => my_X,
Y => my_Y,
OUT_ON => my_PIXEL_ON);

View file

@ -0,0 +1,95 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.07.2021 13:37:43
-- Design Name:
-- Module Name: SystemKeyboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SystemKeyboard is
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (0 to 10);
btnC : in STD_LOGIC);
end SystemKeyboard;
architecture Behavioral of SystemKeyboard is
component Keyboard
Port (CLK : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
Data_read : in STD_LOGIC;
Data_av : out STD_LOGIC;
Data : out STD_LOGIC_VECTOR (0 to 6);
alert : out STD_LOGIC);
end component;
signal intern_Data_read : STD_LOGIC := '0';
signal intern_Data_av : STD_LOGIC := '0';
signal Data_Read : STD_LOGIC_VECTOR (0 to 6);
begin
instance_Keyboard : Keyboard
port map (CLK => CLK,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
Data_read => intern_Data_read,
Data_av => intern_Data_av,
Data => Data_Read,
alert => led(10));
led(7) <= '0';
led(8) <= intern_Data_av;
led(9) <= intern_Data_read;
process
begin
wait until CLK'event and CLK = '1';
if (intern_Data_av = '1' and btnC = '1') then
led(0 to 6) <= Data_read;
intern_Data_read <= '1';
else