Browse Source

Screen et Keyboard Okkkkkkkkk (enfin) (TAF : i ne s'affiche pas, bug DELETE, changer taille police, petits bugs affichage)

Faure Paul 2 months ago
parent
commit
8fc5ea8d5f

+ 11
- 11
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -61,11 +61,11 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
61 61
 #set_property PACKAGE_PIN V14 [get_ports {led[7]}]
62 62
 #	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
63 63
 #set_property PACKAGE_PIN V13 [get_ports {led[8]}]
64
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
64
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
65 65
 #set_property PACKAGE_PIN V3 [get_ports {led[9]}]
66
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
66
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
67 67
 #set_property PACKAGE_PIN W3 [get_ports {led[10]}]
68
-	#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
68
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69 69
 #set_property PACKAGE_PIN U3 [get_ports {led[11]}]
70 70
 	#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
71 71
 #set_property PACKAGE_PIN P3 [get_ports {flag[0]}]
@@ -108,8 +108,8 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
108 108
 
109 109
 
110 110
 ##Buttons
111
-set_property PACKAGE_PIN U18 [get_ports btnC]
112
-	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
111
+#set_property PACKAGE_PIN U18 [get_ports btnC]
112
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
113 113
 ##set_property PACKAGE_PIN T18 [get_ports btnU]
114 114
 #	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115 115
 #set_property PACKAGE_PIN W19 [get_ports btnL]
@@ -271,12 +271,12 @@ set_property PACKAGE_PIN R19 [get_ports Vsync]
271 271
 
272 272
 
273 273
 ##USB HID (PS/2)
274
-#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
275
-	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
276
-	#set_property PULLUP true [get_ports PS2Clk]
277
-#set_property PACKAGE_PIN B17 [get_ports PS2Data]
278
-	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
279
-	#set_property PULLUP true [get_ports PS2Data]
274
+set_property PACKAGE_PIN C17 [get_ports PS2Clk]
275
+	set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
276
+	set_property PULLUP true [get_ports PS2Clk]
277
+set_property PACKAGE_PIN B17 [get_ports PS2Data]
278
+	set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
279
+	set_property PULLUP true [get_ports PS2Data]
280 280
 
281 281
 
282 282
 ##Quad SPI Flash

+ 5
- 5
Processeur.srcs/sim_1/new/TestTableASCII.vhd View File

@@ -40,12 +40,12 @@ end TestTableASCII;
40 40
 architecture Behavioral of TestTableASCII is
41 41
 
42 42
     component TableASCII is
43
-    port ( CodeASCII : in Natural;
44
-           Font  : out font_T);
43
+    Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
44
+           Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
45 45
     end component;
46 46
 
47
-    signal my_CodeASCII : Natural := 0;
48
-    signal my_Font      : font_T := (others => (others => '0'));
47
+    signal my_CodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000";
48
+    signal my_Font      : STD_LOGIC_VECTOR (0 to 63) := (others => '0');
49 49
     
50 50
 begin
51 51
 
@@ -56,7 +56,7 @@ begin
56 56
     
57 57
     process 
58 58
     begin   
59
-        my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
59
+        my_CodeASCII <= "0000000" after 5 ns, "0000000" after 10 ns, "1000001" after 15 ns, "1000011" after 25 ns;
60 60
         wait;
61 61
     end process;  
62 62
 

+ 97
- 0
Processeur.srcs/sim_1/new/Test_Compteur.vhd View File

@@ -0,0 +1,97 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 05.07.2021 16:38:12
6
+-- Design Name: 
7
+-- Module Name: Test_Compteur - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+
26
+
27
+
28
+-- Uncomment the following library declaration if using
29
+-- arithmetic functions with Signed or Unsigned values
30
+--use IEEE.NUMERIC_STD.ALL;
31
+
32
+-- Uncomment the following library declaration if instantiating
33
+-- any Xilinx leaf cells in this code.
34
+--library UNISIM;
35
+--use UNISIM.VComponents.all;
36
+
37
+entity Test_Compteur is
38
+--  Port ( );
39
+end Test_Compteur;
40
+
41
+architecture Behavioral of Test_Compteur is
42
+
43
+    constant screen_width   : natural := 1280;
44
+    constant screen_height  : natural := 1040;
45
+        
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+    subtype X_T is Natural range 0 to screen_width - 1;
47
+    subtype Y_T is Natural range 0 to screen_height - 1;
48
+
49
+    component Compteur_X is
50
+    Port ( CLK : in STD_LOGIC;
51
+           RST : in STD_LOGIC;
52
+           Value : out X_T;
53
+           Carry : out STD_LOGIC);
54
+    end component;
55
+    
56
+    component Compteur_Y is
57
+    Port ( CLK : in STD_LOGIC;
58
+           RST : in STD_LOGIC;
59
+           Value : out Y_T);
60
+    end component;
61
+   
62
+    signal my_Carry : STD_LOGIC := '0';
63
+    signal my_Value : X_T := 0;
64
+    signal my_Value_Y : X_T := 0;
65
+   
66
+    signal my_CLK       : STD_LOGIC := '0';
67
+    signal my_RST       : STD_LOGIC := '1';
68
+    
69
+    constant CLK_period : time := 10 ns;
70
+
71
+begin
72
+
73
+    inst_Compteur_X : Compteur_X 
74
+    Port map ( CLK => my_CLK,
75
+               RST => my_RST,
76
+               Value => my_Value,
77
+               Carry => my_Carry);
78
+               
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+    inst_Compteur_Y : Compteur_Y 
80
+    Port map ( CLK => my_Carry,
81
+               RST => my_RST,
82
+               Value => my_Value_Y);
83
+
84
+    CLK_process : process
85
+    begin
86
+        my_CLK <= '0';
87
+        wait for CLK_period/2;
88
+        my_CLK <= '1';
89
+        wait for CLK_period/2;
90
+    end process;
91
+
92
+    process 
93
+    begin   
94
+        wait;
95
+    end process;  
96
+      
97
+end Behavioral;

+ 14
- 17
Processeur.srcs/sim_1/new/Test_Ecran.vhd View File

@@ -38,18 +38,17 @@ end Test_Ecran;
38 38
 architecture Behavioral of Test_Ecran is
39 39
 
40 40
     component Ecran is
41
-    Generic (  HEIGHT         : Natural;
42
-               WIDTH          : Natural;
43
-               CaracterHeight : Natural;
44
-               CaracterWidht  : Natural            
45
-    );
46
-    Port (     CLK            : in STD_LOGIC;
47
-               RST            : in STD_LOGIC;
48
-               Data_Av        : in STD_LOGIC;
49
-               Data_IN        : in STD_LOGIC_VECTOR (6 downto 0);
50
-               X              : in Natural;
51
-               Y              : in Natural;
52
-               OUT_ON         : out STD_LOGIC_VECTOR (6 downto 0));
41
+        Generic (  HEIGHT         : Natural;
42
+                   WIDTH          : Natural        
43
+        );
44
+        Port (     CLK            : in STD_LOGIC;
45
+                   RST            : in STD_LOGIC;
46
+                   Data_Av        : in STD_LOGIC;
47
+                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
48
+                   
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+                   X              : in Natural;
50
+                   Y              : in Natural;
51
+                   OUT_ON         : out STD_LOGIC);
53 52
     end component; 
54 53
     
55 54
     
@@ -59,16 +58,14 @@ architecture Behavioral of Test_Ecran is
59 58
     signal my_Data_IN : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
60 59
     signal my_X : Natural := 0;
61 60
     signal my_Y : Natural := 0;
62
-    signal my_OUT_ON : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
61
+    signal my_OUT_ON : STD_LOGIC := '0';
63 62
     
64 63
     constant CLK_period : time := 10 ns;
65 64
 
66 65
 begin
67 66
     instance : Ecran 
68
-    generic map(  HEIGHT => 14,
69
-                  WIDTH => 22,
70
-                  CaracterHeight => 4,
71
-                  CaracterWidht => 5          
67
+    generic map(  HEIGHT => 50,
68
+                  WIDTH => 68   
72 69
     )
73 70
     port map(  CLK => my_CLK,
74 71
                RST => my_RST,

+ 93
- 0
Processeur.srcs/sim_1/new/Test_Keyboard.vhd View File

@@ -0,0 +1,93 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 02.07.2021 08:21:55
6
+-- Design Name: 
7
+-- Module Name: Test_Keyboard - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Keyboard is
35
+--  Port ( );
36
+end Test_Keyboard;
37
+
38
+architecture Behavioral of Test_Keyboard is
39
+
40
+    component Keyboard is
41
+    Port (CLK : in STD_LOGIC;
42
+  
43
+          PS2Clk : in STD_LOGIC;
44
+          PS2Data : in STD_LOGIC;
45
+        
46
+          Data_read : in STD_LOGIC;
47
+          Data_av : out STD_LOGIC;
48
+          Data : out STD_LOGIC_VECTOR (0 to 7);
49
+        
50
+          alert : out STD_LOGIC);
51
+    end component;
52
+    
53
+    signal CLK : STD_LOGIC := '0';
54
+    signal PS2Clk : STD_LOGIC := '0';
55
+    signal PS2Data : STD_LOGIC := '0';
56
+    signal Data_read : STD_LOGIC := '0';
57
+    signal Data_av : STD_LOGIC := '0';
58
+    signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
59
+    signal alert : STD_LOGIC := '0';
60
+    
61
+    constant CLK_period : TIME := 10 ns;
62
+
63
+begin
64
+
65
+    CLK_process : process
66
+    begin
67
+        CLK <= '1';
68
+        wait for CLK_period/2;
69
+        CLK <= '0';
70
+        wait for CLK_period/2;
71
+    end process;
72
+
73
+    instance : Keyboard
74
+    port map (CLK => CLK,
75
+          
76
+              PS2Clk => PS2Clk,
77
+              PS2Data => PS2Data, 
78
+            
79
+              Data_read => Data_read,
80
+              Data_av => Data_av,
81
+              Data => Data,
82
+            
83
+              alert => alert);
84
+              
85
+    process
86
+    begin
87
+        PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
88
+        PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
89
+        Data_read <= '1' after 3000 ns;
90
+        wait;
91
+    end process; 
92
+
93
+end Behavioral;

+ 88
- 0
Processeur.srcs/sim_1/new/Test_KeyboardControler.vhd View File

@@ -0,0 +1,88 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 02.07.2021 08:21:55
6
+-- Design Name: 
7
+-- Module Name: Test_KeyboardControler - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_KeyboardControler is
35
+--  Port ( );
36
+end Test_KeyboardControler;
37
+
38
+architecture Behavioral of Test_KeyboardControler is
39
+
40
+    component KeyboardControler
41
+      Port (CLK : in STD_LOGIC;
42
+      
43
+            PS2Clk : in STD_LOGIC;
44
+            PS2Data : in STD_LOGIC;
45
+            
46
+            Data_av : out STD_LOGIC;
47
+            Data : out STD_LOGIC_VECTOR (0 to 7);
48
+            
49
+            alert : out STD_LOGIC);
50
+    end component;
51
+    
52
+    signal CLK : STD_LOGIC := '0';
53
+    signal PS2Clk : STD_LOGIC := '0';
54
+    signal PS2Data : STD_LOGIC := '0';
55
+    signal Data_av : STD_LOGIC := '0';
56
+    signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
57
+    signal alert : STD_LOGIC := '0';
58
+    
59
+    constant CLK_period : TIME := 10 ns;
60
+    
61
+begin
62
+
63
+    CLK_process : process
64
+    begin
65
+        CLK <= '1';
66
+        wait for CLK_period/2;
67
+        CLK <= '0';
68
+        wait for CLK_period/2;
69
+    end process;
70
+
71
+    instance : KeyboardControler
72
+    port map (CLK => CLK,
73
+          
74
+              PS2Clk => PS2Clk,
75
+              PS2Data => PS2Data, 
76
+            
77
+              Data_av => Data_av,
78
+              Data => Data,
79
+            
80
+              alert => alert);
81
+              
82
+    process
83
+    begin
84
+        PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
85
+        PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
86
+        wait;
87
+    end process; 
88
+end Behavioral;

+ 1
- 1
Processeur.srcs/sim_1/new/Test_ScreenSystem.vhd View File

@@ -60,7 +60,7 @@ architecture Behavioral of Test_ScreenSystem is
60 60
     signal my_btnC : STD_LOGIC := '0';
61 61
     signal my_CLK  : STD_LOGIC := '0';
62 62
 
63
-    constant CLK_period : time := 10 ns;
63
+    constant CLK_period : time := 9.26 ns;
64 64
 
65 65
 begin
66 66
     instance : ScreenSystem

+ 95
- 0
Processeur.srcs/sim_1/new/Test_SystemKeyboardScreen.vhd View File

@@ -0,0 +1,95 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 07.07.2021 18:57:39
6
+-- Design Name: 
7
+-- Module Name: Test_SystemKeyboardScreen - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_SystemKeyboardScreen is
35
+--  Port ( );
36
+end Test_SystemKeyboardScreen;
37
+
38
+architecture Behavioral of Test_SystemKeyboardScreen is
39
+
40
+    component SystemKeyboardScreen
41
+    Port ( CLK : in STD_LOGIC;
42
+    
43
+           PS2Clk : in STD_LOGIC;
44
+           PS2Data : in STD_LOGIC;
45
+           
46
+           vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
47
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
48
+           vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
49
+           Hsync : out STD_LOGIC;
50
+           Vsync : out STD_LOGIC);
51
+    end component;
52
+
53
+    signal CLK : STD_LOGIC := '0';
54
+    
55
+    signal PS2Clk : STD_LOGIC := '0';
56
+    signal PS2Data : STD_LOGIC := '0';
57
+    
58
+    signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
59
+    signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
60
+    signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
61
+    signal Hsync : STD_LOGIC := '0';
62
+    signal Vsync : STD_LOGIC := '0';
63
+    
64
+    signal CLK_period : Time := 10 ns;
65
+
66
+begin
67
+
68
+    instance : SystemKeyboardScreen
69
+    port map ( CLK => CLK,
70
+    
71
+               PS2Clk => PS2Clk,
72
+               PS2Data => PS2Data,
73
+               
74
+               vgaRed => vgaRed,
75
+               vgaGreen => vgaGreen,
76
+               vgaBlue => vgaBlue,
77
+               Hsync => Hsync,
78
+               Vsync => Vsync);
79
+
80
+    CLK_process : process
81
+    begin
82
+        CLK <= '0';
83
+        wait for CLK_period/2;
84
+        CLK <= '1';
85
+        wait for CLK_period/2;
86
+    end process;
87
+    
88
+    process 
89
+    begin   
90
+        PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
91
+        PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
92
+        wait;
93
+    end process;  
94
+
95
+end Behavioral;

+ 26
- 21
Processeur.srcs/sim_1/new/Test_VGAControler.vhd View File

@@ -28,24 +28,37 @@ end Test_VGAControler;
28 28
 
29 29
 architecture Behavioral of Test_VGAControler is
30 30
 
31
+    constant Display_CaracterWidht  : Natural := 16;
32
+    constant Display_CaracterHeight : Natural := 16;
33
+
34
+    constant screen_width   : natural := 1280;
35
+    constant screen_height  : natural := 1024;
36
+    
37
+    constant X_PulseWidth : Natural := 112;
38
+    constant X_FrontPorch : Natural := 48;
39
+    constant X_BackPorch  : Natural := 248;
40
+    constant Y_PulseWidth : Natural := 3;
41
+    constant Y_FrontPorch : Natural := 1;
42
+    constant Y_BackPorch  : Natural := 38;
43
+        
44
+    subtype X_T is Natural range 0 to screen_width - 1;
45
+    subtype Y_T is Natural range 0 to screen_height - 1;
46
+    
47
+    constant C_Blocks : Natural := screen_width/Display_CaracterWidht;
48
+    constant L_Blocks : Natural := screen_height/Display_CaracterHeight;
49
+    
50
+    subtype L_T is Natural range 0 to L_Blocks - 1;
51
+    subtype C_T is Natural range 0 to C_Blocks - 1;
52
+
31 53
     component VGAControler is
32
-    Generic (  HEIGHT    : Natural;
33
-               WIDTH     : Natural;
34
-               X_PulseWidth : Natural;
35
-               X_FrontPorch : Natural;
36
-               X_BackPorch  : Natural;
37
-               Y_PulseWidth : Natural;
38
-               Y_FrontPorch : Natural;
39
-               Y_BackPorch  : Natural              
40
-    );
41 54
     Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
42 55
                VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
43 56
                VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
44 57
                VGA_HS    : out STD_LOGIC;
45 58
                VGA_VS    : out STD_LOGIC;
46 59
                
47
-               X         : out Natural;
48
-               Y         : out Natural;
60
+               X         : out X_T;
61
+               Y         : out Y_T;
49 62
                PIXEL_ON  : in STD_LOGIC;
50 63
                
51 64
                CLK       : in STD_LOGIC;
@@ -59,8 +72,8 @@ architecture Behavioral of Test_VGAControler is
59 72
     signal my_VGA_HS    : STD_LOGIC := '0';
60 73
     signal my_VGA_VS    : STD_LOGIC := '0';
61 74
    
62
-    signal my_X         : Natural := 0;
63
-    signal my_Y         : Natural := 0;
75
+    signal my_X         : X_T := 0;
76
+    signal my_Y         : Y_T := 0;
64 77
     signal my_PIXEL_ON  : STD_LOGIC := '0';
65 78
    
66 79
     signal my_CLK       : STD_LOGIC := '0';
@@ -70,14 +83,6 @@ architecture Behavioral of Test_VGAControler is
70 83
 
71 84
 begin
72 85
     instance : VGAControler 
73
-    generic map(  HEIGHT => 4,
74
-                  WIDTH =>10,
75
-                  X_PulseWidth => 2,
76
-                  X_FrontPorch => 1,
77
-                  X_BackPorch  => 3,
78
-                  Y_PulseWidth => 1,
79
-                  Y_FrontPorch => 1,
80
-                  Y_BackPorch  => 1)
81 86
     port map(  VGA_RED   => my_VGA_RED,
82 87
                VGA_BLUE  => my_VGA_BLUE,
83 88
                VGA_GREEN => my_VGA_GREEN,

Processeur.srcs/sources_1/new/Compteur.vhd → Processeur.srcs/sources_1/new/Compteur_X.vhd View File

@@ -2,9 +2,9 @@
2 2
 -- Company: 
3 3
 -- Engineer: 
4 4
 -- 
5
+-- Create Date: 05.07.2021 15:20:28
5 6
 -- Design Name: 
7
+-- Module Name: Compteur_X - Behavioral
6 8
 -- Project Name: 
7 9
 -- Target Devices: 
8 10
 -- Tool Versions: 
@@ -22,20 +22,19 @@
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24 24
 
25
-entity Compteur is
26
-    Generic (Min : Natural;
27
-             Max : Natural
28
-            );
29
-    Port    (CLK : in STD_LOGIC;
30
-             RST : in STD_LOGIC;
31
-             Value : out Natural;
32
-             Carry : out STD_LOGIC);
33
-end Compteur;
25
+use work.ScreenProperties.all;
34 26
 
35
-architecture Behavioral of Compteur is
27
+entity Compteur_X is
28
+    Port ( CLK : in STD_LOGIC;
29
+           RST : in STD_LOGIC;
30
+           Value : out X_T;
31
+           Carry : out STD_LOGIC);
32
+end Compteur_X;
36 33
 
37
-    signal current : Natural := Min;
38
-    signal InternCarry : STD_LOGIC := '0';
34
+architecture Behavioral of Compteur_X is
35
+
36
+signal current : X_T := 0;
37
+signal intern_Carry : STD_LOGIC := '0';
39 38
     
40 39
 begin
41 40
 
@@ -43,19 +42,19 @@ begin
43 42
     begin
44 43
         wait until CLK'event and CLK = '1';
45 44
         if (RST = '0') then
46
-            current <= Min;
45
+            current <= 0;
47 46
         else 
48 47
             current <= current + 1;
49
-            if (current = Max) then
50
-                InternCarry <= '1'; 
51
-                current <= Min;
48
+            if (current = screen_width + X_PulseWidth + X_FrontPorch + X_BackPorch - 1) then
49
+                intern_Carry <= '1'; 
50
+                current <= 0;
52 51
             else 
53
-                InternCarry <= '0';
52
+                intern_Carry <= '0';
54 53
             end if;
55 54
         end if;
56 55
     end process;
57 56
     
58 57
     Value <= current;
59
-    Carry <= InternCarry;
58
+    Carry <= intern_Carry;
60 59
     
61
-end Behavioral;
60
+end Behavioral;

+ 54
- 0
Processeur.srcs/sources_1/new/Compteur_Y.vhd View File

@@ -0,0 +1,54 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 05.07.2021 15:20:28
6
+-- Design Name: 
7
+-- Module Name: Compteur_Y - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+use work.ScreenProperties.all;
26
+
27
+entity Compteur_Y is
28
+    Port ( CLK : in STD_LOGIC;
29
+           RST : in STD_LOGIC;
30
+           Value : out Y_T);
31
+end Compteur_Y;
32
+
33
+architecture Behavioral of Compteur_Y is
34
+
35
+signal current : Y_T := 0;
36
+    
37
+begin
38
+
39
+    process
40
+    begin
41
+        wait until CLK'event and CLK = '1';
42
+        if (RST = '0') then
43
+            current <= 0;
44
+        else 
45
+            current <= current + 1;
46
+            if (current = screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1) then
47
+                current <= 0;
48
+            end if;
49
+        end if;
50
+    end process;
51
+    
52
+    Value <= current;
53
+    
54
+end Behavioral;

+ 67
- 52
Processeur.srcs/sources_1/new/Ecran.vhd View File

@@ -21,48 +21,51 @@
21 21
 
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+use IEEE.NUMERIC_STD.ALL;
24 26
 
25 27
 use work.font.all;
28
+use work.ScreenProperties.all;
26 29
 
27 30
     entity Ecran is
28
-        Generic (  HEIGHT         : Natural;
29
-                   WIDTH          : Natural        
30
-        );
31 31
         Port (     CLK            : in STD_LOGIC;
32 32
                    RST            : in STD_LOGIC;
33 33
                    Data_Av        : in STD_LOGIC;
34
-                   Data_IN        : in Natural;
35
-                   X              : in Natural;
36
-                   Y              : in Natural;
34
+                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
35
+                   
36
+                   X              : in X_T;
37
+                   Y              : in Y_T;
37 38
                    OUT_ON         : out STD_LOGIC);
38 39
     end Ecran;
39 40
 
40 41
 architecture Behavioral of Ecran is
41 42
 
42 43
     component TableASCII is
43
-        Port ( CodeASCII : Natural;
44
-               Font : out font_T);
44
+    Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
45
+           Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
45 46
     end component;
46 47
 
47
-    constant Flush : Natural := 0;
48
-    constant RetourChariot : Natural := 13;
49
-
50
-    constant CaracterHeight : Natural := 16;
51
-    constant CaracterWidht  : Natural := 16;
52
-    constant HeightSize : Natural := HEIGHT/CaracterHeight;
53
-    constant WidthSize  : Natural := WIDTH/CaracterWidht;
48
+    constant Flush : STD_LOGIC_VECTOR (0 to 6) := "0000000";
49
+    constant RetourChariot : STD_LOGIC_VECTOR (0 to 6) := "0001101";
50
+    constant Delete : STD_LOGIC_VECTOR (0 to 6) := "1111111";
51
+    
52
+    signal Ecran : STD_LOGIC_VECTOR (0 to Ecran_Taille - 1) := (others => '0'); --(0 => '1', 1 => '0', 2 => '0', 3 => '1', 4 => '0', 5 => '0', 6 => '0', others => '0');
53
+    
54
+    signal L : STD_LOGIC_VECTOR (0 to 6) := "0000000";
55
+    signal L_inc : STD_LOGIC_VECTOR (0 to 6);
56
+    signal C : STD_LOGIC_VECTOR (0 to 6) := "0000000";
54 57
     
55
-    type T_Ligne is array (0 to WidthSize - 1) of Natural;
56
-    type T_Ecran is array (0 to HeightSize - 1) of T_Ligne;
58
+    signal InitialL : STD_LOGIC_VECTOR (0 to 6) := "0000000";
59
+    signal InitialL_inc : STD_LOGIC_VECTOR (0 to 6);
60
+    signal Full : STD_LOGIC := '0';
57 61
     
58
-    signal Ecran : T_Ecran := (others => (0 => 72, 1 => 101, 2 => 108, 3 => 108, 4 => 111, 5 => 32, 6 => 87, 7 => 111, 8 => 114, 9 => 108, 10 => 100, others => 0));
59
-    signal L : Natural := 0;
60
-    signal C : Natural := 0;
61
-    signal InitialL : Natural := 0;
62
-    signal Full : BOOLEAN := false;
62
+    signal L_Lecture : L_T := 0;
63 63
     
64
-    signal CurrentCodeASCII : Natural := 0;
65
-    signal CurrentFont : font_T;
64
+    signal point_dereferencement : Natural := 0;
65
+    signal point_dereferencement_ecriture : Natural := 0;
66
+    
67
+    signal CurrentCodeASCII : STD_LOGIC_VECTOR (0 to 6) := "0000000";
68
+    signal CurrentFont : STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1) := (others => '0');
66 69
     
67 70
 begin
68 71
 
@@ -74,45 +77,57 @@ begin
74 77
     begin
75 78
         wait until CLK'event and CLK='1';
76 79
         if (RST = '0') then
77
-            Ecran <= (others => (others => 0));
78
-            L <= 0;
79
-            C <= 0;
80
-            InitialL <= 0;
81
-            Full <= false;
80
+            Ecran <= (others => '0');
81
+            L <= "0000000";
82
+            C <= "0000000";
83
+            InitialL <= "0000000";
84
+            Full <= '0';
82 85
         elsif (Data_Av = '1') then
83 86
             if (Data_IN = Flush) then
84
-                Ecran <= (others => (others => 0));
85
-                L <= 0;
86
-                C <= 0;
87
-                InitialL <= 0;
88
-                Full <= false;
87
+                Ecran <= (others => '0');
88
+                L <= "0000000";
89
+                C <= "0000000";
90
+                InitialL <= "0000000";
91
+                Full <= '0';
89 92
             elsif (Data_IN = RetourChariot) then
90
-                C <= 0;
91
-                L <= (L + 1) mod HeightSize;
92
-                if ((L + 1) mod HeightSize = 0 or Full) then
93
-                    Full <= true;
94
-                    InitialL <= (InitialL + 1) mod HeightSize;
95
-                    Ecran((L + 1) mod HeightSize) <= (others => 0);
96
-                end if;   
93
+                C <= "0000000";
94
+                L <= L_inc;
95
+                if (L_inc = "0000000" or Full = '1') then
96
+                    Full <= '1';
97
+                    InitialL <= InitialL_inc;
98
+                    Ecran(7 * C_Blocks * to_integer(unsigned(L_inc)) to 7 * C_Blocks * (to_integer(unsigned(L_inc)) + 1) - 1) <= Zero_Line;
99
+                end if; 
100
+            elsif (Data_IN = Delete) then
101
+                if (C > 0) then
102
+                    C <= C - 1;
103
+                    Ecran(7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C))) to 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)) + 1) - 1) <= "0000000";
104
+                end if; 
97 105
             else
98
-                Ecran(L)(C) <= Data_IN;
106
+                Ecran(point_dereferencement_ecriture to point_dereferencement_ecriture + 6) <= Data_IN;
99 107
                 C <= C + 1;
100
-                if (C + 1 = WidthSize) then
101
-                    C <= 0;
102
-                    L <= (L + 1) mod HeightSize;
103
-                    if ((L + 1) mod HeightSize = 0 or Full) then
104
-                        Full <= true;
105
-                        InitialL <= (InitialL + 1) mod HeightSize;
106
-                        Ecran((L + 1) mod HeightSize) <= (others => 0);
108
+                if (C + 1 = C_Blocks) then
109
+                    C <= "0000000";
110
+                    L <= L_inc;
111
+                    if (L_inc = 0 or Full = '1') then
112
+                        Full <= '1';
113
+                        InitialL <= InitialL_inc;
114
+                        Ecran(7 * C_Blocks * to_integer(unsigned(L_inc)) to 7 * C_Blocks * (to_integer(unsigned(L_inc)) + 1) - 1) <= Zero_Line;
107 115
                     end if;   
108 116
                 end if;
109 117
             end if;
110 118
         end if;            
111 119
     end process;
112 120
     
113
-    CurrentCodeASCII <= Ecran((Y/CaracterHeight + InitialL) mod HeightSize)(X/CaracterWidht) when (Y/CaracterHeight < HeightSize and X/CaracterWidht < WidthSize and RST='1') else
114
-                        0;
121
+    L_inc <= "0000000" when L + 1 = L_Blocks else L + 1;
122
+    InitialL_inc <= "0000000" when InitialL + 1 = L_Blocks else InitialL + 1;
123
+    L_Lecture <= Y/Display_CaracterHeight + to_integer(unsigned(InitialL)) - L_Blocks when (Y/Display_CaracterHeight + to_integer(unsigned(InitialL))) >= L_Blocks else Y/Display_CaracterHeight + to_integer(unsigned(InitialL));
124
+        
125
+    point_dereferencement <= (7 * (C_Blocks * L_Lecture + (X/Display_CaracterWidht)));
126
+    point_dereferencement_ecriture <= 7 * (C_Blocks * to_integer(unsigned(L)) + to_integer(unsigned(C)));
127
+    
128
+    CurrentCodeASCII <= Ecran(point_dereferencement to point_dereferencement + 6) when (Y/Display_CaracterHeight < L_Blocks and X/Display_CaracterWidht < C_Blocks and RST='1') else
129
+                        "0000000";
115 130
 
116
-    OUT_ON <= CurrentFont((Y mod CaracterHeight) / (CaracterHeight / font_height), (X mod CaracterWidht) / (CaracterWidht / font_width));
131
+    OUT_ON <= CurrentFont(((Y mod Display_CaracterHeight) / (Display_CaracterHeight / font_height)) * font_width + ((Display_CaracterWidht - 1) - (X mod Display_CaracterWidht)) / (Display_CaracterWidht / font_width));
117 132
 
118 133
 end Behavioral;

+ 104
- 0
Processeur.srcs/sources_1/new/Keyboard.vhd View File

@@ -0,0 +1,104 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 01.07.2021 09:09:30
6
+-- Design Name: 
7
+-- Module Name: Keyboard - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Keyboard is
35
+    Port (CLK : in STD_LOGIC;
36
+  
37
+          PS2Clk : in STD_LOGIC;
38
+          PS2Data : in STD_LOGIC;
39
+        
40
+          Data_read : in STD_LOGIC;
41
+          Data_av : out STD_LOGIC;
42
+          Data : out STD_LOGIC_VECTOR (0 to 6);
43
+        
44
+          alert : out STD_LOGIC);
45
+end Keyboard;
46
+
47
+architecture Behavioral of Keyboard is
48
+
49
+    component KeyboardControler 
50
+    Port (CLK : in STD_LOGIC;
51
+  
52
+          PS2Clk : in STD_LOGIC;
53
+          PS2Data : in STD_LOGIC;
54
+        
55
+          Data_av : out STD_LOGIC;
56
+          Data : out STD_LOGIC_VECTOR (0 to 7);
57
+          
58
+          alert : out STD_LOGIC);
59
+    end component;
60
+    
61
+    component KeyboardToASCII
62
+        Port ( KeyCode : in STD_LOGIC_VECTOR (0 to 7);
63
+               CodeASCII : out STD_LOGIC_VECTOR (0 to 6));
64
+    end component;
65
+    
66
+    signal buffer_Data : STD_LOGIC_VECTOR (0 to 7);
67
+    signal keyboardControleur_Data_av : STD_LOGIC;
68
+    
69
+    signal intern_Data_av : STD_LOGIC := '0';
70
+    signal intern_Data : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
71
+
72
+begin
73
+    
74
+    instance_KeyboardControler : KeyboardControler
75
+    port map (CLK => CLK,
76
+      
77
+              PS2Clk => PS2Clk,
78
+              PS2Data => PS2Data,
79
+            
80
+              Data_av => keyboardControleur_Data_av,
81
+              Data => buffer_Data,
82
+              
83
+              alert => alert);
84
+              
85
+    instance_KeyboardToASCII : KeyboardToASCII 
86
+    port map ( KeyCode => buffer_Data,
87
+               CodeASCII => intern_Data);
88
+              
89
+    process
90
+    begin
91
+        wait until CLK'event and CLK = '1';
92
+        if (intern_Data_av = '0') then
93
+            if (keyboardControleur_Data_av = '1') then
94
+                Data <= intern_Data;
95
+                intern_Data_av <= '1';
96
+            end if;
97
+        elsif (Data_read = '1') then
98
+            intern_Data_av <= '0';
99
+        end if;
100
+    end process;
101
+
102
+    Data_av <= intern_Data_av;
103
+
104
+end Behavioral;

+ 126
- 0
Processeur.srcs/sources_1/new/KeyboardControler.vhd View File

@@ -0,0 +1,126 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 01.07.2021 09:09:30
6
+-- Design Name: 
7
+-- Module Name: KeyboardControler - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity KeyboardControler is
35
+  Port (CLK : in STD_LOGIC;
36
+  
37
+        PS2Clk : in STD_LOGIC;
38
+        PS2Data : in STD_LOGIC;
39
+        
40
+        Data_av : out STD_LOGIC;
41
+        Data : out STD_LOGIC_VECTOR (0 to 7);
42
+        
43
+        alert : out STD_LOGIC);
44
+end KeyboardControler;
45
+
46
+architecture Behavioral of KeyboardControler is
47
+
48
+    subtype compteur_T is Natural range 0 to 10;
49
+    signal compteur : compteur_T := 0;
50
+    signal current_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
51
+    signal previous_data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
52
+    signal parity : STD_LOGIC := '0';
53
+    signal intern_alert : STD_LOGIC := '0';
54
+    signal intern_Data_av : STD_LOGIC := '0';
55
+    signal dejaSignale : boolean := false;
56
+
57
+begin
58
+    
59
+    process 
60
+    begin
61
+        wait until PS2Clk'event and PS2Clk = '1';
62
+        case compteur is
63
+        when 0 =>
64
+            parity <= '1'; 
65
+            intern_alert <= '0';   
66
+            intern_Data_av <= '0';
67
+        when 1 =>
68
+            current_data(7) <= PS2Data;
69
+            parity <= parity XOR PS2Data;
70
+        when 2 =>
71
+            current_data(6) <= PS2Data;
72
+            parity <= parity XOR PS2Data;
73
+        when 3 =>
74
+            current_data(5) <= PS2Data;
75
+            parity <= parity XOR PS2Data;
76
+        when 4 =>
77
+            current_data(4) <= PS2Data;
78
+            parity <= parity XOR PS2Data;
79
+        when 5 =>
80
+            current_data(3) <= PS2Data;
81
+            parity <= parity XOR PS2Data;
82
+        when 6 =>
83
+            current_data(2) <= PS2Data;
84
+            parity <= parity XOR PS2Data;
85
+        when 7 =>
86
+            current_data(1) <= PS2Data;
87
+            parity <= parity XOR PS2Data;
88
+        when 8 =>
89
+            current_data(0) <= PS2Data;
90
+            parity <= parity XOR PS2Data;
91
+        when 9 =>
92
+            if (parity = PS2Data) then
93
+                intern_alert <= '0';
94
+            else 
95
+                intern_alert <= '1';
96
+            end if;
97
+        when 10 =>
98
+            if (intern_alert = '0') then
99
+                previous_data <= current_data;
100
+                if (not (previous_data = "11110000" or current_data = "11110000" or previous_data = "11100000")) then
101
+                    Data <= current_data;
102
+                    intern_Data_av <= '1';
103
+                end if; 
104
+            end if;
105
+        end case;
106
+    
107
+        compteur <= (compteur + 1) mod 11;
108
+    end process;
109
+    
110
+    process
111
+    begin
112
+        wait until CLK'event and CLK = '1';
113
+        if (intern_Data_av = '1' and not dejaSignale) then
114
+            Data_av <= '1';
115
+            dejaSignale <= true;
116
+        else 
117
+            Data_av <= '0';
118
+        end if;
119
+        if (intern_Data_av = '0') then
120
+            dejaSignale <= false;
121
+        end if;
122
+    end process; 
123
+
124
+    alert <= intern_alert;
125
+    
126
+end Behavioral;

+ 75
- 0
Processeur.srcs/sources_1/new/KeyboardToASCII.vhd View File

@@ -0,0 +1,75 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 02.07.2021 10:43:18
6
+-- Design Name: 
7
+-- Module Name: KeyboardToASCII - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+entity KeyboardToASCII is
26
+    Port ( KeyCode : in STD_LOGIC_VECTOR (0 to 7);
27
+           CodeASCII : out STD_LOGIC_VECTOR (0 to 6));
28
+end KeyboardToASCII;
29
+
30
+architecture Behavioral of KeyboardToASCII is
31
+
32
+begin
33
+
34
+    CodeASCII <= "0000000" when (KeyCode = x"05") else     -- F1 -> flush
35
+                 "0001101" when (KeyCode = x"5a") else    -- Enter
36
+                 "1111111" when (KeyCode = x"66") else   -- Del
37
+                 "1000001" when (KeyCode = x"15") else    -- A
38
+                 "1000010" when (KeyCode = x"32") else    -- B
39
+                 "1000011" when (KeyCode = x"21") else    -- C
40
+                 "1000100" when (KeyCode = x"23") else    -- D
41
+                 "1000101" when (KeyCode = x"24") else    -- E
42
+                 "1000110" when (KeyCode = x"2b") else    -- F
43
+                 "1000111" when (KeyCode = x"34") else    -- G
44
+                 "1001000" when (KeyCode = x"33") else    -- H
45
+                 "1001001" when (KeyCode = x"83") else    -- I
46
+                 "1001010" when (KeyCode = x"3b") else    -- J
47
+                 "1001011" when (KeyCode = x"42") else    -- K
48
+                 "1001100" when (KeyCode = x"4b") else    -- L
49
+                 "1001101" when (KeyCode = x"4c") else    -- M
50
+                 "1001110" when (KeyCode = x"31") else    -- N
51
+                 "1001111" when (KeyCode = x"44") else    -- O
52
+                 "1010000" when (KeyCode = x"4d") else    -- P
53
+                 "1010001" when (KeyCode = x"1c") else    -- Q
54
+                 "1010010" when (KeyCode = x"2d") else    -- R
55
+                 "1010011" when (KeyCode = x"1b") else    -- S
56
+                 "1010100" when (KeyCode = x"2c") else    -- T
57
+                 "1010101" when (KeyCode = x"3c") else    -- U
58
+                 "1010110" when (KeyCode = x"2a") else    -- V
59
+                 "1010111" when (KeyCode = x"1a") else    -- W
60
+                 "1011000" when (KeyCode = x"22") else    -- X
61
+                 "1011001" when (KeyCode = x"35") else    -- Y
62
+                 "1011010" when (KeyCode = x"1d") else    -- Z
63
+                 "0110000" when (KeyCode = x"70") else    -- 0
64
+                 "0110001" when (KeyCode = x"69") else    -- 1
65
+                 "0110010" when (KeyCode = x"72") else    -- 2
66
+                 "0110011" when (KeyCode = x"7a") else    -- 3
67
+                 "0110100" when (KeyCode = x"6b") else    -- 4
68
+                 "0110101" when (KeyCode = x"73") else    -- 5
69
+                 "0110110" when (KeyCode = x"74") else    -- 6
70
+                 "0110111" when (KeyCode = x"6c") else    -- 7
71
+                 "0111000" when (KeyCode = x"75") else    -- 8
72
+                 "0111001" when (KeyCode = x"7d") else    -- 9
73
+                 "0000001";                                -- Rien
74
+
75
+end Behavioral;

+ 33
- 0
Processeur.srcs/sources_1/new/ScreenProperties.vhd View File

@@ -0,0 +1,33 @@
1
+library IEEE;
2
+use IEEE.STD_LOGIC_1164.ALL;
3
+
4
+package ScreenProperties is 
5
+    
6
+    constant Display_CaracterWidht  : Natural := 64;
7
+    constant Display_CaracterHeight : Natural := 64;
8
+
9
+    constant screen_width   : natural := 1280;
10
+    constant screen_height  : natural := 1024;
11
+    
12
+    constant X_PulseWidth : Natural := 112;
13
+    constant X_FrontPorch : Natural := 48;
14
+    constant X_BackPorch  : Natural := 248;
15
+    constant Y_PulseWidth : Natural := 3;
16
+    constant Y_FrontPorch : Natural := 1;
17
+    constant Y_BackPorch  : Natural := 38;
18
+        
19
+    subtype X_T is Natural range 0 to screen_width  + X_PulseWidth + X_FrontPorch + X_BackPorch - 1;
20
+    subtype Y_T is Natural range 0 to screen_height + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1;
21
+    
22
+    constant C_Blocks : Natural := screen_width/Display_CaracterWidht;
23
+    constant L_Blocks : Natural := screen_height/Display_CaracterHeight;
24
+    constant Ecran_Taille : Natural := C_Blocks * L_Blocks * 7;
25
+    
26
+    constant L_Size : Natural := C_Blocks * 7;
27
+    
28
+    constant Zero_Line : STD_LOGIC_VECTOR (0 to L_Size - 1) := (others => '0');
29
+    
30
+    subtype L_T is Natural range 0 to L_Blocks - 1;
31
+    subtype C_T is Natural range 0 to C_Blocks - 1;
32
+    
33
+end package;

+ 12
- 34
Processeur.srcs/sources_1/new/ScreenSystem.vhd View File

@@ -22,6 +22,8 @@
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24 24
 
25
+use work.ScreenProperties.all;
26
+
25 27
 -- Uncomment the following library declaration if using
26 28
 -- arithmetic functions with Signed or Unsigned values
27 29
 --use IEEE.NUMERIC_STD.ALL;
@@ -47,23 +49,14 @@ end ScreenSystem;
47 49
 architecture Behavioral of ScreenSystem is
48 50
 
49 51
     component VGAControler is
50
-    Generic (  HEIGHT    : Natural;
51
-               WIDTH     : Natural;
52
-               X_PulseWidth : Natural;
53
-               X_FrontPorch : Natural;
54
-               X_BackPorch  : Natural;
55
-               Y_PulseWidth : Natural;
56
-               Y_FrontPorch : Natural;
57
-               Y_BackPorch  : Natural              
58
-    );
59 52
     Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
60 53
                VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
61 54
                VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
62 55
                VGA_HS    : out STD_LOGIC;
63 56
                VGA_VS    : out STD_LOGIC;
64 57
                
65
-               X         : out Natural;
66
-               Y         : out Natural;
58
+               X         : out X_T;
59
+               Y         : out Y_T;
67 60
                PIXEL_ON  : in STD_LOGIC;
68 61
                
69 62
                CLK       : in STD_LOGIC;
@@ -80,45 +73,25 @@ architecture Behavioral of ScreenSystem is
80 73
     end component;
81 74
     
82 75
     component Ecran is
83
-        Generic (  HEIGHT         : Natural;
84
-                   WIDTH          : Natural        
85
-        );
86 76
         Port (     CLK            : in STD_LOGIC;
87 77
                    RST            : in STD_LOGIC;
88 78
                    Data_Av        : in STD_LOGIC;
89
-                   Data_IN        : in Natural;
90
-                   X              : in Natural;
91
-                   Y              : in Natural;
79
+                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
80
+                   X              : in X_T;
81
+                   Y              : in Y_T;
92 82
                    OUT_ON         : out STD_LOGIC);
93 83
     end component;
94 84
     
95
-    signal my_X : Natural := 0;
96
-    signal my_Y : Natural := 0;
85
+    signal my_X : X_T := 0;
86
+    signal my_Y : Y_T := 0;
97 87
     signal my_PIXEL_ON : STD_LOGIC := '0';
98 88
     
99
-    signal compteur : natural := 0;
100 89
     signal my_CLK : STD_LOGIC := '0';
101 90
     signal RST : STD_LOGIC;
102 91
 
103 92
 begin
104 93
 
105 94
     instanceVGA : VGAControler 
106
-    generic map(  HEIGHT => 1024,
107
-                  WIDTH => 1280,
108
-                  X_PulseWidth => 112,
109
-                  X_FrontPorch => 48,
110
-                  X_BackPorch  => 248,
111
-                  Y_PulseWidth => 3,
112
-                  Y_FrontPorch => 1,
113
-                  Y_BackPorch  => 38)
114 95
     port map(  VGA_RED   => vgaRed,
115 96
                VGA_BLUE  => vgaBlue,
116 97
                VGA_GREEN => vgaGreen,
@@ -138,26 +111,13 @@ begin
138 111
               clk_in1 => CLK,
139 112
               clk_out1 => my_CLK
140 113
              );
141
-          
142
-
114
+    
115
+    
143 116
     instance_Ecran : Ecran
144
-    generic map (  HEIGHT => 1024,
145
-                   WIDTH  => 1280        
146
-    )
147 117
     port map (     CLK     => CLK,
148 118
                    RST     => RST,
149 119
                    Data_Av => '0',
150
-                   Data_IN => 0,
120
+                   Data_IN => "0000000",
151 121
                    X => my_X,
152 122
                    Y => my_Y,
153 123
                    OUT_ON => my_PIXEL_ON);

+ 95
- 0
Processeur.srcs/sources_1/new/SystemKeyboard.vhd View File

@@ -0,0 +1,95 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 01.07.2021 13:37:43
6
+-- Design Name: 
7
+-- Module Name: SystemKeyboard - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity SystemKeyboard is
35
+    Port (CLK : in STD_LOGIC;
36
+    
37
+          PS2Clk : in STD_LOGIC;
38
+          PS2Data : in STD_LOGIC;
39
+          
40
+          led : out STD_LOGIC_VECTOR (0 to 10);
41
+          btnC : in STD_LOGIC);
42
+end SystemKeyboard;
43
+
44
+architecture Behavioral of SystemKeyboard is
45
+
46
+component Keyboard 
47
+    Port (CLK : in STD_LOGIC;
48
+  
49
+          PS2Clk : in STD_LOGIC;
50
+          PS2Data : in STD_LOGIC;
51
+        
52
+          Data_read : in STD_LOGIC;
53
+          Data_av : out STD_LOGIC;
54
+          Data : out STD_LOGIC_VECTOR (0 to 6);
55
+        
56
+          alert : out STD_LOGIC);
57
+end component;
58
+
59
+signal intern_Data_read : STD_LOGIC := '0';
60
+signal intern_Data_av   : STD_LOGIC := '0';
61
+signal Data_Read : STD_LOGIC_VECTOR (0 to 6);
62
+
63
+begin
64
+
65
+    instance_Keyboard : Keyboard
66
+    port map (CLK => CLK,
67
+    
68
+              PS2Clk => PS2Clk,
69
+              PS2Data => PS2Data,
70
+            
71
+              Data_read => intern_Data_read,
72
+              Data_av => intern_Data_av,
73
+              Data => Data_Read,
74
+            
75
+              alert => led(10));
76
+       
77
+    led(7) <= '0';       
78
+    led(8) <= intern_Data_av;
79
+    led(9) <= intern_Data_read;
80
+    
81
+    process
82
+    begin
83
+        wait until CLK'event and CLK = '1';
84
+        if (intern_Data_av = '1' and btnC = '1') then
85
+            led(0 to 6) <= Data_read;
86
+            intern_Data_read <= '1';
87
+        else 
88
+            intern_Data_read <= '0';
89
+        end if;
90
+    end process;
91
+            
92
+   
93
+              
94
+
95
+end Behavioral;

+ 231
- 0
Processeur.srcs/sources_1/new/SystemKeyboardScreen.vhd View File

@@ -0,0 +1,231 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 02.07.2021 10:04:44
6
+-- Design Name: 
7
+-- Module Name: SystemKeyboardScreen - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+use work.ScreenProperties.all;
26
+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
29
+--use IEEE.NUMERIC_STD.ALL;
30
+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
35
+
36
+entity SystemKeyboardScreen is
37
+    Port ( CLK : in STD_LOGIC;
38
+    
39
+           PS2Clk : in STD_LOGIC;
40
+           PS2Data : in STD_LOGIC;
41
+           
42
+           vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
43
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
44
+           vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
45
+           Hsync : out STD_LOGIC;
46
+           Vsync : out STD_LOGIC);
47
+end SystemKeyboardScreen;
48
+
49
+architecture Behavioral of SystemKeyboardScreen is
50
+
51
+    component Keyboard 
52
+    Port (CLK : in STD_LOGIC;
53
+  
54
+          PS2Clk : in STD_LOGIC;
55
+          PS2Data : in STD_LOGIC;
56
+        
57
+          Data_read : in STD_LOGIC;
58
+          Data_av : out STD_LOGIC;
59
+          Data : out STD_LOGIC_VECTOR (0 to 6);
60
+        
61
+          alert : out STD_LOGIC);
62
+    end component;
63
+    
64
+    component VGAControler is
65
+    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
66
+               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
67
+               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
68
+               VGA_HS    : out STD_LOGIC;
69
+               VGA_VS    : out STD_LOGIC;
70
+               
71
+               X         : out X_T;
72
+               Y         : out Y_T;
73
+               PIXEL_ON  : in STD_LOGIC;
74
+               
75
+               CLK       : in STD_LOGIC;
76
+               RST       : in STD_LOGIC);
77
+    end component; 
78
+    
79
+    component clk_wiz_0
80
+    port
81
+     (-- Clock in ports
82
+      clk_in1           : in     std_logic;
83
+      -- Clock out ports
84
+      clk_out1          : out    std_logic
85
+     );
86
+    end component;
87
+    
88
+    component Ecran is
89
+        Port (     CLK            : in STD_LOGIC;
90
+                   RST            : in STD_LOGIC;
91
+                   Data_Av        : in STD_LOGIC;
92
+                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
93
+                   X              : in X_T;
94
+                   Y              : in Y_T;
95
+                   OUT_ON         : out STD_LOGIC);
96
+    end component;
97
+    
98
+    signal my_X : X_T := 0;
99
+    signal my_Y : Y_T := 0;
100
+    signal my_PIXEL_ON : STD_LOGIC := '0';
101
+    
102
+    signal Keyboard_Data_read : STD_LOGIC := '0';
103
+    signal Keyboard_Data_av : STD_LOGIC := '0';
104
+    signal Keyboard_Data : STD_LOGIC_VECTOR (0 to 6);
105
+    signal Screen_Data_av : STD_LOGIC := '0';
106
+    
107
+    
108
+    signal alert : STD_LOGIC := '0';
109
+    
110
+    signal my_CLK : STD_LOGIC := '0';
111
+    signal RST : STD_LOGIC := '1';
112
+
113
+begin
114
+    
115
+    instanceVGA : VGAControler 
116
+    port map(  VGA_RED   => vgaRed,
117
+               VGA_BLUE  => vgaBlue,
118
+               VGA_GREEN => vgaGreen,
119
+               VGA_HS    => Hsync,
120
+               VGA_VS    => Vsync,
121
+                 
122
+               X         => my_X,
123
+               Y         => my_Y,
124
+               PIXEL_ON  => my_PIXEL_ON,
125
+                 
126
+               CLK       => my_CLK,
127
+               RST       => RST);
128
+               
129
+    
130
+    clk_wiz_0_inst : clk_wiz_0
131
+    port map (
132
+              clk_in1 => CLK,
133
+              clk_out1 => my_CLK
134
+             );
135
+
136
+    instance_Ecran : Ecran
137
+    port map (     CLK     => CLK,
138
+                   RST     => RST,
139
+                   Data_Av => Screen_Data_av,
140
+                   Data_IN => Keyboard_Data,
141
+                   X => my_X,
142
+                   Y => my_Y,
143
+                   OUT_ON => my_PIXEL_ON);
144
+                   
145
+    instance_Keyboard : Keyboard 
146
+    port map (CLK => CLK,
147
+ 
148
+              PS2Clk => PS2Clk,
149
+              PS2Data => PS2Data,
150
+       
151
+              Data_read => Keyboard_Data_av,
152
+              Data_av => Keyboard_Data_av,
153
+              Data => Keyboard_Data,
154
+       
155
+              alert => alert);
156
+              
157
+    process
158
+    begin
159
+        wait until CLK'event and CLK = '1';
160
+        if (Keyboard_Data_av = '1') then
161
+            Screen_Data_av <= '1';
162
+        else
163
+            Screen_Data_av <= '0';
164
+        end if;
165
+    end process;
166
+        
167
+
168
+end Behavioral;
169
+
170
+
171
+--entity SystemKeyboardScreen is
172
+--    Port ( CLK : in STD_LOGIC;
173
+    
174
+--           led : out STD_LOGIC_VECTOR (0 to 0);
175
+--           btnC : in STD_LOGIC;
176
+--           sw : in STD_LOGIC_VECTOR (0 to 6));
177
+--end SystemKeyboardScreen;
178
+
179
+--architecture Behavioral of SystemKeyboardScreen is
180
+
181
+--    component Ecran is
182
+--        Port (     CLK            : in STD_LOGIC;
183
+--                   RST            : in STD_LOGIC;
184
+--                   Data_Av        : in STD_LOGIC;
185
+--                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
186
+--                   X              : in X_T;
187
+--                   Y              : in Y_T;
188
+--                   OUT_ON         : out STD_LOGIC);
189
+--    end component;
190
+    
191
+--    component Compteur_X is
192
+--    Port ( CLK : in STD_LOGIC;
193
+--           RST : in STD_LOGIC;
194
+--           Value : out X_T;
195
+--           Carry : out STD_LOGIC);
196
+--    end component;
197
+    
198
+--    component Compteur_Y is
199
+--    Port ( CLK : in STD_LOGIC;
200
+--           RST : in STD_LOGIC;
201
+--           Value : out Y_T);
202
+--    end component;
203
+    
204
+--    signal my_X : X_T := 0;
205
+--    signal my_Y : Y_T := 0;
206
+--    signal Y_CLK : STD_LOGIC := '0';
207
+--    signal RST : STD_LOGIC := '1';
208
+
209
+--begin
210
+
211
+--    X_Compteur : Compteur_X
212
+--    port map    (CLK => CLK,
213
+--                 RST => RST,
214
+--                 Value => my_X,
215
+--                 Carry => Y_CLK);
216
+                 
217
+--    Y_Compteur : Compteur_Y
218
+--    port map    (CLK => Y_CLK,
219
+--                 RST => RST,
220
+--                 Value => my_Y);
221
+
222
+--    instance_Ecran : Ecran
223
+--    port map (     CLK     => CLK,
224
+--                   RST     => RST,
225
+--                   Data_Av => btnC,
226
+--                   Data_IN => sw,
227
+--                   X => my_X,
228
+--                   Y => my_Y,
229
+--                   OUT_ON => led(0));
230
+                   
231
+--end Behavioral;

+ 6
- 141
Processeur.srcs/sources_1/new/TableASCII.vhd View File

@@ -21,159 +21,24 @@
21 21
 
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24
-
25
-Library UNISIM;
26
-use UNISIM.vcomponents.all;
27
-
28
-Library UNIMACRO;
29
-use UNIMACRO.vcomponents.all;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+use IEEE.NUMERIC_STD.ALL;
30 26
 
31 27
 use work.font.all;
32 28
 
33 29
 
34 30
 
35 31
 entity TableASCII is
36
-    Port ( CodeASCII : Natural;
37
-           Font : out font_T);
32
+    Port ( CodeASCII : STD_LOGIC_VECTOR (0 to 6);
33
+           Font : out STD_LOGIC_VECTOR (0 to (font_width * font_height) - 1));
38 34
 end TableASCII;
39 35
 
40 36
 architecture Behavioral of TableASCII is
41
-
42
-    type FontMemory_T is array (0 to 127) of font_T;
43 37
     
44
-    signal FontMemory : FontMemory_T := (
45
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0000 (nul)
46
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0001
47
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0002
48
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0003
49
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0004
50
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0005
51
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0006
52
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0007
53
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0008
54
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0009
55
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000A
56
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000B
57
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000C
58
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000D
59
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000E
60
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000F
61
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0010
62
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0011
63
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0012
64
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0013
65
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0014
66
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0015
67
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0016
68
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0017
69
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0018
70
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0019
71
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001A
72
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001B
73
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001C
74
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001D
75
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001E
76
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001F
77
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0020 (space)
78
-        ( x"18", x"3C", x"3C", x"18", x"18", x"00", x"18", x"00"),   -- U+0021 (!)
79
-        ( x"36", x"36", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0022 (")
80
-        ( x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"),   -- U+0023 (#)
81
-        ( x"0C", x"3E", x"03", x"1E", x"30", x"1F", x"0C", x"00"),   -- U+0024 ($)
82
-        ( x"00", x"63", x"33", x"18", x"0C", x"66", x"63", x"00"),   -- U+0025 (%)
83
-        ( x"1C", x"36", x"1C", x"6E", x"3B", x"33", x"6E", x"00"),   -- U+0026 (&)
84
-        ( x"06", x"06", x"03", x"00", x"00", x"00", x"00", x"00"),   -- U+0027 (')
85
-        ( x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00"),   -- U+0028 (()
86
-        ( x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00"),   -- U+0029 ())
87
-        ( x"00", x"66", x"3C", x"FF", x"3C", x"66", x"00", x"00"),   -- U+002A (*)
88
-        ( x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00"),   -- U+002B (+)
89
-        ( x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06"),   -- U+002C (,)
90
-        ( x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00"),   -- U+002D (-)
91
-        ( x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00"),   -- U+002E (.)
92
-        ( x"60", x"30", x"18", x"0C", x"06", x"03", x"01", x"00"),   -- U+002F (/)
93
-        ( x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00"),   -- U+0030 (0)
94
-        ( x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00"),   -- U+0031 (1)
95
-        ( x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00"),   -- U+0032 (2)
96
-        ( x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00"),   -- U+0033 (3)
97
-        ( x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00"),   -- U+0034 (4)
98
-        ( x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00"),   -- U+0035 (5)
99
-        ( x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00"),   -- U+0036 (6)
100
-        ( x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00"),   -- U+0037 (7)
101
-        ( x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00"),   -- U+0038 (8)
102
-        ( x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00"),   -- U+0039 (9)
103
-        ( x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00"),   -- U+003A (:)
104
-        ( x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"06"),   -- U+003B (--)
105
-        ( x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00"),   -- U+003C (<)
106
-        ( x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00"),   -- U+003D (=)
107
-        ( x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00"),   -- U+003E (>)
108
-        ( x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00"),   -- U+003F (?)
109
-        ( x"3E", x"63", x"7B", x"7B", x"7B", x"03", x"1E", x"00"),   -- U+0040 (@)
110
-        ( x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00"),   -- U+0041 (A)
111
-        ( x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00"),   -- U+0042 (B)
112
-        ( x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00"),   -- U+0043 (C)
113
-        ( x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00"),   -- U+0044 (D)
114
-        ( x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00"),   -- U+0045 (E)
115
-        ( x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00"),   -- U+0046 (F)
116
-        ( x"3C", x"66", x"03", x"03", x"73", x"66", x"7C", x"00"),   -- U+0047 (G)
117
-        ( x"33", x"33", x"33", x"3F", x"33", x"33", x"33", x"00"),   -- U+0048 (H)
118
-        ( x"1E", x"0C", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+0049 (I)
119
-        ( x"78", x"30", x"30", x"30", x"33", x"33", x"1E", x"00"),   -- U+004A (J)
120
-        ( x"67", x"66", x"36", x"1E", x"36", x"66", x"67", x"00"),   -- U+004B (K)
121
-        ( x"0F", x"06", x"06", x"06", x"46", x"66", x"7F", x"00"),   -- U+004C (L)
122
-        ( x"63", x"77", x"7F", x"7F", x"6B", x"63", x"63", x"00"),   -- U+004D (M)
123
-        ( x"63", x"67", x"6F", x"7B", x"73", x"63", x"63", x"00"),   -- U+004E (N)
124
-        ( x"1C", x"36", x"63", x"63", x"63", x"36", x"1C", x"00"),   -- U+004F (O)
125
-        ( x"3F", x"66", x"66", x"3E", x"06", x"06", x"0F", x"00"),   -- U+0050 (P)
126
-        ( x"1E", x"33", x"33", x"33", x"3B", x"1E", x"38", x"00"),   -- U+0051 (Q)
127
-        ( x"3F", x"66", x"66", x"3E", x"36", x"66", x"67", x"00"),   -- U+0052 (R)
128
-        ( x"1E", x"33", x"07", x"0E", x"38", x"33", x"1E", x"00"),   -- U+0053 (S)
129
-        ( x"3F", x"2D", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+0054 (T)
130
-        ( x"33", x"33", x"33", x"33", x"33", x"33", x"3F", x"00"),   -- U+0055 (U)
131
-        ( x"33", x"33", x"33", x"33", x"33", x"1E", x"0C", x"00"),   -- U+0056 (V)
132
-        ( x"63", x"63", x"63", x"6B", x"7F", x"77", x"63", x"00"),   -- U+0057 (W)
133
-        ( x"63", x"63", x"36", x"1C", x"1C", x"36", x"63", x"00"),   -- U+0058 (X)
134
-        ( x"33", x"33", x"33", x"1E", x"0C", x"0C", x"1E", x"00"),   -- U+0059 (Y)
135
-        ( x"7F", x"63", x"31", x"18", x"4C", x"66", x"7F", x"00"),   -- U+005A (Z)
136
-        ( x"1E", x"06", x"06", x"06", x"06", x"06", x"1E", x"00"),   -- U+005B ([)
137
-        ( x"03", x"06", x"0C", x"18", x"30", x"60", x"40", x"00"),   -- U+005C (\)
138
-        ( x"1E", x"18", x"18", x"18", x"18", x"18", x"1E", x"00"),   -- U+005D (])
139
-        ( x"08", x"1C", x"36", x"63", x"00", x"00", x"00", x"00"),   -- U+005E (^)
140
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"FF"),   -- U+005F (_)
141
-        ( x"0C", x"0C", x"18", x"00", x"00", x"00", x"00", x"00"),   -- U+0060 (`)
142
-        ( x"00", x"00", x"1E", x"30", x"3E", x"33", x"6E", x"00"),   -- U+0061 (a)
143
-        ( x"07", x"06", x"06", x"3E", x"66", x"66", x"3B", x"00"),   -- U+0062 (b)
144
-        ( x"00", x"00", x"1E", x"33", x"03", x"33", x"1E", x"00"),   -- U+0063 (c)
145
-        ( x"38", x"30", x"30", x"3e", x"33", x"33", x"6E", x"00"),   -- U+0064 (d)
146
-        ( x"00", x"00", x"1E", x"33", x"3f", x"03", x"1E", x"00"),   -- U+0065 (e)
147
-        ( x"1C", x"36", x"06", x"0f", x"06", x"06", x"0F", x"00"),   -- U+0066 (f)
148
-        ( x"00", x"00", x"6E", x"33", x"33", x"3E", x"30", x"1F"),   -- U+0067 (g)
149
-        ( x"07", x"06", x"36", x"6E", x"66", x"66", x"67", x"00"),   -- U+0068 (h)
150
-        ( x"0C", x"00", x"0E", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+0069 (i)
151
-        ( x"30", x"00", x"30", x"30", x"30", x"33", x"33", x"1E"),   -- U+006A (j)
152
-        ( x"07", x"06", x"66", x"36", x"1E", x"36", x"67", x"00"),   -- U+006B (k)
153
-        ( x"0E", x"0C", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+006C (l)
154
-        ( x"00", x"00", x"33", x"7F", x"7F", x"6B", x"63", x"00"),   -- U+006D (m)
155
-        ( x"00", x"00", x"1F", x"33", x"33", x"33", x"33", x"00"),   -- U+006E (n)
156
-        ( x"00", x"00", x"1E", x"33", x"33", x"33", x"1E", x"00"),   -- U+006F (o)
157
-        ( x"00", x"00", x"3B", x"66", x"66", x"3E", x"06", x"0F"),   -- U+0070 (p)
158
-        ( x"00", x"00", x"6E", x"33", x"33", x"3E", x"30", x"78"),   -- U+0071 (q)
159
-        ( x"00", x"00", x"3B", x"6E", x"66", x"06", x"0F", x"00"),   -- U+0072 (r)
160
-        ( x"00", x"00", x"3E", x"03", x"1E", x"30", x"1F", x"00"),   -- U+0073 (s)
161
-        ( x"08", x"0C", x"3E", x"0C", x"0C", x"2C", x"18", x"00"),   -- U+0074 (t)
162
-        ( x"00", x"00", x"33", x"33", x"33", x"33", x"6E", x"00"),   -- U+0075 (u)
163
-        ( x"00", x"00", x"33", x"33", x"33", x"1E", x"0C", x"00"),   -- U+0076 (v)
164
-        ( x"00", x"00", x"63", x"6B", x"7F", x"7F", x"36", x"00"),   -- U+0077 (w)
165
-        ( x"00", x"00", x"63", x"36", x"1C", x"36", x"63", x"00"),   -- U+0078 (x)
166
-        ( x"00", x"00", x"33", x"33", x"33", x"3E", x"30", x"1F"),   -- U+0079 (y)
167
-        ( x"00", x"00", x"3F", x"19", x"0C", x"26", x"3F", x"00"),   -- U+007A (z)
168
-        ( x"38", x"0C", x"0C", x"07", x"0C", x"0C", x"38", x"00"),   -- U+007B (()
169
-        ( x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00"),   -- U+007C (|)
170
-        ( x"07", x"0C", x"0C", x"38", x"0C", x"0C", x"07", x"00"),   -- U+007D ())
171
-        ( x"6E", x"3B", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+007E (~)
172
-        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00")    -- U+007F
173
-    );
38
+    signal FontMemory : STD_LOGIC_VECTOR (0 to (128 * font_width * font_height) - 1) := (x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000183C3C1818001800363600000000000036367F367F3636000C3E031E301F0C00006333180C6663001C361C6E3B336E000606030000000000180C0606060C1800060C1818180C060000663CFF3C660000000C0C3F0C0C000000000000000C0C060000003F0000000000000000000C0C006030180C060301003E63737B6F673E000C0E0C0C0C0C3F001E33301C06333F001E33301C30331E00383C36337F3078003F031F3030331E001C06031F33331E003F3330180C0C0C001E33331E33331E001E33333E30180E00000C0C00000C0C00000C0C00000C0C06180C0603060C180000003F00003F0000060C1830180C06001E3330180C000C003E637B7B7B031E000C1E33333F3333003F66663E66663F003C66030303663C001F36666666361F007F46161E16467F007F46161E16060F003C66030373667C003333333F333333001E0C0C0C0C0C1E007830303033331E006766361E366667000F06060646667F0063777F7F6B63630063676F7B736363001C36636363361C003F66663E06060F001E3333333B1E38003F66663E366667001E33070E38331E003F2D0C0C0C0C1E003333333333333F0033333333331E0C006363636B7F7763006363361C1C3663003333331E0C0C1E007F6331184C667F001E06060606061E0003060C18306040001E18181818181E00081C36630000000000000000000000FF0C0C18000000000000001E303E336E000706063E66663B0000001E3303331E003830303e33336E0000001E333f031E001C36060f06060F0000006E33333E301F0706366E666667000C000E0C0C0C1E00300030303033331E070666361E3667000E0C0C0C0C0C1E000000337F7F6B630000001F333333330000001E3333331E0000003B66663E060F00006E33333E307800003B6E66060F0000003E031E301F00080C3E0C0C2C18000000333333336E0000003333331E0C000000636B7F7F3600000063361C36630000003333333E301F00003F190C263F00380C0C070C0C38001818180018181800070C0C380C0C07006E3B0000000000000000000000000000");
174 39
     
175 40
 begin
176 41
 
177
-   Font <= FontMemory(CodeASCII);
42
+   Font <= FontMemory(font_height * font_width * to_integer(unsigned(CodeASCII)) to font_height * font_width * (to_integer(unsigned(CodeASCII)) + 1) - 1);
178 43
    
179 44
 end Behavioral;

+ 31
- 45
Processeur.srcs/sources_1/new/VGAControler.vhd View File

@@ -22,33 +22,17 @@
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24 24
 
25
---use IEEE.NUMERIC_STD.ALL;
26
-
27
---library UNISIM;
28
---use UNISIM.VComponents.all;
25
+use work.ScreenProperties.all;
29 26
 
30 27
 entity VGAControler is
31
-    Generic (  HEIGHT    : Natural;
32
-               WIDTH     : Natural;
33
-               X_PulseWidth : Natural;
34
-               X_FrontPorch : Natural;
35
-               X_BackPorch  : Natural;
36
-               Y_PulseWidth : Natural;
37
-               Y_FrontPorch : Natural;
38
-               Y_BackPorch  : Natural              
39
-    );
40 28
     Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
41 29
                VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
42 30
                VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
43 31
                VGA_HS    : out STD_LOGIC;
44 32
                VGA_VS    : out STD_LOGIC;
45 33
                
46
-               X         : out Natural;
47
-               Y         : out Natural;
34
+               X         : out X_T;
35
+               Y         : out Y_T;
48 36
                PIXEL_ON  : in STD_LOGIC;
49 37
                
50 38
                CLK       : in STD_LOGIC;
@@ -57,55 +41,53 @@ end VGAControler;
57 41
 
58 42
 architecture Behavioral of VGAControler is
59 43
 
60
-    component Compteur is
61
-    Generic (Min : Natural;
62
-             Max : Natural
63
-            );
64
-    Port    (CLK : in STD_LOGIC;
65
-             RST : in STD_LOGIC;
66
-             Value : out Natural;
67
-             Carry : out STD_LOGIC);
44
+    component Compteur_X is
45
+    Port ( CLK : in STD_LOGIC;
46
+           RST : in STD_LOGIC;
47
+           Value : out X_T;
48
+           Carry : out STD_LOGIC);
68 49
     end component;
69 50
     
70
-    signal X_pos : Natural := 0;
71
-    signal Y_pos : Natural := 0;
51
+    component Compteur_Y is
52
+    Port ( CLK : in STD_LOGIC;
53
+           RST : in STD_LOGIC;
54
+           Value : out Y_T);
55
+    end component;
56
+
57
+
58
+    signal X_pos : X_T := 0;
59
+    signal Y_pos : Y_T := 0;
72 60
     signal Y_CLK : STD_LOGIC := '0';
73
-    signal Screen_CLK : STD_LOGIC := '0';
74 61
     signal active : BOOLEAN := false;
75 62
 
76
-begin
77
-
78
-    X_Compteur : Compteur 
79
-    generic map (Min => 0,
80
-                 Max => WIDTH + X_PulseWidth + X_FrontPorch + X_BackPorch - 1)
63
+begin    
64
+    
65
+    X_Compteur : Compteur_X
81 66
     port map    (CLK => CLK,
82 67
                  RST => RST,
83 68
                  Value => X_pos,
84 69
                  Carry => Y_CLK);
85 70
                  
86
-    Y_Compteur : Compteur 
87
-    generic map (Min => 0,
88
-                 Max => HEIGHT + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1)
71
+    Y_Compteur : Compteur_Y
89 72
     port map    (CLK => Y_CLK,
90 73
                  RST => RST,
91
-                 Value => Y_pos,
92
-                 Carry => Screen_CLK);
74
+                 Value => Y_pos);
93 75
                  
94
-    active <= ((X_pos < WIDTH) and (Y_pos < HEIGHT));
76
+    active <= ((X_pos < screen_width) and (Y_pos < screen_height));
95 77
                  
96
-    VGA_RED   <= "0000" when (RST = '0') else 
97
-                 "1000" when ((PIXEL_ON = '0') or (not active)) else 
78
+    VGA_RED   <= "0000" when ((RST = '0') or (not active)) else 
79
+                 "1000" when (PIXEL_ON = '0') else 
98 80
                  "1111";
99
-    VGA_BLUE  <= "0000" when (RST = '0') else 
100
-                 "1000" when ((PIXEL_ON = '0') or (not active)) else 
81
+    VGA_BLUE  <= "0000" when ((RST = '0') or (not active)) else 
82
+                 "1000" when (PIXEL_ON = '0') else 
101 83
                  "1111";
102
-    VGA_GREEN <= "0000" when (RST = '0') else 
103
-                 "1000" when ((PIXEL_ON = '0') or (not active)) else 
84
+    VGA_GREEN <= "0000" when ((RST = '0') or (not active)) else 
85
+                 "1000" when (PIXEL_ON = '0') else 
104 86
                  "1111";
105 87
         
106
-    VGA_HS    <= '0' when ((RST = '0') or (X_pos < WIDTH  + X_FrontPorch) or (X_pos >= WIDTH  + X_FrontPorch + X_PulseWidth)) else 
88
+    VGA_HS    <= '0' when ((RST = '0') or (X_pos < screen_width  + X_FrontPorch) or (X_pos >= screen_width  + X_FrontPorch + X_PulseWidth)) else 
107 89
                  '1';
108
-    VGA_VS    <= '0' when ((RST = '0') or (Y_pos < HEIGHT + Y_FrontPorch) or (Y_pos >= HEIGHT + Y_FrontPorch + Y_PulseWidth)) else 
90
+    VGA_VS    <= '0' when ((RST = '0') or (Y_pos < screen_height + Y_FrontPorch) or (Y_pos >= screen_height + Y_FrontPorch + Y_PulseWidth)) else 
109 91
                  '1';
110 92
 
111 93
     X <= X_pos;

+ 0
- 5
Processeur.srcs/sources_1/new/font.vhd View File

@@ -1,11 +1,6 @@
1
-library IEEE;
2
-use IEEE.STD_LOGIC_1164.ALL;
3
-
4 1
 package font is 
5 2
 
6 3
     constant font_width  : natural := 8;
7 4
     constant font_height : natural := 8;
8 5
     
9
-    type font_T is array (0 to font_height - 1, font_width - 1 downto 0) of STD_LOGIC;
10
-    
11 6
 end package;

+ 83
- 12
Processeur.xpr View File

@@ -3,7 +3,7 @@
3 3
 <!--                                                         -->
4 4
 <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
5 5
 
6
-<Project Version="7" Minor="38" Path="/home/pfaure/Documents/PSI/Processeur/Processeur.xpr">
6
+<Project Version="7" Minor="38" Path="/home/pfaure/Documents/TESTPROCESSEUR/Processeur/Processeur/Processeur.xpr">
7 7
   <DefaultLaunch Dir="$PRUNDIR"/>
8 8
   <Configuration>
9 9
     <Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
@@ -35,7 +35,7 @@
35 35
     <Option Name="DSAVendor" Val="xilinx"/>
36 36
     <Option Name="DSABoardId" Val="basys3"/>
37 37
     <Option Name="DSANumComputeUnits" Val="16"/>
38
-    <Option Name="WTXSimLaunchSim" Val="420"/>
38
+    <Option Name="WTXSimLaunchSim" Val="470"/>
39 39
     <Option Name="WTModelSimLaunchSim" Val="0"/>
40 40
     <Option Name="WTQuestaLaunchSim" Val="0"/>
41 41
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -167,7 +167,7 @@
167 167
           <Attr Name="UsedIn" Val="simulation"/>
168 168
         </FileInfo>
169 169
       </File>
170
-      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
170
+      <File Path="$PSRCDIR/sources_1/new/ScreenProperties.vhd">
171 171
         <FileInfo>
172 172
           <Attr Name="UsedIn" Val="synthesis"/>
173 173
           <Attr Name="UsedIn" Val="simulation"/>
@@ -209,9 +209,51 @@
209 209
           <Attr Name="UsedIn" Val="simulation"/>
210 210
         </FileInfo>
211 211
       </File>
212
+      <File Path="$PSRCDIR/sources_1/new/Keyboard.vhd">
213
+        <FileInfo>
214
+          <Attr Name="UsedIn" Val="synthesis"/>
215
+          <Attr Name="UsedIn" Val="simulation"/>
216
+        </FileInfo>
217
+      </File>
218
+      <File Path="$PSRCDIR/sources_1/new/KeyboardControler.vhd">
219
+        <FileInfo>
220
+          <Attr Name="UsedIn" Val="synthesis"/>
221
+          <Attr Name="UsedIn" Val="simulation"/>
222
+        </FileInfo>
223
+      </File>
224
+      <File Path="$PSRCDIR/sources_1/new/SystemKeyboard.vhd">
225
+        <FileInfo>
226
+          <Attr Name="UsedIn" Val="synthesis"/>
227
+          <Attr Name="UsedIn" Val="simulation"/>
228
+        </FileInfo>
229
+      </File>
230
+      <File Path="$PSRCDIR/sources_1/new/SystemKeyboardScreen.vhd">
231
+        <FileInfo>
232
+          <Attr Name="UsedIn" Val="synthesis"/>
233
+          <Attr Name="UsedIn" Val="simulation"/>
234
+        </FileInfo>
235
+      </File>
236
+      <File Path="$PSRCDIR/sources_1/new/KeyboardToASCII.vhd">
237
+        <FileInfo>
238
+          <Attr Name="UsedIn" Val="synthesis"/>
239
+          <Attr Name="UsedIn" Val="simulation"/>
240
+        </FileInfo>
241
+      </File>
242
+      <File Path="$PSRCDIR/sources_1/new/Compteur_Y.vhd">
243
+        <FileInfo>
244
+          <Attr Name="UsedIn" Val="synthesis"/>
245
+          <Attr Name="UsedIn" Val="simulation"/>
246
+        </FileInfo>
247
+      </File>
248
+      <File Path="$PSRCDIR/sources_1/new/Compteur_X.vhd">
249
+        <FileInfo>
250
+          <Attr Name="UsedIn" Val="synthesis"/>
251
+          <Attr Name="UsedIn" Val="simulation"/>
252
+        </FileInfo>
253
+      </File>
212 254
       <Config>
213 255
         <Option Name="DesignMode" Val="RTL"/>
214
-        <Option Name="TopModule" Val="ScreenSystem"/>
256
+        <Option Name="TopModule" Val="SystemKeyboardScreen"/>
215 257
       </Config>
216 258
     </FileSet>
217 259
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@@ -331,13 +373,36 @@
331 373
           <Attr Name="UsedIn" Val="simulation"/>
332 374
         </FileInfo>
333 375
       </File>
376
+      <File Path="$PSRCDIR/sim_1/new/Test_KeyboardControler.vhd">
377
+        <FileInfo>
378
+          <Attr Name="UsedIn" Val="synthesis"/>
379
+          <Attr Name="UsedIn" Val="simulation"/>
380
+        </FileInfo>
381
+      </File>
382
+      <File Path="$PSRCDIR/sim_1/new/Test_Keyboard.vhd">
383
+        <FileInfo>
384
+          <Attr Name="UsedIn" Val="synthesis"/>
385
+          <Attr Name="UsedIn" Val="simulation"/>
386
+        </FileInfo>
387
+      </File>
388
+      <File Path="$PSRCDIR/sim_1/new/Test_Compteur.vhd">
389
+        <FileInfo>
390
+          <Attr Name="UsedIn" Val="synthesis"/>
391
+          <Attr Name="UsedIn" Val="simulation"/>
392
+        </FileInfo>
393
+      </File>
394
+      <File Path="$PSRCDIR/sim_1/new/Test_SystemKeyboardScreen.vhd">
395
+        <FileInfo>
396
+          <Attr Name="UsedIn" Val="synthesis"/>
397
+          <Attr Name="UsedIn" Val="simulation"/>
398
+        </FileInfo>
399
+      </File>
334 400
       <Config>
335 401
         <Option Name="DesignMode" Val="RTL"/>
336
-        <Option Name="TopModule" Val="TestTableASCII"/>
402
+        <Option Name="TopModule" Val="Test_SystemKeyboardScreen"/>
337 403
         <Option Name="TopLib" Val="xil_defaultlib"/>
338 404
         <Option Name="TransportPathDelay" Val="0"/>
339 405
         <Option Name="TransportIntDelay" Val="0"/>
340
-        <Option Name="SimMode" Val="post-implementation"/>
341 406
         <Option Name="SrcSet" Val="sources_1"/>
342 407
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
343 408
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
@@ -380,21 +445,27 @@
380 445
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
381 446
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
382 447
     </Run>
383
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="false">
448
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Spread logic throughout the device to avoid creating congested regions. (medium setting)" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="false">
384 449
       <Strategy Version="1" Minor="2">
385
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
450
+        <StratHandle Name="Congestion_SpreadLogic_medium" Flow="Vivado Implementation 2018"/>
386 451
         <Step Id="init_design"/>
387 452
         <Step Id="opt_design"/>
388 453
         <Step Id="power_opt_design"/>
389
-        <Step Id="place_design"/>
454
+        <Step Id="place_design">
455
+          <Option Id="Directive">5</Option>
456
+        </Step>
390 457
         <Step Id="post_place_power_opt_design"/>
391
-        <Step Id="phys_opt_design"/>
392
-        <Step Id="route_design"/>
458
+        <Step Id="phys_opt_design" EnableStepBool="1">
459
+          <Option Id="Directive">0</Option>
460
+        </Step>
461
+        <Step Id="route_design">
462
+          <Option Id="Directive">7</Option>
463
+        </Step>
393 464
         <Step Id="post_route_phys_opt_design"/>
394 465
         <Step Id="write_bitstream"/>
395 466
       </Strategy>
396 467
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
397
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
468
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
398 469
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
399 470
     </Run>
400 471
   </Runs>

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