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Hello world OK, TAF : Add marges, changer interligne, add keyboard

Faure Paul 3 months ago
parent
commit
0ad8e7fd55
2 changed files with 20 additions and 8 deletions
  1. 1
    1
      Processeur.srcs/sources_1/new/font.vhd
  2. 19
    7
      Processeur.xpr

+ 1
- 1
Processeur.srcs/sources_1/new/font.vhd View File

@@ -6,6 +6,6 @@ package font is
6 6
     constant font_width  : natural := 8;
7 7
     constant font_height : natural := 8;
8 8
     
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-    type font_T is array (0 to font_height - 1, 0 to font_width - 1) of STD_LOGIC;
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+    type font_T is array (0 to font_height - 1, font_width - 1 downto 0) of STD_LOGIC;
10 10
     
11 11
 end package;

+ 19
- 7
Processeur.xpr View File

@@ -1,9 +1,9 @@
1 1
 <?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)              -->
2
+<!-- Product Version: Vivado v2018.2 (64-bit)              -->
3 3
 <!--                                                         -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
4
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
5 5
 
6
-<Project Version="7" Minor="17" Path="/home/paulfaure/Documents/4A/PSI/Processeur/Processeur.xpr">
6
+<Project Version="7" Minor="38" Path="/home/pfaure/Documents/PSI/Processeur/Processeur.xpr">
7 7
   <DefaultLaunch Dir="$PRUNDIR"/>
8 8
   <Configuration>
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     <Option Name="Id" Val="c2fc77f80b2a4a04afc3ac9eb7900c74"/>
@@ -13,6 +13,7 @@
13 13
     <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
14 14
     <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
15 15
     <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
16
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
16 17
     <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
17 18
     <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
18 19
     <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
@@ -22,14 +23,16 @@
22 23
     <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
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     <Option Name="ActiveSimSet" Val="sim_1"/>
24 25
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
26
+    <Option Name="ProjectType" Val="Default"/>
25 27
     <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
26 28
     <Option Name="IPCachePermission" Val="read"/>
27 29
     <Option Name="IPCachePermission" Val="write"/>
28 30
     <Option Name="EnableCoreContainer" Val="FALSE"/>
29 31
     <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
30
-    <Option Name="IPUserFilesDir" Val="$PPRDIR/Processeur.ip_user_files"/>
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-    <Option Name="IPStaticSourceDir" Val="$PPRDIR/Processeur.ip_user_files/ipstatic"/>
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+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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     <Option Name="EnableBDX" Val="FALSE"/>
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+    <Option Name="DSAVendor" Val="xilinx"/>
33 36
     <Option Name="DSABoardId" Val="basys3"/>
34 37
     <Option Name="DSANumComputeUnits" Val="16"/>
35 38
     <Option Name="WTXSimLaunchSim" Val="420"/>
@@ -51,6 +54,7 @@
51 54
     <Option Name="XSimTimeUnit" Val="ns"/>
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     <Option Name="XSimArrayDisplayLimit" Val="64"/>
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     <Option Name="XSimTraceLimit" Val="65536"/>
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+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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   </Configuration>
55 59
   <FileSets Version="1" Minor="31">
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     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@@ -356,6 +360,9 @@
356 360
     <Simulator Name="IES">
357 361
       <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
358 362
     </Simulator>
363
+    <Simulator Name="Xcelium">
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+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
365
+    </Simulator>
359 366
     <Simulator Name="VCS">
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       <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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     </Simulator>
@@ -364,14 +371,16 @@
364 371
     </Simulator>
365 372
   </Simulators>
366 373
   <Runs Version="1" Minor="10">
367
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
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+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
368 375
       <Strategy Version="1" Minor="2">
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         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
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         <Step Id="synth_design"/>
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       </Strategy>
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
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       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
373 382
     </Run>
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-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
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+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="false">
375 384
       <Strategy Version="1" Minor="2">
376 385
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
377 386
         <Step Id="init_design"/>
@@ -384,7 +393,10 @@
384 393
         <Step Id="post_route_phys_opt_design"/>
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         <Step Id="write_bitstream"/>
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       </Strategy>
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
387 398
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
388 399
     </Run>
389 400
   </Runs>
401
+  <Board/>
390 402
 </Project>

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