Browse Source

Screen en cours

Paul Faure 3 months ago
parent
commit
c5bf8f5b1f

+ 60
- 60
Processeur.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -9,22 +9,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports CLK]
9 9
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
10 10
 
11 11
 ## Switches
12
-set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
13
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
14
-set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
15
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
16
-set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
17
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
18
-set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
19
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
20
-set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
21
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
22
-set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
23
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
24
-set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
25
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
26
-set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
27
-	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
12
+#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
13
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
14
+#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
15
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
16
+#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
17
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
18
+#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
19
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
20
+#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
21
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
22
+#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
23
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
24
+#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
25
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
26
+#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
27
+#	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
28 28
 #set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29 29
 #	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30 30
 #set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
@@ -44,22 +44,22 @@ set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
44 44
 
45 45
 
46 46
 ## LEDs
47
-set_property PACKAGE_PIN U16 [get_ports {led[0]}]
48
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
49
-set_property PACKAGE_PIN E19 [get_ports {led[1]}]
50
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
51
-set_property PACKAGE_PIN U19 [get_ports {led[2]}]
52
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
53
-set_property PACKAGE_PIN V19 [get_ports {led[3]}]
54
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
55
-set_property PACKAGE_PIN W18 [get_ports {led[4]}]
56
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
57
-set_property PACKAGE_PIN U15 [get_ports {led[5]}]
58
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
59
-set_property PACKAGE_PIN U14 [get_ports {led[6]}]
60
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
61
-set_property PACKAGE_PIN V14 [get_ports {led[7]}]
62
-	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
47
+#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
48
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
49
+#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
50
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
51
+#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
52
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
53
+#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
54
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
55
+#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
56
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
57
+#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
58
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
59
+#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
60
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
61
+#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
62
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
63 63
 #set_property PACKAGE_PIN V13 [get_ports {led[8]}]
64 64
 	#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
65 65
 #set_property PACKAGE_PIN V3 [get_ports {led[9]}]
@@ -233,34 +233,34 @@ set_property PACKAGE_PIN U18 [get_ports btnC]
233 233
 
234 234
 
235 235
 ##VGA Connector
236
-#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
237
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
238
-#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
239
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
240
-#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
241
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
242
-#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
243
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
244
-#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
245
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
246
-#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
247
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
248
-#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
249
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
250
-#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
251
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
252
-#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
253
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
254
-#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
255
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
256
-#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
257
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
258
-#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
259
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
260
-#set_property PACKAGE_PIN P19 [get_ports Hsync]
261
-	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
262
-#set_property PACKAGE_PIN R19 [get_ports Vsync]
263
-	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
236
+set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
237
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
238
+set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
239
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
240
+set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
241
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
242
+set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
243
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
244
+set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
245
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
246
+set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
247
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
248
+set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
249
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
250
+set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
251
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
252
+set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
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+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
254
+set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
255
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
256
+set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
257
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
258
+set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
259
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
260
+set_property PACKAGE_PIN P19 [get_ports Hsync]
261
+	set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
262
+set_property PACKAGE_PIN R19 [get_ports Vsync]
263
+	set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
264 264
 
265 265
 
266 266
 ##USB-RS232 Interface

+ 63
- 0
Processeur.srcs/sim_1/new/TestTableASCII.vhd View File

@@ -0,0 +1,63 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 29.06.2021 16:16:32
6
+-- Design Name: 
7
+-- Module Name: TestTableASCII - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+use work.font.all;
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+
27
+-- Uncomment the following library declaration if using
28
+-- arithmetic functions with Signed or Unsigned values
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+--use IEEE.NUMERIC_STD.ALL;
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+
31
+-- Uncomment the following library declaration if instantiating
32
+-- any Xilinx leaf cells in this code.
33
+--library UNISIM;
34
+--use UNISIM.VComponents.all;
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+
36
+entity TestTableASCII is
37
+--  Port ( );
38
+end TestTableASCII;
39
+
40
+architecture Behavioral of TestTableASCII is
41
+
42
+    component TableASCII is
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+    port ( CodeASCII : in Natural;
44
+           Font  : out font_T);
45
+    end component;
46
+
47
+    signal my_CodeASCII : Natural := 0;
48
+    signal my_Font      : font_T := (others => (others => '0'));
49
+    
50
+begin
51
+
52
+    instance : TableASCII 
53
+    port map( CodeASCII => my_CodeASCII,
54
+              Font      => my_Font
55
+             );
56
+    
57
+    process 
58
+    begin   
59
+        my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
60
+        wait;
61
+    end process;  
62
+
63
+end Behavioral;

+ 96
- 0
Processeur.srcs/sim_1/new/Test_Ecran.vhd View File

@@ -0,0 +1,96 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 11:25:08
6
+-- Design Name: 
7
+-- Module Name: Test_Ecran - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_Ecran is
35
+--  Port ( );
36
+end Test_Ecran;
37
+
38
+architecture Behavioral of Test_Ecran is
39
+
40
+    component Ecran is
41
+    Generic (  HEIGHT         : Natural;
42
+               WIDTH          : Natural;
43
+               CaracterHeight : Natural;
44
+               CaracterWidht  : Natural            
45
+    );
46
+    Port (     CLK            : in STD_LOGIC;
47
+               RST            : in STD_LOGIC;
48
+               Data_Av        : in STD_LOGIC;
49
+               Data_IN        : in STD_LOGIC_VECTOR (6 downto 0);
50
+               X              : in Natural;
51
+               Y              : in Natural;
52
+               OUT_ON         : out STD_LOGIC_VECTOR (6 downto 0));
53
+    end component; 
54
+    
55
+    
56
+    signal my_CLK : STD_LOGIC := '0';
57
+    signal my_RST : STD_LOGIC := '1';
58
+    signal my_Data_Av : STD_LOGIC := '0';
59
+    signal my_Data_IN : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
60
+    signal my_X : Natural := 0;
61
+    signal my_Y : Natural := 0;
62
+    signal my_OUT_ON : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
63
+    
64
+    constant CLK_period : time := 10 ns;
65
+
66
+begin
67
+    instance : Ecran 
68
+    generic map(  HEIGHT => 14,
69
+                  WIDTH => 22,
70
+                  CaracterHeight => 4,
71
+                  CaracterWidht => 5          
72
+    )
73
+    port map(  CLK => my_CLK,
74
+               RST => my_RST,
75
+               Data_Av => my_Data_Av,
76
+               Data_IN => my_Data_IN,
77
+               X => my_X,
78
+               Y => my_Y,
79
+               OUT_ON => my_OUT_ON);
80
+
81
+    CLK_process : process
82
+    begin
83
+        my_CLK <= '0';
84
+        wait for CLK_period/2;
85
+        my_CLK <= '1';
86
+        wait for CLK_period/2;
87
+    end process;
88
+
89
+    process 
90
+    begin   
91
+    my_Data_Av <= '1' after 0 ns;
92
+    my_Data_IN <= "0000001" after 0 ns, "0000010" after 40 ns, "0000011" after 80 ns, "0000100" after 120 ns, "0001101" after 140 ns, "0000101" after 150 ns, "0000000" after 170 ns, "0000001" after 180 ns, "0000010" after 220 ns;
93
+    wait;
94
+    end process;  
95
+      
96
+end Behavioral;

+ 1
- 2
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd View File

@@ -100,8 +100,7 @@ begin
100 100
                  IN_Instruction => my_IN_Instruction,
101 101
                  OUT_A => my_OUT_A,
102 102
                  OUT_B => my_OUT_B,
103
-                 OUT_Instruction => my_OUT_Instruction,
104
-                 OUT_AddrRetour => my_OUT_AddrRetour);
103
+                 OUT_Instruction => my_OUT_Instruction);
105 104
     
106 105
     CLK_process :process
107 106
     begin

+ 90
- 0
Processeur.srcs/sim_1/new/Test_ScreenSystem.vhd View File

@@ -0,0 +1,90 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 29.06.2021 08:40:33
6
+-- Design Name: 
7
+-- Module Name: Test_ScreenSystem - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity Test_ScreenSystem is
35
+--  Port ( );
36
+end Test_ScreenSystem;
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+
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+architecture Behavioral of Test_ScreenSystem is
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+
40
+    component ScreenSystem is
41
+      Port (  vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
42
+              vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
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+              vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
44
+              Hsync    : out STD_LOGIC;
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+              Vsync    : out STD_LOGIC;
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+              
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+              
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+              btnC : in STD_LOGIC;
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+              CLK  : in  STD_LOGIC
50
+       );
51
+     end component;
52
+       
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+    signal my_vgaRed   : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
54
+    signal my_vgaBlue  : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
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+    signal my_vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
56
+    signal my_Hsync    : STD_LOGIC := '0';
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+    signal my_Vsync    : STD_LOGIC := '0';
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+    
59
+    
60
+    signal my_btnC : STD_LOGIC := '0';
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+    signal my_CLK  : STD_LOGIC := '0';
62
+
63
+    constant CLK_period : time := 10 ns;
64
+
65
+begin
66
+    instance : ScreenSystem
67
+    port map    (
68
+                 vgaRed => my_vgaRed,
69
+                 vgaBlue => my_vgaBlue,
70
+                 vgaGreen => my_vgaGreen,
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+                 Hsync => my_Hsync,
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+                 Vsync => my_Vsync,
73
+                 btnC => my_btnC,
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+                 CLK => my_CLK
75
+                );
76
+    
77
+    CLK_process :process
78
+    begin
79
+        my_CLK <= '0';
80
+        wait for CLK_period/2;
81
+        my_CLK <= '1';
82
+        wait for CLK_period/2;
83
+    end process;
84
+    
85
+    process 
86
+    begin   
87
+        wait;
88
+    end process;  
89
+      
90
+end Behavioral;

+ 108
- 0
Processeur.srcs/sim_1/new/Test_VGAControler.vhd View File

@@ -0,0 +1,108 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 15:55:57
6
+-- Design Name: 
7
+-- Module Name: Test_VGAControler - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+entity Test_VGAControler is
26
+--  Port ( );
27
+end Test_VGAControler;
28
+
29
+architecture Behavioral of Test_VGAControler is
30
+
31
+    component VGAControler is
32
+    Generic (  HEIGHT    : Natural;
33
+               WIDTH     : Natural;
34
+               X_PulseWidth : Natural;
35
+               X_FrontPorch : Natural;
36
+               X_BackPorch  : Natural;
37
+               Y_PulseWidth : Natural;
38
+               Y_FrontPorch : Natural;
39
+               Y_BackPorch  : Natural              
40
+    );
41
+    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
42
+               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
43
+               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
44
+               VGA_HS    : out STD_LOGIC;
45
+               VGA_VS    : out STD_LOGIC;
46
+               
47
+               X         : out Natural;
48
+               Y         : out Natural;
49
+               PIXEL_ON  : in STD_LOGIC;
50
+               
51
+               CLK       : in STD_LOGIC;
52
+               RST       : in STD_LOGIC);
53
+    end component; 
54
+    
55
+    
56
+    signal my_VGA_RED   : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
57
+    signal my_VGA_BLUE  : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
58
+    signal my_VGA_GREEN : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
59
+    signal my_VGA_HS    : STD_LOGIC := '0';
60
+    signal my_VGA_VS    : STD_LOGIC := '0';
61
+   
62
+    signal my_X         : Natural := 0;
63
+    signal my_Y         : Natural := 0;
64
+    signal my_PIXEL_ON  : STD_LOGIC := '0';
65
+   
66
+    signal my_CLK       : STD_LOGIC := '0';
67
+    signal my_RST       : STD_LOGIC := '1';
68
+    
69
+    constant CLK_period : time := 10 ns;
70
+
71
+begin
72
+    instance : VGAControler 
73
+    generic map(  HEIGHT => 4,
74
+                  WIDTH =>10,
75
+                  X_PulseWidth => 2,
76
+                  X_FrontPorch => 1,
77
+                  X_BackPorch  => 3,
78
+                  Y_PulseWidth => 1,
79
+                  Y_FrontPorch => 1,
80
+                  Y_BackPorch  => 1)
81
+    port map(  VGA_RED   => my_VGA_RED,
82
+               VGA_BLUE  => my_VGA_BLUE,
83
+               VGA_GREEN => my_VGA_GREEN,
84
+               VGA_HS    => my_VGA_HS,
85
+               VGA_VS    => my_VGA_VS,
86
+                 
87
+               X         => my_X,
88
+               Y         => my_Y,
89
+               PIXEL_ON  => my_PIXEL_ON,
90
+                 
91
+               CLK       => my_CLK,
92
+               RST       => my_RST);
93
+
94
+    CLK_process : process
95
+    begin
96
+        my_CLK <= '0';
97
+        wait for CLK_period/2;
98
+        my_CLK <= '1';
99
+        wait for CLK_period/2;
100
+    end process;
101
+
102
+    process 
103
+    begin   
104
+        my_PIXEL_ON <= '1' after 50 ns, '0' after 100 ns, '1' after 150 ns, '0' after 200 ns;
105
+        wait;
106
+    end process;  
107
+      
108
+end Behavioral;

+ 61
- 0
Processeur.srcs/sources_1/new/Compteur.vhd View File

@@ -0,0 +1,61 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 14:59:39
6
+-- Design Name: 
7
+-- Module Name: Compteur - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+entity Compteur is
26
+    Generic (Min : Natural;
27
+             Max : Natural
28
+            );
29
+    Port    (CLK : in STD_LOGIC;
30
+             RST : in STD_LOGIC;
31
+             Value : out Natural;
32
+             Carry : out STD_LOGIC);
33
+end Compteur;
34
+
35
+architecture Behavioral of Compteur is
36
+
37
+    signal current : Natural := Min;
38
+    signal InternCarry : STD_LOGIC := '0';
39
+    
40
+begin
41
+
42
+    process
43
+    begin
44
+        wait until CLK'event and CLK = '1';
45
+        if (RST = '0') then
46
+            current <= Min;
47
+        else 
48
+            current <= current + 1;
49
+            if (current = Max) then
50
+                InternCarry <= '1'; 
51
+                current <= Min;
52
+            else 
53
+                InternCarry <= '0';
54
+            end if;
55
+        end if;
56
+    end process;
57
+    
58
+    Value <= current;
59
+    Carry <= InternCarry;
60
+    
61
+end Behavioral;

+ 118
- 0
Processeur.srcs/sources_1/new/Ecran.vhd View File

@@ -0,0 +1,118 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 09:20:00
6
+-- Design Name: 
7
+-- Module Name: Ecran - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+use work.font.all;
26
+
27
+    entity Ecran is
28
+        Generic (  HEIGHT         : Natural;
29
+                   WIDTH          : Natural        
30
+        );
31
+        Port (     CLK            : in STD_LOGIC;
32
+                   RST            : in STD_LOGIC;
33
+                   Data_Av        : in STD_LOGIC;
34
+                   Data_IN        : in Natural;
35
+                   X              : in Natural;
36
+                   Y              : in Natural;
37
+                   OUT_ON         : out STD_LOGIC);
38
+    end Ecran;
39
+
40
+architecture Behavioral of Ecran is
41
+
42
+    component TableASCII is
43
+        Port ( CodeASCII : Natural;
44
+               Font : out font_T);
45
+    end component;
46
+
47
+    constant Flush : Natural := 0;
48
+    constant RetourChariot : Natural := 13;
49
+
50
+    constant CaracterHeight : Natural := 16;
51
+    constant CaracterWidht  : Natural := 16;
52
+    constant HeightSize : Natural := HEIGHT/CaracterHeight;
53
+    constant WidthSize  : Natural := WIDTH/CaracterWidht;
54
+    
55
+    type T_Ligne is array (0 to WidthSize - 1) of Natural;
56
+    type T_Ecran is array (0 to HeightSize - 1) of T_Ligne;
57
+    
58
+    signal Ecran : T_Ecran := (others => (0 => 72, 1 => 101, 2 => 108, 3 => 108, 4 => 111, 5 => 32, 6 => 87, 7 => 111, 8 => 114, 9 => 108, 10 => 100, others => 0));
59
+    signal L : Natural := 0;
60
+    signal C : Natural := 0;
61
+    signal InitialL : Natural := 0;
62
+    signal Full : BOOLEAN := false;
63
+    
64
+    signal CurrentCodeASCII : Natural := 0;
65
+    signal CurrentFont : font_T;
66
+    
67
+begin
68
+
69
+    instance_TableASCII : TableASCII
70
+    port map (CodeASCII => CurrentCodeASCII,
71
+              Font => CurrentFont);
72
+
73
+    process
74
+    begin
75
+        wait until CLK'event and CLK='1';
76
+        if (RST = '0') then
77
+            Ecran <= (others => (others => 0));
78
+            L <= 0;
79
+            C <= 0;
80
+            InitialL <= 0;
81
+            Full <= false;
82
+        elsif (Data_Av = '1') then
83
+            if (Data_IN = Flush) then
84
+                Ecran <= (others => (others => 0));
85
+                L <= 0;
86
+                C <= 0;
87
+                InitialL <= 0;
88
+                Full <= false;
89
+            elsif (Data_IN = RetourChariot) then
90
+                C <= 0;
91
+                L <= (L + 1) mod HeightSize;
92
+                if ((L + 1) mod HeightSize = 0 or Full) then
93
+                    Full <= true;
94
+                    InitialL <= (InitialL + 1) mod HeightSize;
95
+                    Ecran((L + 1) mod HeightSize) <= (others => 0);
96
+                end if;   
97
+            else
98
+                Ecran(L)(C) <= Data_IN;
99
+                C <= C + 1;
100
+                if (C + 1 = WidthSize) then
101
+                    C <= 0;
102
+                    L <= (L + 1) mod HeightSize;
103
+                    if ((L + 1) mod HeightSize = 0 or Full) then
104
+                        Full <= true;
105
+                        InitialL <= (InitialL + 1) mod HeightSize;
106
+                        Ecran((L + 1) mod HeightSize) <= (others => 0);
107
+                    end if;   
108
+                end if;
109
+            end if;
110
+        end if;            
111
+    end process;
112
+    
113
+    CurrentCodeASCII <= Ecran((Y/CaracterHeight + InitialL) mod HeightSize)(X/CaracterWidht) when (Y/CaracterHeight < HeightSize and X/CaracterWidht < WidthSize and RST='1') else
114
+                        0;
115
+
116
+    OUT_ON <= CurrentFont((Y mod CaracterHeight) / (CaracterHeight / font_height), (X mod CaracterWidht) / (CaracterWidht / font_width));
117
+
118
+end Behavioral;

+ 169
- 0
Processeur.srcs/sources_1/new/ScreenSystem.vhd View File

@@ -0,0 +1,169 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 17:27:26
6
+-- Design Name: 
7
+-- Module Name: ScreenSystem - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity ScreenSystem is
35
+  Port (  vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
36
+          vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
37
+          vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
38
+          Hsync    : out STD_LOGIC;
39
+          Vsync    : out STD_LOGIC;
40
+          
41
+          
42
+          btnC : in STD_LOGIC;
43
+          CLK       : in  STD_LOGIC
44
+       );
45
+end ScreenSystem;
46
+
47
+architecture Behavioral of ScreenSystem is
48
+
49
+    component VGAControler is
50
+    Generic (  HEIGHT    : Natural;
51
+               WIDTH     : Natural;
52
+               X_PulseWidth : Natural;
53
+               X_FrontPorch : Natural;
54
+               X_BackPorch  : Natural;
55
+               Y_PulseWidth : Natural;
56
+               Y_FrontPorch : Natural;
57
+               Y_BackPorch  : Natural              
58
+    );
59
+    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
60
+               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
61
+               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
62
+               VGA_HS    : out STD_LOGIC;
63
+               VGA_VS    : out STD_LOGIC;
64
+               
65
+               X         : out Natural;
66
+               Y         : out Natural;
67
+               PIXEL_ON  : in STD_LOGIC;
68
+               
69
+               CLK       : in STD_LOGIC;
70
+               RST       : in STD_LOGIC);
71
+    end component; 
72
+    
73
+    component clk_wiz_0
74
+    port
75
+     (-- Clock in ports
76
+      clk_in1           : in     std_logic;
77
+      -- Clock out ports
78
+      clk_out1          : out    std_logic
79
+     );
80
+    end component;
81
+    
82
+    component Ecran is
83
+        Generic (  HEIGHT         : Natural;
84
+                   WIDTH          : Natural        
85
+        );
86
+        Port (     CLK            : in STD_LOGIC;
87
+                   RST            : in STD_LOGIC;
88
+                   Data_Av        : in STD_LOGIC;
89
+                   Data_IN        : in Natural;
90
+                   X              : in Natural;
91
+                   Y              : in Natural;
92
+                   OUT_ON         : out STD_LOGIC);
93
+    end component;
94
+    
95
+    signal my_X : Natural := 0;
96
+    signal my_Y : Natural := 0;
97
+    signal my_PIXEL_ON : STD_LOGIC := '0';
98
+    
99
+    signal compteur : natural := 0;
100
+    signal my_CLK : STD_LOGIC := '0';
101
+    signal RST : STD_LOGIC;
102
+
103
+begin
104
+
105
+    instanceVGA : VGAControler 
106
+--    generic map(  HEIGHT => 480,
107
+--                  WIDTH => 640,
108
+--                  X_PulseWidth => 96,
109
+--                  X_FrontPorch => 16,
110
+--                  X_BackPorch  => 48,
111
+--                  Y_PulseWidth => 2,
112
+--                  Y_FrontPorch => 10,
113
+--                  Y_BackPorch  => 33)
114
+    generic map(  HEIGHT => 1024,
115
+                  WIDTH => 1280,
116
+                  X_PulseWidth => 112,
117
+                  X_FrontPorch => 48,
118
+                  X_BackPorch  => 248,
119
+                  Y_PulseWidth => 3,
120
+                  Y_FrontPorch => 1,
121
+                  Y_BackPorch  => 38)
122
+    port map(  VGA_RED   => vgaRed,
123
+               VGA_BLUE  => vgaBlue,
124
+               VGA_GREEN => vgaGreen,
125
+               VGA_HS    => Hsync,
126
+               VGA_VS    => Vsync,
127
+                 
128
+               X         => my_X,
129
+               Y         => my_Y,
130
+               PIXEL_ON  => my_PIXEL_ON,
131
+                 
132
+               CLK       => my_CLK,
133
+               RST       => RST);
134
+               
135
+    
136
+    clk_wiz_0_inst : clk_wiz_0
137
+    port map (
138
+              clk_in1 => CLK,
139
+              clk_out1 => my_CLK
140
+             );
141
+          
142
+--    process 
143
+--    begin
144
+--        wait until CLK'event and CLK = '1';
145
+--        compteur <= (compteur + 1) mod 4;
146
+--        if (compteur = 0) then
147
+--            my_CLK <= '1';
148
+--        elsif (compteur = 2) then
149
+--            my_CLK <= '0';
150
+--        end if;
151
+--    end process;
152
+
153
+    instance_Ecran : Ecran
154
+    generic map (  HEIGHT => 1024,
155
+                   WIDTH  => 1280        
156
+    )
157
+    port map (     CLK     => CLK,
158
+                   RST     => RST,
159
+                   Data_Av => '0',
160
+                   Data_IN => 0,
161
+                   X => my_X,
162
+                   Y => my_Y,
163
+                   OUT_ON => my_PIXEL_ON);
164
+
165
+    -- Gestion du RST (inversion d'état)
166
+    RST <= '1' when btnC = '0' else
167
+           '0';
168
+
169
+end Behavioral;

+ 179
- 0
Processeur.srcs/sources_1/new/TableASCII.vhd View File

@@ -0,0 +1,179 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 09:20:00
6
+-- Design Name: 
7
+-- Module Name: TableASCII - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+Library UNISIM;
26
+use UNISIM.vcomponents.all;
27
+
28
+Library UNIMACRO;
29
+use UNIMACRO.vcomponents.all;
30
+
31
+use work.font.all;
32
+
33
+
34
+
35
+entity TableASCII is
36
+    Port ( CodeASCII : Natural;
37
+           Font : out font_T);
38
+end TableASCII;
39
+
40
+architecture Behavioral of TableASCII is
41
+
42
+    type FontMemory_T is array (0 to 127) of font_T;
43
+    
44
+    signal FontMemory : FontMemory_T := (
45
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0000 (nul)
46
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0001
47
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0002
48
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0003
49
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0004
50
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0005
51
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0006
52
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0007
53
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0008
54
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0009
55
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000A
56
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000B
57
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000C
58
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000D
59
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000E
60
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+000F
61
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0010
62
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0011
63
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0012
64
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0013
65
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0014
66
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0015
67
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0016
68
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0017
69
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0018
70
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0019
71
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001A
72
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001B
73
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001C
74
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001D
75
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001E
76
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+001F
77
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0020 (space)
78
+        ( x"18", x"3C", x"3C", x"18", x"18", x"00", x"18", x"00"),   -- U+0021 (!)
79
+        ( x"36", x"36", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+0022 (")
80
+        ( x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"),   -- U+0023 (#)
81
+        ( x"0C", x"3E", x"03", x"1E", x"30", x"1F", x"0C", x"00"),   -- U+0024 ($)
82
+        ( x"00", x"63", x"33", x"18", x"0C", x"66", x"63", x"00"),   -- U+0025 (%)
83
+        ( x"1C", x"36", x"1C", x"6E", x"3B", x"33", x"6E", x"00"),   -- U+0026 (&)
84
+        ( x"06", x"06", x"03", x"00", x"00", x"00", x"00", x"00"),   -- U+0027 (')
85
+        ( x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00"),   -- U+0028 (()
86
+        ( x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00"),   -- U+0029 ())
87
+        ( x"00", x"66", x"3C", x"FF", x"3C", x"66", x"00", x"00"),   -- U+002A (*)
88
+        ( x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00"),   -- U+002B (+)
89
+        ( x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06"),   -- U+002C (,)
90
+        ( x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00"),   -- U+002D (-)
91
+        ( x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00"),   -- U+002E (.)
92
+        ( x"60", x"30", x"18", x"0C", x"06", x"03", x"01", x"00"),   -- U+002F (/)
93
+        ( x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00"),   -- U+0030 (0)
94
+        ( x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00"),   -- U+0031 (1)
95
+        ( x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00"),   -- U+0032 (2)
96
+        ( x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00"),   -- U+0033 (3)
97
+        ( x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00"),   -- U+0034 (4)
98
+        ( x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00"),   -- U+0035 (5)
99
+        ( x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00"),   -- U+0036 (6)
100
+        ( x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00"),   -- U+0037 (7)
101
+        ( x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00"),   -- U+0038 (8)
102
+        ( x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00"),   -- U+0039 (9)
103
+        ( x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00"),   -- U+003A (:)
104
+        ( x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"06"),   -- U+003B (--)
105
+        ( x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00"),   -- U+003C (<)
106
+        ( x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00"),   -- U+003D (=)
107
+        ( x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00"),   -- U+003E (>)
108
+        ( x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00"),   -- U+003F (?)
109
+        ( x"3E", x"63", x"7B", x"7B", x"7B", x"03", x"1E", x"00"),   -- U+0040 (@)
110
+        ( x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00"),   -- U+0041 (A)
111
+        ( x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00"),   -- U+0042 (B)
112
+        ( x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00"),   -- U+0043 (C)
113
+        ( x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00"),   -- U+0044 (D)
114
+        ( x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00"),   -- U+0045 (E)
115
+        ( x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00"),   -- U+0046 (F)
116
+        ( x"3C", x"66", x"03", x"03", x"73", x"66", x"7C", x"00"),   -- U+0047 (G)
117
+        ( x"33", x"33", x"33", x"3F", x"33", x"33", x"33", x"00"),   -- U+0048 (H)
118
+        ( x"1E", x"0C", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+0049 (I)
119
+        ( x"78", x"30", x"30", x"30", x"33", x"33", x"1E", x"00"),   -- U+004A (J)
120
+        ( x"67", x"66", x"36", x"1E", x"36", x"66", x"67", x"00"),   -- U+004B (K)
121
+        ( x"0F", x"06", x"06", x"06", x"46", x"66", x"7F", x"00"),   -- U+004C (L)
122
+        ( x"63", x"77", x"7F", x"7F", x"6B", x"63", x"63", x"00"),   -- U+004D (M)
123
+        ( x"63", x"67", x"6F", x"7B", x"73", x"63", x"63", x"00"),   -- U+004E (N)
124
+        ( x"1C", x"36", x"63", x"63", x"63", x"36", x"1C", x"00"),   -- U+004F (O)
125
+        ( x"3F", x"66", x"66", x"3E", x"06", x"06", x"0F", x"00"),   -- U+0050 (P)
126
+        ( x"1E", x"33", x"33", x"33", x"3B", x"1E", x"38", x"00"),   -- U+0051 (Q)
127
+        ( x"3F", x"66", x"66", x"3E", x"36", x"66", x"67", x"00"),   -- U+0052 (R)
128
+        ( x"1E", x"33", x"07", x"0E", x"38", x"33", x"1E", x"00"),   -- U+0053 (S)
129
+        ( x"3F", x"2D", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+0054 (T)
130
+        ( x"33", x"33", x"33", x"33", x"33", x"33", x"3F", x"00"),   -- U+0055 (U)
131
+        ( x"33", x"33", x"33", x"33", x"33", x"1E", x"0C", x"00"),   -- U+0056 (V)
132
+        ( x"63", x"63", x"63", x"6B", x"7F", x"77", x"63", x"00"),   -- U+0057 (W)
133
+        ( x"63", x"63", x"36", x"1C", x"1C", x"36", x"63", x"00"),   -- U+0058 (X)
134
+        ( x"33", x"33", x"33", x"1E", x"0C", x"0C", x"1E", x"00"),   -- U+0059 (Y)
135
+        ( x"7F", x"63", x"31", x"18", x"4C", x"66", x"7F", x"00"),   -- U+005A (Z)
136
+        ( x"1E", x"06", x"06", x"06", x"06", x"06", x"1E", x"00"),   -- U+005B ([)
137
+        ( x"03", x"06", x"0C", x"18", x"30", x"60", x"40", x"00"),   -- U+005C (\)
138
+        ( x"1E", x"18", x"18", x"18", x"18", x"18", x"1E", x"00"),   -- U+005D (])
139
+        ( x"08", x"1C", x"36", x"63", x"00", x"00", x"00", x"00"),   -- U+005E (^)
140
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"FF"),   -- U+005F (_)
141
+        ( x"0C", x"0C", x"18", x"00", x"00", x"00", x"00", x"00"),   -- U+0060 (`)
142
+        ( x"00", x"00", x"1E", x"30", x"3E", x"33", x"6E", x"00"),   -- U+0061 (a)
143
+        ( x"07", x"06", x"06", x"3E", x"66", x"66", x"3B", x"00"),   -- U+0062 (b)
144
+        ( x"00", x"00", x"1E", x"33", x"03", x"33", x"1E", x"00"),   -- U+0063 (c)
145
+        ( x"38", x"30", x"30", x"3e", x"33", x"33", x"6E", x"00"),   -- U+0064 (d)
146
+        ( x"00", x"00", x"1E", x"33", x"3f", x"03", x"1E", x"00"),   -- U+0065 (e)
147
+        ( x"1C", x"36", x"06", x"0f", x"06", x"06", x"0F", x"00"),   -- U+0066 (f)
148
+        ( x"00", x"00", x"6E", x"33", x"33", x"3E", x"30", x"1F"),   -- U+0067 (g)
149
+        ( x"07", x"06", x"36", x"6E", x"66", x"66", x"67", x"00"),   -- U+0068 (h)
150
+        ( x"0C", x"00", x"0E", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+0069 (i)
151
+        ( x"30", x"00", x"30", x"30", x"30", x"33", x"33", x"1E"),   -- U+006A (j)
152
+        ( x"07", x"06", x"66", x"36", x"1E", x"36", x"67", x"00"),   -- U+006B (k)
153
+        ( x"0E", x"0C", x"0C", x"0C", x"0C", x"0C", x"1E", x"00"),   -- U+006C (l)
154
+        ( x"00", x"00", x"33", x"7F", x"7F", x"6B", x"63", x"00"),   -- U+006D (m)
155
+        ( x"00", x"00", x"1F", x"33", x"33", x"33", x"33", x"00"),   -- U+006E (n)
156
+        ( x"00", x"00", x"1E", x"33", x"33", x"33", x"1E", x"00"),   -- U+006F (o)
157
+        ( x"00", x"00", x"3B", x"66", x"66", x"3E", x"06", x"0F"),   -- U+0070 (p)
158
+        ( x"00", x"00", x"6E", x"33", x"33", x"3E", x"30", x"78"),   -- U+0071 (q)
159
+        ( x"00", x"00", x"3B", x"6E", x"66", x"06", x"0F", x"00"),   -- U+0072 (r)
160
+        ( x"00", x"00", x"3E", x"03", x"1E", x"30", x"1F", x"00"),   -- U+0073 (s)
161
+        ( x"08", x"0C", x"3E", x"0C", x"0C", x"2C", x"18", x"00"),   -- U+0074 (t)
162
+        ( x"00", x"00", x"33", x"33", x"33", x"33", x"6E", x"00"),   -- U+0075 (u)
163
+        ( x"00", x"00", x"33", x"33", x"33", x"1E", x"0C", x"00"),   -- U+0076 (v)
164
+        ( x"00", x"00", x"63", x"6B", x"7F", x"7F", x"36", x"00"),   -- U+0077 (w)
165
+        ( x"00", x"00", x"63", x"36", x"1C", x"36", x"63", x"00"),   -- U+0078 (x)
166
+        ( x"00", x"00", x"33", x"33", x"33", x"3E", x"30", x"1F"),   -- U+0079 (y)
167
+        ( x"00", x"00", x"3F", x"19", x"0C", x"26", x"3F", x"00"),   -- U+007A (z)
168
+        ( x"38", x"0C", x"0C", x"07", x"0C", x"0C", x"38", x"00"),   -- U+007B (()
169
+        ( x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00"),   -- U+007C (|)
170
+        ( x"07", x"0C", x"0C", x"38", x"0C", x"0C", x"07", x"00"),   -- U+007D ())
171
+        ( x"6E", x"3B", x"00", x"00", x"00", x"00", x"00", x"00"),   -- U+007E (~)
172
+        ( x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00")    -- U+007F
173
+    );
174
+    
175
+begin
176
+
177
+   Font <= FontMemory(CodeASCII);
178
+   
179
+end Behavioral;

+ 114
- 0
Processeur.srcs/sources_1/new/VGAControler.vhd View File

@@ -0,0 +1,114 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 28.06.2021 09:20:00
6
+-- Design Name: 
7
+-- Module Name: VGAControler - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity VGAControler is
35
+    Generic (  HEIGHT    : Natural;
36
+               WIDTH     : Natural;
37
+               X_PulseWidth : Natural;
38
+               X_FrontPorch : Natural;
39
+               X_BackPorch  : Natural;
40
+               Y_PulseWidth : Natural;
41
+               Y_FrontPorch : Natural;
42
+               Y_BackPorch  : Natural              
43
+    );
44
+    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
45
+               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
46
+               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
47
+               VGA_HS    : out STD_LOGIC;
48
+               VGA_VS    : out STD_LOGIC;
49
+               
50
+               X         : out Natural;
51
+               Y         : out Natural;
52
+               PIXEL_ON  : in STD_LOGIC;
53
+               
54
+               CLK       : in STD_LOGIC;
55
+               RST       : in STD_LOGIC);
56
+end VGAControler;
57
+
58
+architecture Behavioral of VGAControler is
59
+
60
+    component Compteur is
61
+    Generic (Min : Natural;
62
+             Max : Natural
63
+            );
64
+    Port    (CLK : in STD_LOGIC;
65
+             RST : in STD_LOGIC;
66
+             Value : out Natural;
67
+             Carry : out STD_LOGIC);
68
+    end component;
69
+    
70
+    signal X_pos : Natural := 0;
71
+    signal Y_pos : Natural := 0;
72
+    signal Y_CLK : STD_LOGIC := '0';
73
+    signal Screen_CLK : STD_LOGIC := '0';
74
+    signal active : BOOLEAN := false;
75
+
76
+begin
77
+
78
+    X_Compteur : Compteur 
79
+    generic map (Min => 0,
80
+                 Max => WIDTH + X_PulseWidth + X_FrontPorch + X_BackPorch - 1)
81
+    port map    (CLK => CLK,
82
+                 RST => RST,
83
+                 Value => X_pos,
84
+                 Carry => Y_CLK);
85
+                 
86
+    Y_Compteur : Compteur 
87
+    generic map (Min => 0,
88
+                 Max => HEIGHT + Y_PulseWidth + Y_FrontPorch + Y_BackPorch - 1)
89
+    port map    (CLK => Y_CLK,
90
+                 RST => RST,
91
+                 Value => Y_pos,
92
+                 Carry => Screen_CLK);
93
+                 
94
+    active <= ((X_pos < WIDTH) and (Y_pos < HEIGHT));
95
+                 
96
+    VGA_RED   <= "0000" when (RST = '0') else 
97
+                 "1000" when ((PIXEL_ON = '0') or (not active)) else 
98
+                 "1111";
99
+    VGA_BLUE  <= "0000" when (RST = '0') else 
100
+                 "1000" when ((PIXEL_ON = '0') or (not active)) else 
101
+                 "1111";
102
+    VGA_GREEN <= "0000" when (RST = '0') else 
103
+                 "1000" when ((PIXEL_ON = '0') or (not active)) else 
104
+                 "1111";
105
+        
106
+    VGA_HS    <= '0' when ((RST = '0') or (X_pos < WIDTH  + X_FrontPorch) or (X_pos >= WIDTH  + X_FrontPorch + X_PulseWidth)) else 
107
+                 '1';
108
+    VGA_VS    <= '0' when ((RST = '0') or (Y_pos < HEIGHT + Y_FrontPorch) or (Y_pos >= HEIGHT + Y_FrontPorch + Y_PulseWidth)) else 
109
+                 '1';
110
+
111
+    X <= X_pos;
112
+    Y <= Y_pos;
113
+
114
+end Behavioral;

+ 107
- 0
Processeur.srcs/sources_1/new/clk_wiz_0.vhd View File

@@ -0,0 +1,107 @@
1
+-- file: clk_wiz_0.vhd
2
+-- 
3
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
4
+-- 
5
+-- This file contains confidential and proprietary information
6
+-- of Xilinx, Inc. and is protected under U.S. and
7
+-- international copyright and other intellectual property
8
+-- laws.
9
+-- 
10
+-- DISCLAIMER
11
+-- This disclaimer is not a license and does not grant any
12
+-- rights to the materials distributed herewith. Except as
13
+-- otherwise provided in a valid license issued to you by
14
+-- Xilinx, and to the maximum extent permitted by applicable
15
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
+-- (2) Xilinx shall not be liable (whether in contract or tort,
21
+-- including negligence, or under any other theory of
22
+-- liability) for any loss or damage of any kind or nature
23
+-- related to, arising under or in connection with these
24
+-- materials, including for any direct, or any indirect,
25
+-- special, incidental, or consequential loss or damage
26
+-- (including loss of data, profits, goodwill, or any type of
27
+-- loss or damage suffered as a result of any action brought
28
+-- by a third party) even if such damage or loss was
29
+-- reasonably foreseeable or Xilinx had been advised of the
30
+-- possibility of the same.
31
+-- 
32
+-- CRITICAL APPLICATIONS
33
+-- Xilinx products are not designed or intended to be fail-
34
+-- safe, or for use in any application requiring fail-safe
35
+-- performance, such as life-support or safety devices or
36
+-- systems, Class III medical devices, nuclear facilities,
37
+-- applications related to the deployment of airbags, or any
38
+-- other applications that could lead to death, personal
39
+-- injury, or severe property or environmental damage
40
+-- (individually and collectively, "Critical
41
+-- Applications"). Customer assumes the sole risk and
42
+-- liability of any use of Xilinx products in Critical
43
+-- Applications, subject only to applicable laws and
44
+-- regulations governing limitations on product liability.
45
+-- 
46
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
+-- PART OF THIS FILE AT ALL TIMES.
48
+-- 
49
+------------------------------------------------------------------------------
50
+-- User entered comments
51
+------------------------------------------------------------------------------
52
+-- None
53
+--
54
+------------------------------------------------------------------------------
55
+--  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
56
+--   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
57
+------------------------------------------------------------------------------
58
+-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
59
+--
60
+------------------------------------------------------------------------------
61
+-- Input Clock   Freq (MHz)    Input Jitter (UI)
62
+------------------------------------------------------------------------------
63
+-- __primary_________100.000____________0.010
64
+
65
+library ieee;
66
+use ieee.std_logic_1164.all;
67
+use ieee.std_logic_unsigned.all;
68
+use ieee.std_logic_arith.all;
69
+use ieee.numeric_std.all;
70
+
71
+library unisim;
72
+use unisim.vcomponents.all;
73
+
74
+entity clk_wiz_0 is
75
+port
76
+ (-- Clock in ports
77
+  clk_in1           : in     std_logic;
78
+  -- Clock out ports
79
+  clk_out1          : out    std_logic
80
+ );
81
+end clk_wiz_0;
82
+
83
+architecture xilinx of clk_wiz_0 is
84
+  attribute CORE_GENERATION_INFO : string;
85
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
86
+
87
+component clk_wiz_0_clk_wiz
88
+port
89
+ (-- Clock in ports
90
+  clk_in1           : in     std_logic;
91
+  -- Clock out ports
92
+  clk_out1          : out    std_logic
93
+ );
94
+end component;
95
+
96
+begin
97
+
98
+  U0: clk_wiz_0_clk_wiz 
99
+   port map ( 
100
+
101
+   -- Clock in ports
102
+   clk_in1 => clk_in1,
103
+  -- Clock out ports  
104
+   clk_out1 => clk_out1              
105
+ );
106
+
107
+end xilinx;

+ 201
- 0
Processeur.srcs/sources_1/new/clk_wiz_0_clk_wiz.vhd View File

@@ -0,0 +1,201 @@
1
+    -- file: clk_wiz_0_clk_wiz.vhd
2
+    -- 
3
+    -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
4
+    -- 
5
+    -- This file contains confidential and proprietary information
6
+    -- of Xilinx, Inc. and is protected under U.S. and
7
+    -- international copyright and other intellectual property
8
+    -- laws.
9
+    -- 
10
+    -- DISCLAIMER
11
+    -- This disclaimer is not a license and does not grant any
12
+    -- rights to the materials distributed herewith. Except as
13
+    -- otherwise provided in a valid license issued to you by
14
+    -- Xilinx, and to the maximum extent permitted by applicable
15
+    -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16
+    -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17
+    -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18
+    -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19
+    -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20
+    -- (2) Xilinx shall not be liable (whether in contract or tort,
21
+    -- including negligence, or under any other theory of
22
+    -- liability) for any loss or damage of any kind or nature
23
+    -- related to, arising under or in connection with these
24
+    -- materials, including for any direct, or any indirect,
25
+    -- special, incidental, or consequential loss or damage
26
+    -- (including loss of data, profits, goodwill, or any type of
27
+    -- loss or damage suffered as a result of any action brought
28
+    -- by a third party) even if such damage or loss was
29
+    -- reasonably foreseeable or Xilinx had been advised of the
30
+    -- possibility of the same.
31
+    -- 
32
+    -- CRITICAL APPLICATIONS
33
+    -- Xilinx products are not designed or intended to be fail-
34
+    -- safe, or for use in any application requiring fail-safe
35
+    -- performance, such as life-support or safety devices or
36
+    -- systems, Class III medical devices, nuclear facilities,
37
+    -- applications related to the deployment of airbags, or any
38
+    -- other applications that could lead to death, personal
39
+    -- injury, or severe property or environmental damage
40
+    -- (individually and collectively, "Critical
41
+    -- Applications"). Customer assumes the sole risk and
42
+    -- liability of any use of Xilinx products in Critical
43
+    -- Applications, subject only to applicable laws and
44
+    -- regulations governing limitations on product liability.
45
+    -- 
46
+    -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47
+    -- PART OF THIS FILE AT ALL TIMES.
48
+    -- 
49
+    ------------------------------------------------------------------------------
50
+    -- User entered comments
51
+    ------------------------------------------------------------------------------
52
+    -- None
53
+    --
54
+    ------------------------------------------------------------------------------
55
+    --  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
56
+    --   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
57
+    ------------------------------------------------------------------------------
58
+    -- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
59
+    --
60
+    ------------------------------------------------------------------------------
61
+    -- Input Clock   Freq (MHz)    Input Jitter (UI)
62
+    ------------------------------------------------------------------------------
63
+    -- __primary_________100.000____________0.010
64
+
65
+    library ieee;
66
+    use ieee.std_logic_1164.all;
67
+    use ieee.std_logic_unsigned.all;
68
+    use ieee.std_logic_arith.all;
69
+    use ieee.numeric_std.all;
70
+
71
+    library unisim;
72
+    use unisim.vcomponents.all;
73
+
74
+    entity clk_wiz_0_clk_wiz is
75
+    port
76
+     (-- Clock in ports
77
+      clk_in1           : in     std_logic;
78
+      -- Clock out ports
79
+      clk_out1          : out    std_logic
80
+     );
81
+    end clk_wiz_0_clk_wiz;
82
+
83
+    architecture xilinx of clk_wiz_0_clk_wiz is
84
+      -- Input clock buffering / unused connectors
85
+      signal clk_in1_clk_wiz_0      : std_logic;
86
+      -- Output clock buffering / unused connectors
87
+      signal clkfbout_clk_wiz_0         : std_logic;
88
+      signal clkfbout_buf_clk_wiz_0     : std_logic;
89
+      signal clkfboutb_unused : std_logic;
90
+      signal clk_out1_clk_wiz_0          : std_logic;
91
+      signal clkout0b_unused         : std_logic;
92
+      signal clkout1_unused   : std_logic;
93
+      signal clkout1b_unused         : std_logic;
94
+      signal clkout2_unused   : std_logic;
95
+      signal clkout2b_unused         : std_logic;
96
+      signal clkout3_unused   : std_logic;
97
+      signal clkout3b_unused  : std_logic;
98
+      signal clkout4_unused   : std_logic;
99
+      signal clkout5_unused   : std_logic;
100
+      signal clkout6_unused   : std_logic;
101
+      -- Dynamic programming unused signals
102
+      signal do_unused        : std_logic_vector(15 downto 0);
103
+      signal drdy_unused      : std_logic;
104
+      -- Dynamic phase shift unused signals
105
+      signal psdone_unused    : std_logic;
106
+      signal locked_int : std_logic;
107
+      -- Unused status signals
108
+      signal clkfbstopped_unused : std_logic;
109
+      signal clkinstopped_unused : std_logic;
110
+
111
+    begin
112
+
113
+
114
+      -- Input buffering
115
+      --------------------------------------
116
+    clk_in1_clk_wiz_0 <= clk_in1;
117
+
118
+
119
+
120
+      -- Clocking PRIMITIVE
121
+      --------------------------------------
122
+      -- Instantiation of the MMCM PRIMITIVE
123
+      --    * Unused inputs are tied off
124
+      --    * Unused outputs are labeled unused
125
+      mmcm_adv_inst : MMCME2_ADV
126
+      generic map
127
+       (BANDWIDTH            => "OPTIMIZED",
128
+        CLKOUT4_CASCADE      => FALSE,
129
+        COMPENSATION         => "ZHOLD",
130
+        STARTUP_WAIT         => FALSE,
131
+        DIVCLK_DIVIDE        => 1,
132
+        CLKFBOUT_MULT_F      => 10.125,
133
+        CLKFBOUT_PHASE       => 0.000,
134
+        CLKFBOUT_USE_FINE_PS => FALSE,
135
+        CLKOUT0_DIVIDE_F     => 9.375,
136
+        CLKOUT0_PHASE        => 0.000,
137
+        CLKOUT0_DUTY_CYCLE   => 0.500,
138
+        CLKOUT0_USE_FINE_PS  => FALSE,
139
+        CLKIN1_PERIOD        => 10.0,
140
+        REF_JITTER1          => 0.010)
141
+      port map
142
+        -- Output clocks
143
+       (
144
+        CLKFBOUT            => clkfbout_clk_wiz_0,
145
+        CLKFBOUTB           => clkfboutb_unused,
146
+        CLKOUT0             => clk_out1_clk_wiz_0,
147
+        CLKOUT0B            => clkout0b_unused,
148
+        CLKOUT1             => clkout1_unused,
149
+        CLKOUT1B            => clkout1b_unused,
150
+        CLKOUT2             => clkout2_unused,
151
+        CLKOUT2B            => clkout2b_unused,
152
+        CLKOUT3             => clkout3_unused,
153
+        CLKOUT3B            => clkout3b_unused,
154
+        CLKOUT4             => clkout4_unused,
155
+        CLKOUT5             => clkout5_unused,
156
+        CLKOUT6             => clkout6_unused,
157
+        -- Input clock control
158
+        CLKFBIN             => clkfbout_buf_clk_wiz_0,
159
+        CLKIN1              => clk_in1_clk_wiz_0,
160
+        CLKIN2              => '0',
161
+        -- Tied to always select the primary input clock
162
+        CLKINSEL            => '1',
163
+        -- Ports for dynamic reconfiguration
164
+        DADDR               => (others => '0'),
165
+        DCLK                => '0',
166
+        DEN                 => '0',
167
+        DI                  => (others => '0'),
168
+        DO                  => do_unused,
169
+        DRDY                => drdy_unused,
170
+        DWE                 => '0',
171
+        -- Ports for dynamic phase shift
172
+        PSCLK               => '0',
173
+        PSEN                => '0',
174
+        PSINCDEC            => '0',
175
+        PSDONE              => psdone_unused,
176
+        -- Other control and status signals
177
+        LOCKED              => locked_int,
178
+        CLKINSTOPPED        => clkinstopped_unused,
179
+        CLKFBSTOPPED        => clkfbstopped_unused,
180
+        PWRDWN              => '0',
181
+        RST                 => '0');
182
+
183
+
184
+      -- Output buffering
185
+      -------------------------------------
186
+
187
+      clkf_buf : BUFG
188
+      port map
189
+       (O => clkfbout_buf_clk_wiz_0,
190
+        I => clkfbout_clk_wiz_0);
191
+
192
+
193
+
194
+      clkout1_buf : BUFG
195
+      port map
196
+       (O   => clk_out1,
197
+        I   => clk_out1_clk_wiz_0);
198
+
199
+
200
+
201
+    end xilinx;

+ 11
- 0
Processeur.srcs/sources_1/new/font.vhd View File

@@ -0,0 +1,11 @@
1
+library IEEE;
2
+use IEEE.STD_LOGIC_1164.ALL;
3
+
4
+package font is 
5
+
6
+    constant font_width  : natural := 8;
7
+    constant font_height : natural := 8;
8
+    
9
+    type font_T is array (0 to font_height - 1, 0 to font_width - 1) of STD_LOGIC;
10
+    
11
+end package;

+ 97
- 27
Processeur.xpr View File

@@ -32,20 +32,20 @@
32 32
     <Option Name="EnableBDX" Val="FALSE"/>
33 33
     <Option Name="DSABoardId" Val="basys3"/>
34 34
     <Option Name="DSANumComputeUnits" Val="16"/>
35
-    <Option Name="WTXSimLaunchSim" Val="339"/>
35
+    <Option Name="WTXSimLaunchSim" Val="420"/>
36 36
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38
     <Option Name="WTIesLaunchSim" Val="0"/>
39 39
     <Option Name="WTVcsLaunchSim" Val="0"/>
40 40
     <Option Name="WTRivieraLaunchSim" Val="0"/>
41 41
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
42
-    <Option Name="WTXSimExportSim" Val="0"/>
43
-    <Option Name="WTModelSimExportSim" Val="0"/>
44
-    <Option Name="WTQuestaExportSim" Val="0"/>
45
-    <Option Name="WTIesExportSim" Val="0"/>
46
-    <Option Name="WTVcsExportSim" Val="0"/>
47
-    <Option Name="WTRivieraExportSim" Val="0"/>
48
-    <Option Name="WTActivehdlExportSim" Val="0"/>
42
+    <Option Name="WTXSimExportSim" Val="2"/>
43
+    <Option Name="WTModelSimExportSim" Val="2"/>
44
+    <Option Name="WTQuestaExportSim" Val="2"/>
45
+    <Option Name="WTIesExportSim" Val="2"/>
46
+    <Option Name="WTVcsExportSim" Val="2"/>
47
+    <Option Name="WTRivieraExportSim" Val="2"/>
48
+    <Option Name="WTActivehdlExportSim" Val="2"/>
49 49
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
50 50
     <Option Name="XSimRadix" Val="hex"/>
51 51
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -61,12 +61,6 @@
61 61
           <Attr Name="UsedIn" Val="simulation"/>
62 62
         </FileInfo>
63 63
       </File>
64
-      <File Path="$PSRCDIR/sources_1/new/System.vhd">
65
-        <FileInfo SFType="VHDL2008">
66
-          <Attr Name="UsedIn" Val="synthesis"/>
67
-          <Attr Name="UsedIn" Val="simulation"/>
68
-        </FileInfo>
69
-      </File>
70 64
       <File Path="$PSRCDIR/sources_1/new/BancRegistres.vhd">
71 65
         <FileInfo>
72 66
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -103,6 +97,18 @@
103 97
           <Attr Name="UsedIn" Val="simulation"/>
104 98
         </FileInfo>
105 99
       </File>
100
+      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
101
+        <FileInfo>
102
+          <Attr Name="UsedIn" Val="synthesis"/>
103
+          <Attr Name="UsedIn" Val="simulation"/>
104
+        </FileInfo>
105
+      </File>
106
+      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
107
+        <FileInfo>
108
+          <Attr Name="UsedIn" Val="synthesis"/>
109
+          <Attr Name="UsedIn" Val="simulation"/>
110
+        </FileInfo>
111
+      </File>
106 112
       <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
107 113
         <FileInfo>
108 114
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -115,13 +121,13 @@
115 121
           <Attr Name="UsedIn" Val="simulation"/>
116 122
         </FileInfo>
117 123
       </File>
118
-      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
124
+      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
119 125
         <FileInfo>
120 126
           <Attr Name="UsedIn" Val="synthesis"/>
121 127
           <Attr Name="UsedIn" Val="simulation"/>
122 128
         </FileInfo>
123 129
       </File>
124
-      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
130
+      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
125 131
         <FileInfo>
126 132
           <Attr Name="UsedIn" Val="synthesis"/>
127 133
           <Attr Name="UsedIn" Val="simulation"/>
@@ -133,25 +139,67 @@
133 139
           <Attr Name="UsedIn" Val="simulation"/>
134 140
         </FileInfo>
135 141
       </File>
136
-      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
142
+      <File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
137 143
         <FileInfo>
138 144
           <Attr Name="UsedIn" Val="synthesis"/>
139 145
           <Attr Name="UsedIn" Val="simulation"/>
140 146
         </FileInfo>
141 147
       </File>
142
-      <File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
148
+      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
143 149
         <FileInfo>
144 150
           <Attr Name="UsedIn" Val="synthesis"/>
145 151
           <Attr Name="UsedIn" Val="simulation"/>
146 152
         </FileInfo>
147 153
       </File>
148
-      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
154
+      <File Path="$PSRCDIR/sources_1/new/clk_wiz_0_clk_wiz.vhd">
149 155
         <FileInfo>
150 156
           <Attr Name="UsedIn" Val="synthesis"/>
151 157
           <Attr Name="UsedIn" Val="simulation"/>
152 158
         </FileInfo>
153 159
       </File>
154
-      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
160
+      <File Path="$PSRCDIR/sources_1/new/clk_wiz_0.vhd">
161
+        <FileInfo>
162
+          <Attr Name="UsedIn" Val="synthesis"/>
163
+          <Attr Name="UsedIn" Val="simulation"/>
164
+        </FileInfo>
165
+      </File>
166
+      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
167
+        <FileInfo>
168
+          <Attr Name="UsedIn" Val="synthesis"/>
169
+          <Attr Name="UsedIn" Val="simulation"/>
170
+        </FileInfo>
171
+      </File>
172
+      <File Path="$PSRCDIR/sources_1/new/VGAControler.vhd">
173
+        <FileInfo>
174
+          <Attr Name="UsedIn" Val="synthesis"/>
175
+          <Attr Name="UsedIn" Val="simulation"/>
176
+        </FileInfo>
177
+      </File>
178
+      <File Path="$PSRCDIR/sources_1/new/font.vhd">
179
+        <FileInfo>
180
+          <Attr Name="UsedIn" Val="synthesis"/>
181
+          <Attr Name="UsedIn" Val="simulation"/>
182
+        </FileInfo>
183
+      </File>
184
+      <File Path="$PSRCDIR/sources_1/new/TableASCII.vhd">
185
+        <FileInfo>
186
+          <Attr Name="UsedIn" Val="synthesis"/>
187
+          <Attr Name="UsedIn" Val="simulation"/>
188
+        </FileInfo>
189
+      </File>
190
+      <File Path="$PSRCDIR/sources_1/new/Ecran.vhd">
191
+        <FileInfo>
192
+          <Attr Name="UsedIn" Val="synthesis"/>
193
+          <Attr Name="UsedIn" Val="simulation"/>
194
+        </FileInfo>
195
+      </File>
196
+      <File Path="$PSRCDIR/sources_1/new/System.vhd">
197
+        <FileInfo SFType="VHDL2008">
198
+          <Attr Name="UsedIn" Val="simulation"/>
199
+          <Attr Name="UsedIn" Val="synthesis"/>
200
+        </FileInfo>
201
+      </File>
202
+      <File Path="$PSRCDIR/sources_1/new/ScreenSystem.vhd">
155 203
         <FileInfo>
156 204
           <Attr Name="UsedIn" Val="synthesis"/>
157 205
           <Attr Name="UsedIn" Val="simulation"/>
@@ -159,8 +207,7 @@
159 207
       </File>
160 208
       <Config>
161 209
         <Option Name="DesignMode" Val="RTL"/>
162
-        <Option Name="TopModule" Val="System"/>
163
-        <Option Name="TopAutoSet" Val="TRUE"/>
210
+        <Option Name="TopModule" Val="ScreenSystem"/>
164 211
       </Config>
165 212
     </FileSet>
166 213
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@@ -256,12 +303,37 @@
256 303
           <Attr Name="UsedIn" Val="simulation"/>
257 304
         </FileInfo>
258 305
       </File>
306
+      <File Path="$PSRCDIR/sim_1/new/Test_Ecran.vhd">
307
+        <FileInfo>
308
+          <Attr Name="UsedIn" Val="synthesis"/>
309
+          <Attr Name="UsedIn" Val="simulation"/>
310
+        </FileInfo>
311
+      </File>
312
+      <File Path="$PSRCDIR/sim_1/new/Test_VGAControler.vhd">
313
+        <FileInfo>
314
+          <Attr Name="UsedIn" Val="synthesis"/>
315
+          <Attr Name="UsedIn" Val="simulation"/>
316
+        </FileInfo>
317
+      </File>
318
+      <File Path="$PSRCDIR/sim_1/new/Test_ScreenSystem.vhd">
319
+        <FileInfo>
320
+          <Attr Name="UsedIn" Val="synthesis"/>
321
+          <Attr Name="UsedIn" Val="simulation"/>
322
+        </FileInfo>
323
+      </File>
324
+      <File Path="$PSRCDIR/sim_1/new/TestTableASCII.vhd">
325
+        <FileInfo>
326
+          <Attr Name="UsedIn" Val="synthesis"/>
327
+          <Attr Name="UsedIn" Val="simulation"/>
328
+        </FileInfo>
329
+      </File>
259 330
       <Config>
260 331
         <Option Name="DesignMode" Val="RTL"/>
261
-        <Option Name="TopModule" Val="Test_Pipeline"/>
332
+        <Option Name="TopModule" Val="TestTableASCII"/>
262 333
         <Option Name="TopLib" Val="xil_defaultlib"/>
263 334
         <Option Name="TransportPathDelay" Val="0"/>
264 335
         <Option Name="TransportIntDelay" Val="0"/>
336
+        <Option Name="SimMode" Val="post-implementation"/>
265 337
         <Option Name="SrcSet" Val="sources_1"/>
266 338
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
267 339
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
@@ -292,15 +364,14 @@
292 364
     </Simulator>
293 365
   </Simulators>
294 366
   <Runs Version="1" Minor="10">
295
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
367
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
296 368
       <Strategy Version="1" Minor="2">
297 369
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
298 370
         <Step Id="synth_design"/>
299 371
       </Strategy>
300
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
301 372
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
302 373
     </Run>
303
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
374
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
304 375
       <Strategy Version="1" Minor="2">
305 376
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
306 377
         <Step Id="init_design"/>
@@ -313,7 +384,6 @@
313 384
         <Step Id="post_route_phys_opt_design"/>
314 385
         <Step Id="write_bitstream"/>
315 386
       </Strategy>
316
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
317 387
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
318 388
     </Run>
319 389
   </Runs>

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