Processeur/Processeur.srcs/sources_1/new/Compteur.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 28.06.2021 14:59:39
-- Design Name: 
-- Module Name: Compteur - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Compteur is
    Generic (Min : Natural;
             Max : Natural
            );
    Port    (CLK : in STD_LOGIC;
             RST : in STD_LOGIC;
             Value : out Natural;
             Carry : out STD_LOGIC);
end Compteur;

architecture Behavioral of Compteur is

    signal current : Natural := Min;
    signal InternCarry : STD_LOGIC := '0';
    
begin

    process
    begin
        wait until CLK'event and CLK = '1';
        if (RST = '0') then
            current <= Min;
        else 
            current <= current + 1;
            if (current = Max) then
                InternCarry <= '1'; 
                current <= Min;
            else 
                InternCarry <= '0';
            end if;
        end if;
    end process;
    
    Value <= current;
    Carry <= InternCarry;
    
end Behavioral;