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TestTableASCII.vhd 1.4KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 29.06.2021 16:16:32
  6. -- Design Name:
  7. -- Module Name: TestTableASCII - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use work.font.all;
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26. -- Uncomment the following library declaration if instantiating
  27. -- any Xilinx leaf cells in this code.
  28. --library UNISIM;
  29. --use UNISIM.VComponents.all;
  30. entity TestTableASCII is
  31. -- Port ( );
  32. end TestTableASCII;
  33. architecture Behavioral of TestTableASCII is
  34. component TableASCII is
  35. port ( CodeASCII : in Natural;
  36. Font : out font_T);
  37. end component;
  38. signal my_CodeASCII : Natural := 0;
  39. signal my_Font : font_T := (others => (others => '0'));
  40. begin
  41. instance : TableASCII
  42. port map( CodeASCII => my_CodeASCII,
  43. Font => my_Font
  44. );
  45. process
  46. begin
  47. my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
  48. wait;
  49. end process;
  50. end Behavioral;