123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263 |
- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 29.06.2021 16:16:32
- -- Design Name:
- -- Module Name: TestTableASCII - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- use work.font.all;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity TestTableASCII is
- -- Port ( );
- end TestTableASCII;
-
- architecture Behavioral of TestTableASCII is
-
- component TableASCII is
- port ( CodeASCII : in Natural;
- Font : out font_T);
- end component;
-
- signal my_CodeASCII : Natural := 0;
- signal my_Font : font_T := (others => (others => '0'));
-
- begin
-
- instance : TableASCII
- port map( CodeASCII => my_CodeASCII,
- Font => my_Font
- );
-
- process
- begin
- my_CodeASCII <= 0 after 5 ns, 1 after 10 ns, 65 after 15 ns, 66 after 25 ns;
- wait;
- end process;
-
- end Behavioral;
|