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clk_wiz_0_clk_wiz.vhd 7.8KB

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  1. -- file: clk_wiz_0_clk_wiz.vhd
  2. --
  3. -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
  4. --
  5. -- This file contains confidential and proprietary information
  6. -- of Xilinx, Inc. and is protected under U.S. and
  7. -- international copyright and other intellectual property
  8. -- laws.
  9. --
  10. -- DISCLAIMER
  11. -- This disclaimer is not a license and does not grant any
  12. -- rights to the materials distributed herewith. Except as
  13. -- otherwise provided in a valid license issued to you by
  14. -- Xilinx, and to the maximum extent permitted by applicable
  15. -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
  16. -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
  17. -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
  18. -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
  19. -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
  20. -- (2) Xilinx shall not be liable (whether in contract or tort,
  21. -- including negligence, or under any other theory of
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  25. -- special, incidental, or consequential loss or damage
  26. -- (including loss of data, profits, goodwill, or any type of
  27. -- loss or damage suffered as a result of any action brought
  28. -- by a third party) even if such damage or loss was
  29. -- reasonably foreseeable or Xilinx had been advised of the
  30. -- possibility of the same.
  31. --
  32. -- CRITICAL APPLICATIONS
  33. -- Xilinx products are not designed or intended to be fail-
  34. -- safe, or for use in any application requiring fail-safe
  35. -- performance, such as life-support or safety devices or
  36. -- systems, Class III medical devices, nuclear facilities,
  37. -- applications related to the deployment of airbags, or any
  38. -- other applications that could lead to death, personal
  39. -- injury, or severe property or environmental damage
  40. -- (individually and collectively, "Critical
  41. -- Applications"). Customer assumes the sole risk and
  42. -- liability of any use of Xilinx products in Critical
  43. -- Applications, subject only to applicable laws and
  44. -- regulations governing limitations on product liability.
  45. --
  46. -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
  47. -- PART OF THIS FILE AT ALL TIMES.
  48. --
  49. ------------------------------------------------------------------------------
  50. -- User entered comments
  51. ------------------------------------------------------------------------------
  52. -- None
  53. --
  54. ------------------------------------------------------------------------------
  55. -- Output Output Phase Duty Cycle Pk-to-Pk Phase
  56. -- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
  57. ------------------------------------------------------------------------------
  58. -- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
  59. --
  60. ------------------------------------------------------------------------------
  61. -- Input Clock Freq (MHz) Input Jitter (UI)
  62. ------------------------------------------------------------------------------
  63. -- __primary_________100.000____________0.010
  64. library ieee;
  65. use ieee.std_logic_1164.all;
  66. use ieee.std_logic_unsigned.all;
  67. use ieee.std_logic_arith.all;
  68. use ieee.numeric_std.all;
  69. library unisim;
  70. use unisim.vcomponents.all;
  71. entity clk_wiz_0_clk_wiz is
  72. port
  73. (-- Clock in ports
  74. clk_in1 : in std_logic;
  75. -- Clock out ports
  76. clk_out1 : out std_logic
  77. );
  78. end clk_wiz_0_clk_wiz;
  79. architecture xilinx of clk_wiz_0_clk_wiz is
  80. -- Input clock buffering / unused connectors
  81. signal clk_in1_clk_wiz_0 : std_logic;
  82. -- Output clock buffering / unused connectors
  83. signal clkfbout_clk_wiz_0 : std_logic;
  84. signal clkfbout_buf_clk_wiz_0 : std_logic;
  85. signal clkfboutb_unused : std_logic;
  86. signal clk_out1_clk_wiz_0 : std_logic;
  87. signal clkout0b_unused : std_logic;
  88. signal clkout1_unused : std_logic;
  89. signal clkout1b_unused : std_logic;
  90. signal clkout2_unused : std_logic;
  91. signal clkout2b_unused : std_logic;
  92. signal clkout3_unused : std_logic;
  93. signal clkout3b_unused : std_logic;
  94. signal clkout4_unused : std_logic;
  95. signal clkout5_unused : std_logic;
  96. signal clkout6_unused : std_logic;
  97. -- Dynamic programming unused signals
  98. signal do_unused : std_logic_vector(15 downto 0);
  99. signal drdy_unused : std_logic;
  100. -- Dynamic phase shift unused signals
  101. signal psdone_unused : std_logic;
  102. signal locked_int : std_logic;
  103. -- Unused status signals
  104. signal clkfbstopped_unused : std_logic;
  105. signal clkinstopped_unused : std_logic;
  106. begin
  107. -- Input buffering
  108. --------------------------------------
  109. clk_in1_clk_wiz_0 <= clk_in1;
  110. -- Clocking PRIMITIVE
  111. --------------------------------------
  112. -- Instantiation of the MMCM PRIMITIVE
  113. -- * Unused inputs are tied off
  114. -- * Unused outputs are labeled unused
  115. mmcm_adv_inst : MMCME2_ADV
  116. generic map
  117. (BANDWIDTH => "OPTIMIZED",
  118. CLKOUT4_CASCADE => FALSE,
  119. COMPENSATION => "ZHOLD",
  120. STARTUP_WAIT => FALSE,
  121. DIVCLK_DIVIDE => 1,
  122. CLKFBOUT_MULT_F => 10.125,
  123. CLKFBOUT_PHASE => 0.000,
  124. CLKFBOUT_USE_FINE_PS => FALSE,
  125. CLKOUT0_DIVIDE_F => 9.375,
  126. CLKOUT0_PHASE => 0.000,
  127. CLKOUT0_DUTY_CYCLE => 0.500,
  128. CLKOUT0_USE_FINE_PS => FALSE,
  129. CLKIN1_PERIOD => 10.0,
  130. REF_JITTER1 => 0.010)
  131. port map
  132. -- Output clocks
  133. (
  134. CLKFBOUT => clkfbout_clk_wiz_0,
  135. CLKFBOUTB => clkfboutb_unused,
  136. CLKOUT0 => clk_out1_clk_wiz_0,
  137. CLKOUT0B => clkout0b_unused,
  138. CLKOUT1 => clkout1_unused,
  139. CLKOUT1B => clkout1b_unused,
  140. CLKOUT2 => clkout2_unused,
  141. CLKOUT2B => clkout2b_unused,
  142. CLKOUT3 => clkout3_unused,
  143. CLKOUT3B => clkout3b_unused,
  144. CLKOUT4 => clkout4_unused,
  145. CLKOUT5 => clkout5_unused,
  146. CLKOUT6 => clkout6_unused,
  147. -- Input clock control
  148. CLKFBIN => clkfbout_buf_clk_wiz_0,
  149. CLKIN1 => clk_in1_clk_wiz_0,
  150. CLKIN2 => '0',
  151. -- Tied to always select the primary input clock
  152. CLKINSEL => '1',
  153. -- Ports for dynamic reconfiguration
  154. DADDR => (others => '0'),
  155. DCLK => '0',
  156. DEN => '0',
  157. DI => (others => '0'),
  158. DO => do_unused,
  159. DRDY => drdy_unused,
  160. DWE => '0',
  161. -- Ports for dynamic phase shift
  162. PSCLK => '0',
  163. PSEN => '0',
  164. PSINCDEC => '0',
  165. PSDONE => psdone_unused,
  166. -- Other control and status signals
  167. LOCKED => locked_int,
  168. CLKINSTOPPED => clkinstopped_unused,
  169. CLKFBSTOPPED => clkfbstopped_unused,
  170. PWRDWN => '0',
  171. RST => '0');
  172. -- Output buffering
  173. -------------------------------------
  174. clkf_buf : BUFG
  175. port map
  176. (O => clkfbout_buf_clk_wiz_0,
  177. I => clkfbout_clk_wiz_0);
  178. clkout1_buf : BUFG
  179. port map
  180. (O => clk_out1,
  181. I => clk_out1_clk_wiz_0);
  182. end xilinx;