Processeur/Processeur.srcs/sim_1/new/Test_Ecran.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 28.06.2021 11:25:08
-- Design Name: 
-- Module Name: Test_Ecran - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_Ecran is
--  Port ( );
end Test_Ecran;

architecture Behavioral of Test_Ecran is

    component Ecran is
        Generic (  HEIGHT         : Natural;
                   WIDTH          : Natural        
        );
        Port (     CLK            : in STD_LOGIC;
                   RST            : in STD_LOGIC;
                   Data_Av        : in STD_LOGIC;
                   Data_IN        : in STD_LOGIC_VECTOR (0 to 6);
                   
                   X              : in Natural;
                   Y              : in Natural;
                   OUT_ON         : out STD_LOGIC);
    end component; 
    
    
    signal my_CLK : STD_LOGIC := '0';
    signal my_RST : STD_LOGIC := '1';
    signal my_Data_Av : STD_LOGIC := '0';
    signal my_Data_IN : STD_LOGIC_VECTOR (6 downto 0) := (others => '0');
    signal my_X : Natural := 0;
    signal my_Y : Natural := 0;
    signal my_OUT_ON : STD_LOGIC := '0';
    
    constant CLK_period : time := 10 ns;

begin
    instance : Ecran 
    generic map(  HEIGHT => 50,
                  WIDTH => 68   
    )
    port map(  CLK => my_CLK,
               RST => my_RST,
               Data_Av => my_Data_Av,
               Data_IN => my_Data_IN,
               X => my_X,
               Y => my_Y,
               OUT_ON => my_OUT_ON);

    CLK_process : process
    begin
        my_CLK <= '0';
        wait for CLK_period/2;
        my_CLK <= '1';
        wait for CLK_period/2;
    end process;

    process 
    begin   
    my_Data_Av <= '1' after 0 ns;
    my_Data_IN <= "0000001" after 0 ns, "0000010" after 40 ns, "0000011" after 80 ns, "0000100" after 120 ns, "0001101" after 140 ns, "0000101" after 150 ns, "0000000" after 170 ns, "0000001" after 180 ns, "0000010" after 220 ns;
    wait;
    end process;  
      
end Behavioral;