Processeur/Processeur.srcs/sim_1/new/Test_SystemKeyboardScreen.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 07.07.2021 18:57:39
-- Design Name: 
-- Module Name: Test_SystemKeyboardScreen - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_SystemKeyboardScreen is
--  Port ( );
end Test_SystemKeyboardScreen;

architecture Behavioral of Test_SystemKeyboardScreen is

    component SystemKeyboardScreen
    Port ( CLK : in STD_LOGIC;
    
           PS2Clk : in STD_LOGIC;
           PS2Data : in STD_LOGIC;
           
           vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
           vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
           Hsync : out STD_LOGIC;
           Vsync : out STD_LOGIC);
    end component;

    signal CLK : STD_LOGIC := '0';
    
    signal PS2Clk : STD_LOGIC := '0';
    signal PS2Data : STD_LOGIC := '0';
    
    signal vgaRed : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal vgaGreen : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal vgaBlue : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal Hsync : STD_LOGIC := '0';
    signal Vsync : STD_LOGIC := '0';
    
    signal CLK_period : Time := 10 ns;

begin

    instance : SystemKeyboardScreen
    port map ( CLK => CLK,
    
               PS2Clk => PS2Clk,
               PS2Data => PS2Data,
               
               vgaRed => vgaRed,
               vgaGreen => vgaGreen,
               vgaBlue => vgaBlue,
               Hsync => Hsync,
               Vsync => Vsync);

    CLK_process : process
    begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
    end process;
    
    process 
    begin   
        PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
        PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
        wait;
    end process;  

end Behavioral;