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Test_Compteur.vhd 2.2KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 05.07.2021 16:38:12
  6. -- Design Name:
  7. -- Module Name: Test_Compteur - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity Test_Compteur is
  30. -- Port ( );
  31. end Test_Compteur;
  32. architecture Behavioral of Test_Compteur is
  33. constant screen_width : natural := 1280;
  34. constant screen_height : natural := 1040;
  35. subtype X_T is Natural range 0 to screen_width - 1;
  36. subtype Y_T is Natural range 0 to screen_height - 1;
  37. component Compteur_X is
  38. Port ( CLK : in STD_LOGIC;
  39. RST : in STD_LOGIC;
  40. Value : out X_T;
  41. Carry : out STD_LOGIC);
  42. end component;
  43. component Compteur_Y is
  44. Port ( CLK : in STD_LOGIC;
  45. RST : in STD_LOGIC;
  46. Value : out Y_T);
  47. end component;
  48. signal my_Carry : STD_LOGIC := '0';
  49. signal my_Value : X_T := 0;
  50. signal my_Value_Y : X_T := 0;
  51. signal my_CLK : STD_LOGIC := '0';
  52. signal my_RST : STD_LOGIC := '1';
  53. constant CLK_period : time := 10 ns;
  54. begin
  55. inst_Compteur_X : Compteur_X
  56. Port map ( CLK => my_CLK,
  57. RST => my_RST,
  58. Value => my_Value,
  59. Carry => my_Carry);
  60. inst_Compteur_Y : Compteur_Y
  61. Port map ( CLK => my_Carry,
  62. RST => my_RST,
  63. Value => my_Value_Y);
  64. CLK_process : process
  65. begin
  66. my_CLK <= '0';
  67. wait for CLK_period/2;
  68. my_CLK <= '1';
  69. wait for CLK_period/2;
  70. end process;
  71. process
  72. begin
  73. wait;
  74. end process;
  75. end Behavioral;