93 lines
2.8 KiB
VHDL
93 lines
2.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 02.07.2021 08:21:55
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-- Design Name:
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-- Module Name: Test_Keyboard - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Test_Keyboard is
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-- Port ( );
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end Test_Keyboard;
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architecture Behavioral of Test_Keyboard is
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component Keyboard is
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Port (CLK : in STD_LOGIC;
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PS2Clk : in STD_LOGIC;
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PS2Data : in STD_LOGIC;
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Data_read : in STD_LOGIC;
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Data_av : out STD_LOGIC;
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Data : out STD_LOGIC_VECTOR (0 to 7);
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alert : out STD_LOGIC);
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end component;
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signal CLK : STD_LOGIC := '0';
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signal PS2Clk : STD_LOGIC := '0';
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signal PS2Data : STD_LOGIC := '0';
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signal Data_read : STD_LOGIC := '0';
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signal Data_av : STD_LOGIC := '0';
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signal Data : STD_LOGIC_VECTOR (0 to 7) := (others => '0');
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signal alert : STD_LOGIC := '0';
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constant CLK_period : TIME := 10 ns;
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begin
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CLK_process : process
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begin
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CLK <= '1';
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wait for CLK_period/2;
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CLK <= '0';
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wait for CLK_period/2;
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end process;
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instance : Keyboard
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port map (CLK => CLK,
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PS2Clk => PS2Clk,
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PS2Data => PS2Data,
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Data_read => Data_read,
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Data_av => Data_av,
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Data => Data,
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alert => alert);
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process
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begin
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PS2Clk <= '1' after 1020 ns, '0' after 1070 ns, '1' after 1120 ns, '0' after 1170 ns, '1' after 1220 ns, '0' after 1270 ns, '1' after 1320 ns, '0' after 1370 ns, '1' after 1420 ns, '0' after 1470 ns, '1' after 1520 ns, '0' after 1570 ns, '1' after 1620 ns, '0' after 1670 ns, '1' after 1720 ns, '0' after 1770 ns, '1' after 1820 ns, '0' after 1870 ns, '1' after 1920 ns, '0' after 1970 ns, '1' after 2020 ns, '0' after 2070 ns;
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PS2Data <= '0' after 1020 ns, '1' after 1120 ns, '0' after 1220 ns, '1' after 1320 ns, '0' after 1420 ns, '1' after 1520 ns, '0' after 1620 ns, '0' after 1720 ns, '0' after 1820 ns, '0' after 1920 ns, '1' after 2020 ns, '0' after 2120 ns;
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Data_read <= '1' after 3000 ns;
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wait;
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end process;
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end Behavioral;
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