145 lines
4.4 KiB
VHDL
145 lines
4.4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: INSA-Toulouse
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-- Engineer: Paul Faure
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--
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-- Create Date: 09.07.2021 15:25:56
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-- Module Name: PeripheriqueEcran - Behavioral
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-- Project Name: Processeur sécurisé
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-- Target Devices: Basys 3 ARTIX7
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-- Tool Versions: Vivado 2016.4
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--
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-- Description: Assemble les composants de l'écran pour faire un composant périphérique que l'on peut connecter au processeur
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-- - Le controleur
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-- - L'écran
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-- - Le driver
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--
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-- Dependencies:
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-- - VGAControler
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-- - Ecran
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-- - ScreenDriver
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-- - clk_wiz_0
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--
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-- Comments : la clock doit être accélérée pour atteindre 108Mhz pour le VGA
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.ScreenProperties.all;
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entity PeripheriqueEcran is
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Generic ( Nb_Bits : Natural);
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Port ( CLK : in STD_LOGIC;
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CLK_VGA : in STD_LOGIC;
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RST : in STD_LOGIC;
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vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
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vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
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vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
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Hsync : out STD_LOGIC;
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Vsync : out STD_LOGIC;
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STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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STD_OUT_Av : in STD_LOGIC;
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STD_OUT_Int : in STD_LOGIC);
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end PeripheriqueEcran;
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architecture Behavioral of PeripheriqueEcran is
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component VGAControler is
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Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_HS : out STD_LOGIC;
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VGA_VS : out STD_LOGIC;
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X : out X_T;
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Y : out Y_T;
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PIXEL_ON : in STD_LOGIC;
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC);
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end component;
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component clk_wiz_0
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port
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(-- Clock in ports
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clk_in1 : in std_logic;
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-- Clock out ports
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clk_out1 : out std_logic
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);
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end component;
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component Ecran is
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Data_Av : in STD_LOGIC;
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Data_IN : in STD_LOGIC_VECTOR (0 to 6);
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X : in X_T;
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Y : in Y_T;
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OUT_ON : out STD_LOGIC);
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end component;
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component ScreenDriver
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Generic ( Nb_bits : Natural
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);
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Port ( CLK : in STD_LOGIC;
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Value : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
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ValueAv : in STD_LOGIC;
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IsInt : in STD_LOGIC;
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OutData : out STD_LOGIC_VECTOR (0 to 6);
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OutDataAv : out STD_LOGIC);
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end component;
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signal my_X : X_T := 0;
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signal my_Y : Y_T := 0;
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signal my_PIXEL_ON : STD_LOGIC := '0';
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signal OutData : STD_LOGIC_VECTOR (0 to 6) := (others => '0');
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signal OutDataAv : STD_LOGIC := '0';
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signal my_CLK : STD_LOGIC := '0';
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begin
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instanceVGA : VGAControler
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port map( VGA_RED => vgaRed,
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VGA_BLUE => vgaBlue,
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VGA_GREEN => vgaGreen,
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VGA_HS => Hsync,
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VGA_VS => Vsync,
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X => my_X,
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Y => my_Y,
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PIXEL_ON => my_PIXEL_ON,
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CLK => my_CLK,
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RST => RST);
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clk_wiz_0_inst : clk_wiz_0
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port map (
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clk_in1 => CLK_VGA,
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clk_out1 => my_CLK
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);
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instance_Ecran : Ecran
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port map ( CLK => CLK,
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RST => RST,
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Data_Av => OutDataAv,
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Data_IN => OutData,
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X => my_X,
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Y => my_Y,
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OUT_ON => my_PIXEL_ON);
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instance_ScreenDriver : ScreenDriver
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Generic map ( Nb_bits => Nb_Bits
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)
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Port map ( CLK => CLK,
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Value => STD_OUT,
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ValueAv => STD_OUT_Av,
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IsInt => STD_OUT_Int,
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OutData => OutData,
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OutDataAv => OutDataAv);
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end Behavioral;
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