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Preparation merge

Paul Faure 3 months ago
parent
commit
cd30c90fc7

Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd → Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd View File

@@ -3,7 +3,7 @@
3 3
 -- Engineer: Paul Faure
4 4
 -- 
5 5
 -- Create Date: 18.04.2021 21:19:41
6
+-- Module Name: Etage1_LectureInstruction_NS - Behavioral
6 7
 -- Project Name: Processeur sécurisé
7 8
 -- Target Devices: Basys 3 ARTIX7
8 9
 -- Tool Versions: Vivado 2016.4
@@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 24
 use IEEE.NUMERIC_STD.ALL;
25 25
 
26 26
 
27
-entity Etage1_LectureInstruction is
27
+entity Etage1_LectureInstruction_NS is
28 28
     Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
29 29
              Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
30 30
              Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
@@ -61,11 +61,11 @@ entity Etage1_LectureInstruction is
61 61
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
62 62
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
63 63
            Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
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-end Etage1_LectureInstruction;
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+end Etage1_LectureInstruction_NS;
65 65
 
66 66
 
67 67
 
68
-architecture Behavioral of Etage1_LectureInstruction is
68
+architecture Behavioral of Etage1_LectureInstruction_NS is
69 69
     component MemoireInstructions is
70 70
     Generic (Nb_bits : Natural;
71 71
              Addr_size : Natural;

Processeur.srcs/sources_1/new/Etage4_Memoire.vhd → Processeur.srcs/sources_1/new/Etage4_Memoire_NS.vhd View File

@@ -3,7 +3,7 @@
3 3
 -- Engineer: Paul Faure
4 4
 -- 
5 5
 -- Create Date: 18.04.2021 21:19:41
6
+-- Module Name: Etage4_Memoire_NS - Structural
6 7
 -- Project Name: Processeur sécurisé
7 8
 -- Target Devices: Basys 3 ARTIX7
8 9
 -- Tool Versions: Vivado 2016.4
@@ -24,7 +24,7 @@ library IEEE;
24 24
 use IEEE.STD_LOGIC_1164.ALL;
25 25
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 26
 
27
-entity Etage4_Memoire is
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+entity Etage4_Memoire_NS is
28 28
     Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
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               Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
30 30
               Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
@@ -44,9 +44,9 @@ entity Etage4_Memoire is
44 44
            OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
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            OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
46 46
            OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
47
-end Etage4_Memoire;
47
+end Etage4_Memoire_NS;
48 48
 
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-architecture Structural of Etage4_Memoire is
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+architecture Structural of Etage4_Memoire_NS is
50 50
     component MemoireDonnees is
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     Generic (Nb_bits : Natural;
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              Addr_size : Natural;
@@ -186,4 +186,4 @@ begin
186 186
            
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     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
188 188
            
189
-end Structural;
189
+end Structural;

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
File diff suppressed because it is too large
View File


Processeur.srcs/sources_1/new/Pipeline.vhd → Processeur.srcs/sources_1/new/Pipeline_NS.vhd View File

@@ -4,7 +4,7 @@
4 4
 -- 
5 5
 -- Create Date: 19.04.2021 16:57:41
6 6
 -- Design Name: 
7
+-- Module Name: Pipeline_NS - Behavioral
7 8
 -- Project Name: 
8 9
 -- Target Devices: 
9 10
 -- Tool Versions: 
@@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
31 31
 --library UNISIM;
32 32
 --use UNISIM.VComponents.all;
33 33
 
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-entity Pipeline is
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+entity Pipeline_NS is
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     Generic (Nb_bits : Natural := 8;
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              Instruction_En_Memoire_Size : Natural := 29;
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              Addr_Memoire_Instruction_Size : Natural := 3;
@@ -46,11 +46,11 @@ entity Pipeline is
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           RST : STD_LOGIC;
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           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
48 48
           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
49
-end Pipeline;
49
+end Pipeline_NS;
50 50
 
51
-architecture Behavioral of Pipeline is
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+architecture Behavioral of Pipeline_NS is
52 52
     
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-    component Etage1_LectureInstruction is
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+    component Etage1_LectureInstruction_NS is
54 54
     Generic (Instruction_size_in_memory : Natural;
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              Addr_size_mem_instruction : Natural;
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              Mem_instruction_size : Natural;
@@ -122,7 +122,7 @@ architecture Behavioral of Pipeline is
122 122
            C : out STD_LOGIC);
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     end component;
124 124
         
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-    component Etage4_Memoire is
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+    component Etage4_Memoire_NS is
126 126
         Generic ( Nb_bits : Natural;
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                   Mem_size : Natural;
128 128
                   Adresse_mem_size : Natural;
@@ -200,7 +200,7 @@ architecture Behavioral of Pipeline is
200 200
     constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
201 201
     constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
202 202
 begin
203
-    instance_Etage1 : Etage1_LectureInstruction
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+    instance_Etage1 : Etage1_LectureInstruction_NS
204 204
     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
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                  Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
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                  Mem_instruction_size => Memoire_Instruction_Size,
@@ -276,7 +276,7 @@ begin
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                  C => C
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     );
278 278
                       
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-    instance_Etage4 : Etage4_Memoire
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+    instance_Etage4 : Etage4_Memoire_NS
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     generic map( Nb_bits => Nb_bits,
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                  Mem_size => Memoire_Size,
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                  Adresse_mem_size => Adresse_mem_size,
@@ -321,3 +321,4 @@ begin
321 321
         Instruction_to_5 <= Instruction_from_4;
322 322
     end process;        
323 323
 end Behavioral;
324
+

+ 2
- 2
Processeur.srcs/sources_1/new/System.vhd View File

@@ -31,7 +31,7 @@ entity System is
31 31
 end System;
32 32
 
33 33
 architecture Structural of System is
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-    component Pipeline is
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+    component Pipeline_NS is
35 35
     Generic (Nb_bits : Natural := 8;
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              Instruction_En_Memoire_Size : Natural := 29;
37 37
              Addr_Memoire_Instruction_Size : Natural := 3;
@@ -62,7 +62,7 @@ begin
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               CLK_OUT => my_CLK);
63 63
               
64 64
     -- Le processeur, augmentation de la taille de la mémoire d'instruction
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-    instance : Pipeline
65
+    instance : Pipeline_NS
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     generic map (Addr_Memoire_Instruction_Size => 8,
67 67
                  Memoire_Instruction_Size => 256)
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     port map (CLK => my_CLK,

+ 6
- 6
Processeur.xpr View File

@@ -103,37 +103,37 @@
103 103
           <Attr Name="UsedIn" Val="simulation"/>
104 104
         </FileInfo>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
107 107
         <FileInfo>
108 108
           <Attr Name="UsedIn" Val="synthesis"/>
109 109
           <Attr Name="UsedIn" Val="simulation"/>
110 110
         </FileInfo>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
113 113
         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
115 115
           <Attr Name="UsedIn" Val="simulation"/>
116 116
         </FileInfo>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
121 121
           <Attr Name="UsedIn" Val="simulation"/>
122 122
         </FileInfo>
123 123
       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
125 125
         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
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         <FileInfo>
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           <Attr Name="UsedIn" Val="synthesis"/>
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           <Attr Name="UsedIn" Val="simulation"/>
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         </FileInfo>
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       </File>
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-      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
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+      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
137 137
         <FileInfo>
138 138
           <Attr Name="UsedIn" Val="synthesis"/>
139 139
           <Attr Name="UsedIn" Val="simulation"/>

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