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Version fonctionnelle processeur non sécurisé

Paul Faure 3 months ago
parent
commit
f25ee2735a

+ 2
- 1
.gitignore View File

@@ -4,4 +4,5 @@ Processeur.hw/*
4 4
 Processeur.runs/*
5 5
 Processeur.sim/*
6 6
 vivado*
7
-.Xil
7
+.Xil
8
+*.log

+ 2
- 3
Processeur.srcs/sim_1/new/Test_Pipeline.vhd View File

@@ -45,9 +45,7 @@ architecture Behavioral of Test_Pipeline is
45 45
              Instruction_Bus_Size : Natural := 5;
46 46
              Nb_Instructions : Natural := 32;
47 47
              Nb_Registres : Natural := 16;
48
-             Memoire_Size : Natural := 32;
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-             Memoire_Adresses_Retour_Size : Natural := 16;
50
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
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+             Memoire_Size : Natural := 32);
51 49
     Port (CLK : STD_LOGIC;
52 50
           RST : STD_LOGIC;
53 51
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -80,6 +78,7 @@ begin
80 78
     
81 79
     process 
82 80
     begin
81
+        my_STD_IN <= "00000001" after 300 us, "00000010" after 710 us, "00000011" after 1120 us, "00000100" after 1530 us, "00000101" after 1940 us, "00000110" after 2350 us, "00000111" after 2760 us, "00001000" after 3170 us, "00001001" after 3580 us, "00000000" after 3990 us; 
83 82
         wait;
84 83
     end process;
85 84
 end Behavioral;

+ 22
- 57
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd View File

@@ -31,8 +31,6 @@ entity Etage1_LectureInstruction is
31 31
              Nb_bits : Natural; -- Taille d'un mot binaire
32 32
              Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
33 33
              Nb_registres : Natural; -- Nombre de registres du processeurs
34
-             Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale)
35
-             Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour
36 34
              Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA)
37 35
              Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB)
38 36
              Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC)
@@ -58,6 +56,7 @@ entity Etage1_LectureInstruction is
58 56
     Port ( CLK : in STD_LOGIC; -- Clock
59 57
            RST : in STD_LOGIC; -- Reset
60 58
            Z : in STD_LOGIC;   -- Flag Zero de l'ALU (utile pour le JMZ)
59
+           Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
61 60
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
62 61
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
63 62
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
@@ -75,23 +74,8 @@ architecture Behavioral of Etage1_LectureInstruction is
75 74
            D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
76 75
     end component;
77 76
     
78
-    component MemoireAdressesRetour is
79
-        Generic (Nb_bits : Natural;
80
-                 Addr_size : Natural;
81
-                 Mem_size : Natural);
82
-        Port ( R : in STD_LOGIC;
83
-               W : in STD_LOGIC;
84
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
85
-               RST : in STD_LOGIC;
86
-               CLK : in STD_LOGIC;
87
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
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-               E : out STD_LOGIC;
89
-               F : out STD_LOGIC);
90
-    end component;
91
-    
92 77
     -- Signaux pour récuperer l'instruction de la mémoire
93 78
     signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
94
-    signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
95 79
     signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
96 80
     
97 81
     
@@ -99,13 +83,6 @@ architecture Behavioral of Etage1_LectureInstruction is
99 83
     subtype Registre is integer range -1 to Nb_registres - 1;
100 84
     type Tab_registres is array (1 to 3) of Registre;
101 85
     signal Tableau : Tab_registres := (others => - 1);
102
-    
103
-    -- Signaux de gestion pour la mémoire des adresses de retour
104
-    signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
105
-    signal E : STD_LOGIC;
106
-    signal F : STD_LOGIC;
107
-    signal R_Aux : STD_LOGIC := '0';
108
-    signal W_Aux : STD_LOGIC := '0';
109 86
 
110 87
     -- constantes pour injecter des bulles dans le pipeline
111 88
     constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
@@ -127,21 +104,6 @@ begin
127 104
                  Mem_size => Mem_instruction_size)
128 105
     port map (Addr => Pointeur_Instruction,
129 106
               D_OUT => Instruction_courante);
130
-              
131
-    instance_MemoireAdressesRetour : MemoireAdressesRetour
132
-    generic map (Nb_bits => Addr_size_mem_instruction,
133
-                 Addr_size => Adresse_size_mem_adresse_retour,
134
-                 Mem_size => Mem_adresse_retour_size
135
-    )
136
-    port map ( R => R_Aux,
137
-               W => W_Aux,
138
-               D_IN => Pointeur_instruction_next,
139
-               RST => RST,
140
-               CLK => CLK,
141
-               D_OUT => Adresse_Retour,
142
-               E => E,
143
-               F => F
144
-    );
145 107
 
146 108
               
147 109
     process 
@@ -166,19 +128,29 @@ begin
166 128
             if (not bulles) then
167 129
                 -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
168 130
                 if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
169
-                    -- CAS PARTICULIER : CALL ou JMP, on transmet et on saute
170
-                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
131
+                    -- CAS PARTICULIER : CALL ou JMP, on transmet (en modifiant le paramètre A pour le CALL (addr de retour à stocker))et on saute
132
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); -- STOCKER
171 133
                     B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
172
-                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
134
+                    A <= ((Nb_bits - 1 downto Addr_size_mem_instruction => '0') & Pointeur_Instruction) + 1;
173 135
                     Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
174 136
                     Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
175 137
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
176
-                    -- CAS PARTICULIER : RET, on transmet et on revient 
177
-                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
178
-                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
179
-                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
180
-                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
181
-                    Pointeur_Instruction <= Adresse_Retour;
138
+                    -- CAS PARTICULIER : RET, on transmet une seule fois, on attend et on revient 
139
+                    compteur <= compteur + 1;
140
+                    if (compteur = 1) then
141
+                        C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
142
+                        B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
143
+                        A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
144
+                        Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
145
+                    elsif (compteur = 5) then
146
+                        Pointeur_Instruction <= Addr_Retour (Addr_size_mem_instruction - 1 downto 0);
147
+                        compteur <= 0;
148
+                    else 
149
+                        C <= Argument_nul;
150
+                        B <= Argument_nul;
151
+                        A <= Argument_nul;
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+                        Instruction <= Instruction_nulle;
153
+                    end if;
182 154
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
183 155
                     -- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement
184 156
                     compteur <= compteur + 1;
@@ -203,7 +175,7 @@ begin
203 175
                             locked <= true;
204 176
                         end if;
205 177
                         compteur <= compteur + 1;
206
-                        if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)))) then
178
+                        if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) * 1000) then
207 179
                             Pointeur_Instruction <= Pointeur_Instruction + 1;
208 180
                             compteur <= 0;
209 181
                         end if;
@@ -278,12 +250,5 @@ begin
278 250
         )
279 251
     );
280 252
     
281
-    -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
282
-    R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
283
-             '0';
284
-    W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
285
-             '0';
286
-             
287
-             
288
-    Pointeur_instruction_next <= Pointeur_instruction + 1;
253
+
289 254
 end Behavioral;

+ 1
- 1
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd View File

@@ -168,7 +168,7 @@ begin
168 168
     
169 169
     -- Un multiplexeur pourrait être utilisé ici, mais cela n'a pas été jugé pertinent
170 170
     Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else
171
-                                STD_IN when IN_2_Instruction = Code_Instruction_GET else
171
+                                STD_IN when IN_5_Instruction = Code_Instruction_GET else
172 172
                                 IN_5_B;
173 173
     
174 174
     

+ 13
- 5
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File

@@ -169,11 +169,19 @@ begin
169 169
     CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
170 170
              '0';
171 171
              
172
-    New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
173
-    EBP <= New_EBP when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_CALL else 
174
-           Last_EBP (Adresse_mem_size - 1 downto 0) when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_RET else
175
-           (others => '0') when RST = '0' else 
176
-           EBP;
172
+    process 
173
+    begin
174
+        wait until CLK'event and CLK = '1';
175
+        if (IN_Instruction = Code_Instruction_CALL) then
176
+            EBP <= New_EBP;
177
+        elsif (IN_Instruction = Code_Instruction_RET) then 
178
+            EBP <= Last_EBP (Adresse_mem_size - 1 downto 0);
179
+        elsif (RST = '0') then
180
+            EBP <= (others => '0');
181
+        end if;
182
+    end process;
183
+           
184
+   New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
177 185
     IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
178 186
            
179 187
     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;

+ 7
- 2
Processeur.srcs/sources_1/new/MemoireDonnees.vhd View File

@@ -47,8 +47,7 @@ begin
47 47
                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
48 48
                 MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
49 49
             elsif (RET = '1') then
50
-                OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2));
51
-                OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
50
+                MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto ((to_integer(unsigned(Addr)) - 2) * Nb_bits)) <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr)));
52 51
             elsif (RW = '0') then
53 52
                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
54 53
             end if;
@@ -57,4 +56,10 @@ begin
57 56
     
58 57
     -- Lecture assynchrone et en permanence
59 58
     D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
59
+    
60
+    -- Sortie lors du ret en assynchrone
61
+    OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)) when (RET = '1') else 
62
+               (others => '0'); 
63
+    OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)) when (RET = '1') else 
64
+                   (others => '0');
60 65
 end Behavioral;

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
File diff suppressed because it is too large
View File


+ 11
- 16
Processeur.srcs/sources_1/new/Pipeline.vhd View File

@@ -41,9 +41,7 @@ entity Pipeline is
41 41
              Nb_Registres : Natural := 16;
42 42
              Addr_registres_size : Natural := 4;
43 43
              Memoire_Size : Natural := 32;
44
-             Adresse_mem_size : Natural := 5;
45
-             Memoire_Adresses_Retour_Size : Natural := 16;
46
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
44
+             Adresse_mem_size : Natural := 5);
47 45
     Port (CLK : STD_LOGIC;
48 46
           RST : STD_LOGIC;
49 47
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -59,8 +57,6 @@ architecture Behavioral of Pipeline is
59 57
              Nb_bits : Natural;
60 58
              Instruction_bus_size : Natural;
61 59
              Nb_registres : Natural;
62
-             Mem_adresse_retour_size : Natural;
63
-             Adresse_size_mem_adresse_retour : Natural;
64 60
              Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
65 61
              Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
66 62
              Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
@@ -73,6 +69,7 @@ architecture Behavioral of Pipeline is
73 69
     Port ( CLK : in STD_LOGIC;
74 70
            RST : in STD_LOGIC;
75 71
            Z : in STD_LOGIC;
72
+           Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
76 73
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
77 74
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
78 75
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -130,8 +127,6 @@ architecture Behavioral of Pipeline is
130 127
                   Mem_size : Natural;
131 128
                   Adresse_mem_size : Natural;
132 129
                   Instruction_bus_size : Natural;
133
-                  Mem_EBP_size : Natural;
134
-                  Adresse_size_mem_EBP : Natural;
135 130
                   Bits_Controle_LC : STD_LOGIC_VECTOR;
136 131
                   Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
137 132
                   Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
@@ -145,7 +140,8 @@ architecture Behavioral of Pipeline is
145 140
                IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
146 141
                OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
147 142
                OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
148
-               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
143
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
144
+               OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); 
149 145
     end component;
150 146
     
151 147
     signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
@@ -180,14 +176,15 @@ architecture Behavioral of Pipeline is
180 176
     signal Z : STD_LOGIC := '0';
181 177
     signal O : STD_LOGIC := '0';
182 178
     signal C : STD_LOGIC := '0';
179
+    signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
183 180
     
184 181
     constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
185 182
     constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
186 183
     constant Bits_Controle_LC_3         : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
187 184
     constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
188
-    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
189
-    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
190
-    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
185
+    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC
186
+    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111";
187
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP
191 188
     constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
192 189
     constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
193 190
     constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
@@ -210,8 +207,6 @@ begin
210 207
                  Nb_bits => Nb_bits,
211 208
                  Instruction_bus_size => Instruction_Bus_Size,
212 209
                  Nb_registres => Nb_Registres,
213
-                 Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
214
-                 Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
215 210
                  Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
216 211
                  Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
217 212
                  Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
@@ -226,6 +221,7 @@ begin
226 221
         CLK => CLK,
227 222
         RST => RST,
228 223
         Z => Z,
224
+        Addr_Retour => AdresseRetour,
229 225
         A => A_from_1,
230 226
         B => B_from_1,
231 227
         C => C_from_1,
@@ -285,8 +281,6 @@ begin
285 281
                  Mem_size => Memoire_Size,
286 282
                  Adresse_mem_size => Adresse_mem_size,
287 283
                  Instruction_bus_size => Instruction_Bus_Size,
288
-                 Mem_EBP_size => Memoire_Adresses_Retour_Size,
289
-                 Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
290 284
                  Bits_Controle_LC => Bits_Controle_LC_4,
291 285
                  Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
292 286
                  Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
@@ -301,7 +295,8 @@ begin
301 295
                  IN_Instruction => Instruction_to_4,
302 296
                  OUT_A => A_from_4,
303 297
                  OUT_B => B_from_4,
304
-                 OUT_Instruction => Instruction_from_4
298
+                 OUT_Instruction => Instruction_from_4,
299
+                 OUT_AddrRetour => AdresseRetour
305 300
     );
306 301
 
307 302
     process

+ 3
- 11
Processeur.srcs/sources_1/new/System.vhd View File

@@ -39,9 +39,7 @@ architecture Structural of System is
39 39
              Instruction_Bus_Size : Natural := 5;
40 40
              Nb_Instructions : Natural := 32;
41 41
              Nb_Registres : Natural := 16;
42
-             Memoire_Size : Natural := 32;
43
-             Memoire_Adresses_Retour_Size : Natural := 16;
44
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
42
+             Memoire_Size : Natural := 32);
45 43
     Port (CLK : STD_LOGIC;
46 44
           RST : STD_LOGIC;
47 45
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -56,17 +54,11 @@ architecture Structural of System is
56 54
     -- signaux auxiliaires
57 55
     signal my_RST : STD_LOGIC;
58 56
     signal my_CLK : STD_LOGIC;
59
-    signal buff_CLK : STD_LOGIC;
60 57
         
61
-begin
62
-    -- Premier diviseur de clock
58
+begin     
59
+    -- Diviseur de clock
63 60
     clk_div : Clock_Divider
64 61
     port map (CLK_IN => CLK,
65
-              CLK_OUT => buff_CLK);
66
-              
67
-    -- Second diviseur de clock
68
-    clk_div_2 : Clock_Divider
69
-    port map (CLK_IN => buff_CLK,
70 62
               CLK_OUT => my_CLK);
71 63
               
72 64
     -- Le processeur, augmentation de la taille de la mémoire d'instruction

+ 2
- 2
Processeur.xpr View File

@@ -32,7 +32,7 @@
32 32
     <Option Name="EnableBDX" Val="FALSE"/>
33 33
     <Option Name="DSABoardId" Val="basys3"/>
34 34
     <Option Name="DSANumComputeUnits" Val="16"/>
35
-    <Option Name="WTXSimLaunchSim" Val="287"/>
35
+    <Option Name="WTXSimLaunchSim" Val="339"/>
36 36
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -240,7 +240,7 @@
240 240
       </File>
241 241
       <Config>
242 242
         <Option Name="DesignMode" Val="RTL"/>
243
-        <Option Name="TopModule" Val="Test_Etage4_Memoire"/>
243
+        <Option Name="TopModule" Val="Test_Pipeline"/>
244 244
         <Option Name="TopLib" Val="xil_defaultlib"/>
245 245
         <Option Name="TransportPathDelay" Val="0"/>
246 246
         <Option Name="TransportIntDelay" Val="0"/>

+ 144
- 38
SimulationsConfig/Test_Pipeline_behav1.wcfg View File

@@ -3,163 +3,269 @@
3 3
    <wave_state>
4 4
    </wave_state>
5 5
    <db_ref_list>
6
-      <db_ref path="Test_Pipeline_behav1.wdb" id="1">
6
+      <db_ref path="Test_Pipeline_behav.wdb" id="1">
7 7
          <top_modules>
8 8
             <top_module name="Test_Pipeline" />
9 9
          </top_modules>
10 10
       </db_ref>
11 11
    </db_ref_list>
12 12
    <zoom_setting>
13
-      <ZoomStartTime time="320666666fs"></ZoomStartTime>
14
-      <ZoomEndTime time="441266667fs"></ZoomEndTime>
15
-      <Cursor1Time time="404267000fs"></Cursor1Time>
13
+      <ZoomStartTime time="9750000000fs"></ZoomStartTime>
14
+      <ZoomEndTime time="10289000001fs"></ZoomEndTime>
15
+      <Cursor1Time time="10000000000fs"></Cursor1Time>
16 16
    </zoom_setting>
17 17
    <column_width_setting>
18 18
       <NameColumnWidth column_width="146"></NameColumnWidth>
19
-      <ValueColumnWidth column_width="73"></ValueColumnWidth>
19
+      <ValueColumnWidth column_width="71"></ValueColumnWidth>
20 20
    </column_width_setting>
21
-   <WVObjectSize size="10" />
22
-   <wvobject fp_name="/Test_Pipeline/my_CLK" type="logic">
21
+   <WVObjectSize size="12" />
22
+   <wvobject type="logic" fp_name="/Test_Pipeline/my_CLK">
23 23
       <obj_property name="ElementShortName">my_CLK</obj_property>
24 24
       <obj_property name="ObjectShortName">my_CLK</obj_property>
25 25
    </wvobject>
26
-   <wvobject fp_name="/Test_Pipeline/my_RST" type="logic">
26
+   <wvobject type="logic" fp_name="/Test_Pipeline/my_RST">
27 27
       <obj_property name="ElementShortName">my_RST</obj_property>
28 28
       <obj_property name="ObjectShortName">my_RST</obj_property>
29 29
    </wvobject>
30
-   <wvobject fp_name="/Test_Pipeline/my_STD_IN" type="array">
30
+   <wvobject type="array" fp_name="/Test_Pipeline/my_STD_IN">
31 31
       <obj_property name="ElementShortName">my_STD_IN[7:0]</obj_property>
32 32
       <obj_property name="ObjectShortName">my_STD_IN[7:0]</obj_property>
33 33
    </wvobject>
34
-   <wvobject fp_name="/Test_Pipeline/my_STD_OUT" type="array">
34
+   <wvobject type="array" fp_name="/Test_Pipeline/my_STD_OUT">
35 35
       <obj_property name="ElementShortName">my_STD_OUT[7:0]</obj_property>
36 36
       <obj_property name="ObjectShortName">my_STD_OUT[7:0]</obj_property>
37 37
    </wvobject>
38
-   <wvobject fp_name="/Test_Pipeline/CLK_period" type="other">
38
+   <wvobject type="other" fp_name="/Test_Pipeline/CLK_period">
39 39
       <obj_property name="ElementShortName">CLK_period</obj_property>
40 40
       <obj_property name="ObjectShortName">CLK_period</obj_property>
41 41
    </wvobject>
42
-   <wvobject fp_name="group20" type="group">
42
+   <wvobject type="group" fp_name="group20">
43 43
       <obj_property name="label">Etage1</obj_property>
44 44
       <obj_property name="DisplayName">label</obj_property>
45 45
       <obj_property name="isExpanded"></obj_property>
46
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_1" type="array">
46
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_1">
47 47
          <obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
48 48
          <obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
49 49
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
50 50
       </wvobject>
51
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_1" type="array">
51
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_1">
52 52
          <obj_property name="ElementShortName">A_from_1[7:0]</obj_property>
53 53
          <obj_property name="ObjectShortName">A_from_1[7:0]</obj_property>
54 54
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
55 55
       </wvobject>
56
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_1" type="array">
56
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_1">
57 57
          <obj_property name="ElementShortName">B_from_1[7:0]</obj_property>
58 58
          <obj_property name="ObjectShortName">B_from_1[7:0]</obj_property>
59 59
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
60 60
       </wvobject>
61
-      <wvobject fp_name="/Test_Pipeline/instance/C_from_1" type="array">
61
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/C_from_1">
62 62
          <obj_property name="ElementShortName">C_from_1[7:0]</obj_property>
63 63
          <obj_property name="ObjectShortName">C_from_1[7:0]</obj_property>
64 64
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
65 65
       </wvobject>
66 66
    </wvobject>
67
-   <wvobject fp_name="group21" type="group">
67
+   <wvobject type="group" fp_name="group21">
68 68
       <obj_property name="label">Etage2</obj_property>
69 69
       <obj_property name="DisplayName">label</obj_property>
70 70
       <obj_property name="isExpanded"></obj_property>
71
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_2" type="array">
71
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_2">
72 72
          <obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
73 73
          <obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
74 74
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
75 75
       </wvobject>
76
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_2" type="array">
76
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_2">
77 77
          <obj_property name="ElementShortName">A_from_2[7:0]</obj_property>
78 78
          <obj_property name="ObjectShortName">A_from_2[7:0]</obj_property>
79 79
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
80 80
       </wvobject>
81
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_2" type="array">
81
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_2">
82 82
          <obj_property name="ElementShortName">B_from_2[7:0]</obj_property>
83 83
          <obj_property name="ObjectShortName">B_from_2[7:0]</obj_property>
84 84
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
85 85
       </wvobject>
86
-      <wvobject fp_name="/Test_Pipeline/instance/C_from_2" type="array">
86
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/C_from_2">
87 87
          <obj_property name="ElementShortName">C_from_2[7:0]</obj_property>
88 88
          <obj_property name="ObjectShortName">C_from_2[7:0]</obj_property>
89 89
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
90 90
       </wvobject>
91 91
    </wvobject>
92
-   <wvobject fp_name="group22" type="group">
92
+   <wvobject type="group" fp_name="group22">
93 93
       <obj_property name="label">Etage3</obj_property>
94 94
       <obj_property name="DisplayName">label</obj_property>
95 95
       <obj_property name="isExpanded"></obj_property>
96
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_3" type="array">
96
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_3">
97 97
          <obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
98 98
          <obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
99 99
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
100 100
       </wvobject>
101
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_3" type="array">
101
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_3">
102 102
          <obj_property name="ElementShortName">A_from_3[7:0]</obj_property>
103 103
          <obj_property name="ObjectShortName">A_from_3[7:0]</obj_property>
104 104
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
105 105
       </wvobject>
106
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_3" type="array">
106
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_3">
107 107
          <obj_property name="ElementShortName">B_from_3[7:0]</obj_property>
108 108
          <obj_property name="ObjectShortName">B_from_3[7:0]</obj_property>
109 109
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
110 110
       </wvobject>
111 111
    </wvobject>
112
-   <wvobject fp_name="group23" type="group">
112
+   <wvobject type="group" fp_name="group23">
113 113
       <obj_property name="label">Etage4</obj_property>
114 114
       <obj_property name="DisplayName">label</obj_property>
115 115
       <obj_property name="isExpanded"></obj_property>
116
-      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_4" type="array">
116
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/Instruction_from_4">
117 117
          <obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
118 118
          <obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
119 119
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
120 120
       </wvobject>
121
-      <wvobject fp_name="/Test_Pipeline/instance/A_from_4" type="array">
121
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/A_from_4">
122 122
          <obj_property name="ElementShortName">A_from_4[7:0]</obj_property>
123 123
          <obj_property name="ObjectShortName">A_from_4[7:0]</obj_property>
124 124
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
125 125
       </wvobject>
126
-      <wvobject fp_name="/Test_Pipeline/instance/B_from_4" type="array">
126
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/B_from_4">
127 127
          <obj_property name="ElementShortName">B_from_4[7:0]</obj_property>
128 128
          <obj_property name="ObjectShortName">B_from_4[7:0]</obj_property>
129 129
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
130 130
       </wvobject>
131 131
    </wvobject>
132
-   <wvobject fp_name="group31" type="group">
132
+   <wvobject type="group" fp_name="group31">
133 133
       <obj_property name="label">Registres</obj_property>
134 134
       <obj_property name="DisplayName">label</obj_property>
135
-      <obj_property name="isExpanded"></obj_property>
136
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/REGISTRES" type="array">
135
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/REGISTRES">
137 136
          <obj_property name="ElementShortName">REGISTRES[127:0]</obj_property>
138 137
          <obj_property name="ObjectShortName">REGISTRES[127:0]</obj_property>
139 138
       </wvobject>
140
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrA" type="array">
139
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrA">
141 140
          <obj_property name="ElementShortName">AddrA[3:0]</obj_property>
142 141
          <obj_property name="ObjectShortName">AddrA[3:0]</obj_property>
143 142
       </wvobject>
144
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrB" type="array">
143
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrB">
145 144
          <obj_property name="ElementShortName">AddrB[3:0]</obj_property>
146 145
          <obj_property name="ObjectShortName">AddrB[3:0]</obj_property>
147 146
       </wvobject>
148
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrC" type="array">
147
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrC">
149 148
          <obj_property name="ElementShortName">AddrC[3:0]</obj_property>
150 149
          <obj_property name="ObjectShortName">AddrC[3:0]</obj_property>
151 150
       </wvobject>
152
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrW" type="array">
151
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrW">
153 152
          <obj_property name="ElementShortName">AddrW[3:0]</obj_property>
154 153
          <obj_property name="ObjectShortName">AddrW[3:0]</obj_property>
155 154
       </wvobject>
156
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/W" type="logic">
155
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/W">
157 156
          <obj_property name="ElementShortName">W</obj_property>
158 157
          <obj_property name="ObjectShortName">W</obj_property>
159 158
       </wvobject>
160
-      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/DATA" type="array">
159
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/DATA">
161 160
          <obj_property name="ElementShortName">DATA[7:0]</obj_property>
162 161
          <obj_property name="ObjectShortName">DATA[7:0]</obj_property>
163 162
       </wvobject>
164 163
    </wvobject>
164
+   <wvobject type="group" fp_name="group115">
165
+      <obj_property name="label">Memoire</obj_property>
166
+      <obj_property name="DisplayName">label</obj_property>
167
+      <obj_property name="isExpanded"></obj_property>
168
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/MEMORY">
169
+         <obj_property name="ElementShortName">MEMORY[255:0]</obj_property>
170
+         <obj_property name="ObjectShortName">MEMORY[255:0]</obj_property>
171
+      </wvobject>
172
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_OUT">
173
+         <obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
174
+         <obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
175
+      </wvobject>
176
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_AddrRet">
177
+         <obj_property name="ElementShortName">OUT_AddrRet[7:0]</obj_property>
178
+         <obj_property name="ObjectShortName">OUT_AddrRet[7:0]</obj_property>
179
+      </wvobject>
180
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_EBP">
181
+         <obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
182
+         <obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
183
+      </wvobject>
184
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_AddrRet">
185
+         <obj_property name="ElementShortName">IN_AddrRet[7:0]</obj_property>
186
+         <obj_property name="ObjectShortName">IN_AddrRet[7:0]</obj_property>
187
+      </wvobject>
188
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_EBP">
189
+         <obj_property name="ElementShortName">IN_EBP[7:0]</obj_property>
190
+         <obj_property name="ObjectShortName">IN_EBP[7:0]</obj_property>
191
+      </wvobject>
192
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/CALL">
193
+         <obj_property name="ElementShortName">CALL</obj_property>
194
+         <obj_property name="ObjectShortName">CALL</obj_property>
195
+      </wvobject>
196
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RET">
197
+         <obj_property name="ElementShortName">RET</obj_property>
198
+         <obj_property name="ObjectShortName">RET</obj_property>
199
+      </wvobject>
200
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/Addr">
201
+         <obj_property name="ElementShortName">Addr[4:0]</obj_property>
202
+         <obj_property name="ObjectShortName">Addr[4:0]</obj_property>
203
+      </wvobject>
204
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_IN">
205
+         <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
206
+         <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
207
+      </wvobject>
208
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RW">
209
+         <obj_property name="ElementShortName">RW</obj_property>
210
+         <obj_property name="ObjectShortName">RW</obj_property>
211
+      </wvobject>
212
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Last_EBP">
213
+         <obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
214
+         <obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
215
+      </wvobject>
216
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/EBP">
217
+         <obj_property name="ElementShortName">EBP[4:0]</obj_property>
218
+         <obj_property name="ObjectShortName">EBP[4:0]</obj_property>
219
+      </wvobject>
220
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees">
221
+         <obj_property name="ElementShortName">Addr_MemoireDonnees[4:0]</obj_property>
222
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees[4:0]</obj_property>
223
+      </wvobject>
224
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/IN_Addr_MemoireDonnees">
225
+         <obj_property name="ElementShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
226
+         <obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
227
+      </wvobject>
228
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees_EBP">
229
+         <obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
230
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
231
+      </wvobject>
232
+   </wvobject>
233
+   <wvobject type="group" fp_name="group121">
234
+      <obj_property name="label">Instructions</obj_property>
235
+      <obj_property name="DisplayName">label</obj_property>
236
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage1/Z">
237
+         <obj_property name="ElementShortName">Z</obj_property>
238
+         <obj_property name="ObjectShortName">Z</obj_property>
239
+      </wvobject>
240
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Addr_Retour">
241
+         <obj_property name="ElementShortName">Addr_Retour[7:0]</obj_property>
242
+         <obj_property name="ObjectShortName">Addr_Retour[7:0]</obj_property>
243
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
244
+      </wvobject>
245
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Pointeur_instruction">
246
+         <obj_property name="ElementShortName">Pointeur_instruction[7:0]</obj_property>
247
+         <obj_property name="ObjectShortName">Pointeur_instruction[7:0]</obj_property>
248
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
249
+      </wvobject>
250
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Instruction_courante">
251
+         <obj_property name="ElementShortName">Instruction_courante[28:0]</obj_property>
252
+         <obj_property name="ObjectShortName">Instruction_courante[28:0]</obj_property>
253
+      </wvobject>
254
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Tableau">
255
+         <obj_property name="ElementShortName">Tableau[1:3]</obj_property>
256
+         <obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
257
+      </wvobject>
258
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/bulles">
259
+         <obj_property name="ElementShortName">bulles</obj_property>
260
+         <obj_property name="ObjectShortName">bulles</obj_property>
261
+      </wvobject>
262
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/compteur">
263
+         <obj_property name="ElementShortName">compteur</obj_property>
264
+         <obj_property name="ObjectShortName">compteur</obj_property>
265
+      </wvobject>
266
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/locked">
267
+         <obj_property name="ElementShortName">locked</obj_property>
268
+         <obj_property name="ObjectShortName">locked</obj_property>
269
+      </wvobject>
270
+   </wvobject>
165 271
 </wave_config>

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