From f25ee2735abfbaf0cd46ea0236f2ef267e752ec7 Mon Sep 17 00:00:00 2001 From: pfaure Date: Wed, 23 Jun 2021 10:55:25 +0200 Subject: [PATCH] =?UTF-8?q?Version=20fonctionnelle=20processeur=20non=20s?= =?UTF-8?q?=C3=A9curis=C3=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 3 +- Processeur.srcs/sim_1/new/Test_Pipeline.vhd | 5 +- .../new/Etage1_LectureInstruction.vhd | 79 +++----- .../sources_1/new/Etage2-5_Registres.vhd | 2 +- .../sources_1/new/Etage4_Memoire.vhd | 18 +- .../sources_1/new/MemoireDonnees.vhd | 9 +- .../sources_1/new/MemoireInstructions.vhd | 2 +- Processeur.srcs/sources_1/new/Pipeline.vhd | 27 ++- Processeur.srcs/sources_1/new/System.vhd | 14 +- Processeur.xpr | 4 +- SimulationsConfig/Test_Pipeline_behav1.wcfg | 182 ++++++++++++++---- 11 files changed, 208 insertions(+), 137 deletions(-) diff --git a/.gitignore b/.gitignore index ddb4605..64b8323 100644 --- a/.gitignore +++ b/.gitignore @@ -4,4 +4,5 @@ Processeur.hw/* Processeur.runs/* Processeur.sim/* vivado* -.Xil \ No newline at end of file +.Xil +*.log diff --git a/Processeur.srcs/sim_1/new/Test_Pipeline.vhd b/Processeur.srcs/sim_1/new/Test_Pipeline.vhd index 454feab..d8430f8 100644 --- a/Processeur.srcs/sim_1/new/Test_Pipeline.vhd +++ b/Processeur.srcs/sim_1/new/Test_Pipeline.vhd @@ -45,9 +45,7 @@ architecture Behavioral of Test_Pipeline is Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; - Memoire_Size : Natural := 32; - Memoire_Adresses_Retour_Size : Natural := 16; - Adresse_Memoire_Adresses_Retour_Size : Natural := 4); + Memoire_Size : Natural := 32); Port (CLK : STD_LOGIC; RST : STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -80,6 +78,7 @@ begin process begin + my_STD_IN <= "00000001" after 300 us, "00000010" after 710 us, "00000011" after 1120 us, "00000100" after 1530 us, "00000101" after 1940 us, "00000110" after 2350 us, "00000111" after 2760 us, "00001000" after 3170 us, "00001001" after 3580 us, "00000000" after 3990 us; wait; end process; end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd index 3c09720..fd36b0c 100644 --- a/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd +++ b/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd @@ -31,8 +31,6 @@ entity Etage1_LectureInstruction is Nb_bits : Natural; -- Taille d'un mot binaire Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction) Nb_registres : Natural; -- Nombre de registres du processeurs - Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale) - Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA) Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB) Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC) @@ -58,6 +56,7 @@ entity Etage1_LectureInstruction is Port ( CLK : in STD_LOGIC; -- Clock RST : in STD_LOGIC; -- Reset Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ) + Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4 A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C @@ -75,23 +74,8 @@ architecture Behavioral of Etage1_LectureInstruction is D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); end component; - component MemoireAdressesRetour is - Generic (Nb_bits : Natural; - Addr_size : Natural; - Mem_size : Natural); - Port ( R : in STD_LOGIC; - W : in STD_LOGIC; - D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); - RST : in STD_LOGIC; - CLK : in STD_LOGIC; - D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); - E : out STD_LOGIC; - F : out STD_LOGIC); - end component; - -- Signaux pour récuperer l'instruction de la mémoire signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0'); - signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0'); signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0'); @@ -99,13 +83,6 @@ architecture Behavioral of Etage1_LectureInstruction is subtype Registre is integer range -1 to Nb_registres - 1; type Tab_registres is array (1 to 3) of Registre; signal Tableau : Tab_registres := (others => - 1); - - -- Signaux de gestion pour la mémoire des adresses de retour - signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0'); - signal E : STD_LOGIC; - signal F : STD_LOGIC; - signal R_Aux : STD_LOGIC := '0'; - signal W_Aux : STD_LOGIC := '0'; -- constantes pour injecter des bulles dans le pipeline constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0'); @@ -127,21 +104,6 @@ begin Mem_size => Mem_instruction_size) port map (Addr => Pointeur_Instruction, D_OUT => Instruction_courante); - - instance_MemoireAdressesRetour : MemoireAdressesRetour - generic map (Nb_bits => Addr_size_mem_instruction, - Addr_size => Adresse_size_mem_adresse_retour, - Mem_size => Mem_adresse_retour_size - ) - port map ( R => R_Aux, - W => W_Aux, - D_IN => Pointeur_instruction_next, - RST => RST, - CLK => CLK, - D_OUT => Adresse_Retour, - E => E, - F => F - ); process @@ -166,19 +128,29 @@ begin if (not bulles) then -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if) if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then - -- CAS PARTICULIER : CALL ou JMP, on transmet et on saute - C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); + -- CAS PARTICULIER : CALL ou JMP, on transmet (en modifiant le paramètre A pour le CALL (addr de retour à stocker))et on saute + C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); -- STOCKER B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); - A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); + A <= ((Nb_bits - 1 downto Addr_size_mem_instruction => '0') & Pointeur_Instruction) + 1; Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits); elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then - -- CAS PARTICULIER : RET, on transmet et on revient - C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); - B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); - A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); - Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); - Pointeur_Instruction <= Adresse_Retour; + -- CAS PARTICULIER : RET, on transmet une seule fois, on attend et on revient + compteur <= compteur + 1; + if (compteur = 1) then + C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); + B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits); + A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits); + Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits); + elsif (compteur = 5) then + Pointeur_Instruction <= Addr_Retour (Addr_size_mem_instruction - 1 downto 0); + compteur <= 0; + else + C <= Argument_nul; + B <= Argument_nul; + A <= Argument_nul; + Instruction <= Instruction_nulle; + end if; elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then -- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement compteur <= compteur + 1; @@ -203,7 +175,7 @@ begin locked <= true; end if; compteur <= compteur + 1; - if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits)))) then + if (compteur + 1 = to_integer(unsigned(Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits))) * 1000) then Pointeur_Instruction <= Pointeur_Instruction + 1; compteur <= 0; end if; @@ -278,12 +250,5 @@ begin ) ); - -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour - R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else - '0'; - W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else - '0'; - - - Pointeur_instruction_next <= Pointeur_instruction + 1; + end Behavioral; diff --git a/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd b/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd index f7ac55a..881c723 100644 --- a/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd +++ b/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd @@ -168,7 +168,7 @@ begin -- Un multiplexeur pourrait être utilisé ici, mais cela n'a pas été jugé pertinent Entree_BancRegistre_DATA <= (others => '0') when RST = '0' else - STD_IN when IN_2_Instruction = Code_Instruction_GET else + STD_IN when IN_5_Instruction = Code_Instruction_GET else IN_5_B; diff --git a/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd b/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd index 0c12e4d..cb745f6 100644 --- a/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd +++ b/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd @@ -169,11 +169,19 @@ begin CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else '0'; - New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2; - EBP <= New_EBP when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_CALL else - Last_EBP (Adresse_mem_size - 1 downto 0) when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_RET else - (others => '0') when RST = '0' else - EBP; + process + begin + wait until CLK'event and CLK = '1'; + if (IN_Instruction = Code_Instruction_CALL) then + EBP <= New_EBP; + elsif (IN_Instruction = Code_Instruction_RET) then + EBP <= Last_EBP (Adresse_mem_size - 1 downto 0); + elsif (RST = '0') then + EBP <= (others => '0'); + end if; + end process; + + New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2; IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP; Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP; diff --git a/Processeur.srcs/sources_1/new/MemoireDonnees.vhd b/Processeur.srcs/sources_1/new/MemoireDonnees.vhd index 2c71dd1..c238e61 100644 --- a/Processeur.srcs/sources_1/new/MemoireDonnees.vhd +++ b/Processeur.srcs/sources_1/new/MemoireDonnees.vhd @@ -47,8 +47,7 @@ begin MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP; MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet; elsif (RET = '1') then - OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)); - OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)); + MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto ((to_integer(unsigned(Addr)) - 2) * Nb_bits)) <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))); elsif (RW = '0') then MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN; end if; @@ -57,4 +56,10 @@ begin -- Lecture assynchrone et en permanence D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr))); + + -- Sortie lors du ret en assynchrone + OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)) when (RET = '1') else + (others => '0'); + OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)) when (RET = '1') else + (others => '0'); end Behavioral; \ No newline at end of file diff --git a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd index 43743d5..0d10e0b 100644 --- a/Processeur.srcs/sources_1/new/MemoireInstructions.vhd +++ b/Processeur.srcs/sources_1/new/MemoireInstructions.vhd @@ -32,7 +32,7 @@ end MemoireInstructions; architecture Behavioral of MemoireInstructions is -- Do not touch until (-- Skadoosh) -- Do not add any Skadoosh - signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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+ signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101010000000000000000000000001000100000000000000000000000001010000000000000101100000000100110011010100001011000000000101100001110000000000000000001001000000000000101000000000011100000110100000000000000000100100000000000000000000000010011000000010000101100000000010110000110000000001000000000101100001011000000000000000001011000010100000001000000000011110110001000000000000000000100000000010000000000000000000001000000000000000000000001010010000000100000001000000000100000000000000000100000000001010000000100000101000000000011010000000000000001000000000101000000001000011000000000001010000000000000101100000000100110010110100001100000000000101100001101000000110000000001011000011000000001000000000010110000101100000100000000000101100001010000000000000000000001000001000000010000000010010100000010000001011000000000001000000010000000110000001001001000000110000000100000000010000000001000000000000000000111000001011000000110000000001001000000110000000000000000100000111110100000000000000000001100000011000000110000000101001000000110000000000000000001010000000100000001000000100100100000010000010100000000001000000000010000000000000000010010000000000000000000000001010000000000000000000000000001011000001110000011100000000010110000011000000110000000000101100000101000001000000000001011000001000000001000000000010110000001100000001000000000101100000010000000000000000001011000000000000010100000000010000000010100000010000000000100000000010000000010000000001111001101110000000000000000010000000000000000010000000000000100000010000000100000010001001000001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-- Skadoosh begin D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr))); diff --git a/Processeur.srcs/sources_1/new/Pipeline.vhd b/Processeur.srcs/sources_1/new/Pipeline.vhd index 2d2d639..d10dadf 100644 --- a/Processeur.srcs/sources_1/new/Pipeline.vhd +++ b/Processeur.srcs/sources_1/new/Pipeline.vhd @@ -41,9 +41,7 @@ entity Pipeline is Nb_Registres : Natural := 16; Addr_registres_size : Natural := 4; Memoire_Size : Natural := 32; - Adresse_mem_size : Natural := 5; - Memoire_Adresses_Retour_Size : Natural := 16; - Adresse_Memoire_Adresses_Retour_Size : Natural := 4); + Adresse_mem_size : Natural := 5); Port (CLK : STD_LOGIC; RST : STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -59,8 +57,6 @@ architecture Behavioral of Pipeline is Nb_bits : Natural; Instruction_bus_size : Natural; Nb_registres : Natural; - Mem_adresse_retour_size : Natural; - Adresse_size_mem_adresse_retour : Natural; Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; @@ -73,6 +69,7 @@ architecture Behavioral of Pipeline is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; Z : in STD_LOGIC; + Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4 A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -130,8 +127,6 @@ architecture Behavioral of Pipeline is Mem_size : Natural; Adresse_mem_size : Natural; Instruction_bus_size : Natural; - Mem_EBP_size : Natural; - Adresse_size_mem_EBP : Natural; Bits_Controle_LC : STD_LOGIC_VECTOR; Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; @@ -145,7 +140,8 @@ architecture Behavioral of Pipeline is IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); - OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); + OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); + OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); end component; signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); @@ -180,14 +176,15 @@ architecture Behavioral of Pipeline is signal Z : STD_LOGIC := '0'; signal O : STD_LOGIC := '0'; signal C : STD_LOGIC := '0'; + signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111"; constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001"; constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000"; constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001"; - constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; - constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111"; - constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111"; + constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC + constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111"; + constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000"; constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110"; constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111"; @@ -210,8 +207,6 @@ begin Nb_bits => Nb_bits, Instruction_bus_size => Instruction_Bus_Size, Nb_registres => Nb_Registres, - Mem_adresse_retour_size => Memoire_Adresses_Retour_Size, - Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size, Instructions_critiques_lecture_A => Instructions_critiques_lecture_A, Instructions_critiques_lecture_B => Instructions_critiques_lecture_B, Instructions_critiques_lecture_C => Instructions_critiques_lecture_C, @@ -226,6 +221,7 @@ begin CLK => CLK, RST => RST, Z => Z, + Addr_Retour => AdresseRetour, A => A_from_1, B => B_from_1, C => C_from_1, @@ -285,8 +281,6 @@ begin Mem_size => Memoire_Size, Adresse_mem_size => Adresse_mem_size, Instruction_bus_size => Instruction_Bus_Size, - Mem_EBP_size => Memoire_Adresses_Retour_Size, - Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size, Bits_Controle_LC => Bits_Controle_LC_4, Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN, Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP, @@ -301,7 +295,8 @@ begin IN_Instruction => Instruction_to_4, OUT_A => A_from_4, OUT_B => B_from_4, - OUT_Instruction => Instruction_from_4 + OUT_Instruction => Instruction_from_4, + OUT_AddrRetour => AdresseRetour ); process diff --git a/Processeur.srcs/sources_1/new/System.vhd b/Processeur.srcs/sources_1/new/System.vhd index c954a9b..fb553fb 100644 --- a/Processeur.srcs/sources_1/new/System.vhd +++ b/Processeur.srcs/sources_1/new/System.vhd @@ -39,9 +39,7 @@ architecture Structural of System is Instruction_Bus_Size : Natural := 5; Nb_Instructions : Natural := 32; Nb_Registres : Natural := 16; - Memoire_Size : Natural := 32; - Memoire_Adresses_Retour_Size : Natural := 16; - Adresse_Memoire_Adresses_Retour_Size : Natural := 4); + Memoire_Size : Natural := 32); Port (CLK : STD_LOGIC; RST : STD_LOGIC; STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); @@ -56,17 +54,11 @@ architecture Structural of System is -- signaux auxiliaires signal my_RST : STD_LOGIC; signal my_CLK : STD_LOGIC; - signal buff_CLK : STD_LOGIC; -begin - -- Premier diviseur de clock +begin + -- Diviseur de clock clk_div : Clock_Divider port map (CLK_IN => CLK, - CLK_OUT => buff_CLK); - - -- Second diviseur de clock - clk_div_2 : Clock_Divider - port map (CLK_IN => buff_CLK, CLK_OUT => my_CLK); -- Le processeur, augmentation de la taille de la mémoire d'instruction diff --git a/Processeur.xpr b/Processeur.xpr index 9369af6..99d1f62 100644 --- a/Processeur.xpr +++ b/Processeur.xpr @@ -32,7 +32,7 @@