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Travail en cours, bug adresse tick d'avant

Paul Faure 3 years ago
parent
402e684461
commit
1442985687
5 changed files with 222 additions and 82 deletions
Split View Show Diff Stats
  1. 56
    26
      Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
  2. 42
    53
      Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
  3. 13
    1
      Processeur.srcs/sources_1/new/MemoireDonnees.vhd
  4. 8
    2
      Processeur.xpr
  5. 103
    0
      SimulationsConfig/Test_Etage4_Memoire_behav.wcfg

+ 56
- 26
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd View File 

@@ -37,34 +37,59 @@ end Test_Etage4_Memoire;
37 37
38 38 
 architecture Behavioral of Test_Etage4_Memoire is
39 39 
     component Etage4_Memoire is
40 
-    Generic ( Nb_bits : Natural;
41 
-              Mem_size : Natural;
42 
-              Instruction_bus_size : Natural;
43 
-              Bits_Controle_LC : STD_LOGIC_VECTOR;
44 
-              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
45 
-              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR);
46 
-        Port ( CLK : in STD_LOGIC;
47 
-               RST : in STD_LOGIC;
48 
-               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
49 
-               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50 
-               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
51 
-               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
52 
-               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
53 
-               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
40 
+        Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
41 
+                  Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
42 
+                  Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
43 
+                  Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
44 
+                  Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
45 
+                  Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
46 
+                  Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
47 
+                  Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
48 
+                  Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
49 
+                  Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
50 
+        Port ( CLK : in STD_LOGIC; -- Clock
51 
+               RST : in STD_LOGIC; -- Reset
52 
+               IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
53 
+               IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
54 
+               IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
55 
+               OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
56 
+               OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
57 
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
58 
+               OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
54 59 
     end component;
55 60
56 61 
     signal my_CLK : STD_LOGIC := '0';
57 62 
     signal my_RST : STD_LOGIC := '1';
58 63 
     signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
59 64 
     signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
60 
-    signal my_IN_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
65 
+    signal my_IN_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
61 66 
     signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
62 67 
     signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
63 
-    signal my_OUT_Instruction : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
68 
+    signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
69 
+    signal my_OUT_AddrRetour : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
64 70
65 
-    constant Bits_Controle_LC : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
66 
-    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (7 downto 0) := "10111111";
67 
-    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
71 
+    constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
72 
+    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1101111110101111111111";
73 
+    constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1001111011001111111111";
74 
+    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
75 
+    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
76 
+    constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
77 
+
78 
+    constant CNULL : STD_LOGIC_VECTOR (4 downto 0) := "00000";
79 
+    constant CWR : STD_LOGIC_VECTOR (4 downto 0) := "01011";
80 
+    constant CCALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
81 
+    constant CRET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
82 
+    constant C0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
83 
+    constant C1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
84 
+    constant C2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
85 
+    constant C3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
86 
+    constant C5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
87 
+    constant C7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
88 
+    constant C12 : STD_LOGIC_VECTOR (7 downto 0) := "00001100";
89 
+    constant C36 : STD_LOGIC_VECTOR (7 downto 0) := "00100100";
90 
+    constant C54 : STD_LOGIC_VECTOR (7 downto 0) := "00110110";
91 
+    constant C77 : STD_LOGIC_VECTOR (7 downto 0) := "01001101";
92 
+    constant C100 : STD_LOGIC_VECTOR (7 downto 0) := "01100100";
68 93
69 94 
     constant CLK_period : time := 10 ns;
70 95 
     
@@ -72,11 +97,15 @@ begin
72 97
73 98 
     instance : Etage4_Memoire
74 99 
     generic map( Nb_bits => 8,
75 
-                 Mem_size => 256,
76 
-                 Instruction_bus_size => 3,
100 
+                 Mem_size => 16,
101 
+                 Adresse_mem_size => 4,
102 
+                 Instruction_bus_size => 5,
77 103 
                  Bits_Controle_LC => Bits_Controle_LC,
78 104 
                  Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
79 
-                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT)
105 
+                 Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
106 
+                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT,
107 
+                 Code_Instruction_CALL => Code_Instruction_CALL,
108 
+                 Code_Instruction_RET => Code_Instruction_RET)
80 109 
     port map(    CLK => my_CLK,
81 110 
                  RST => my_RST,
82 111 
                  IN_A => my_IN_A,
 
@@ -84,7 +113,8 @@ begin
84 113 
                  IN_Instruction => my_IN_Instruction,
85 114 
                  OUT_A => my_OUT_A,
86 115 
                  OUT_B => my_OUT_B,
87 
-                 OUT_Instruction => my_OUT_Instruction);
116 
+                 OUT_Instruction => my_OUT_Instruction,
117 
+                 OUT_AddrRetour => my_OUT_AddrRetour);
88 118
89 119 
     CLK_process :process
90 120 
     begin
 
@@ -96,9 +126,9 @@ begin
96 126
97 127 
     process
98 128 
     begin
99 
-        my_IN_A <= "01011111" after 0 ns, "11111111" after 124 ns;
100 
-        my_IN_B <= "10100110" after 0 ns, "01011111" after 124 ns;
101 
-        my_IN_Instruction <= "000" after 0 ns, "001" after 10 ns, "010" after 20 ns, "011" after 30 ns, "100" after 40 ns, "101" after 50 ns, "110" after 60 ns, "111" after 70 ns, "000" after 80 ns, "110" after 100 ns, "111" after 110 ns, "110" after 120 ns;
129 
+        my_IN_A <= C0 after 0 ns, C0  after 5 ns, C1 after 15 ns, C2 after 25 ns, C77 after 35 ns, C0  after 45 ns, C54 after 55 ns, C0   after 65 ns, C0 after 75 ns;
130 
+        my_IN_B <= C0 after 0 ns, C36 after 5 ns, C5 after 15 ns, C7 after 25 ns, C3  after 35 ns, C12 after 45 ns, C1  after 55 ns, C100 after 65 ns, C0 after 75 ns;
131 
+        my_IN_Instruction <= CNULL after 0 ns, CWR after 5 ns, CWR after 15 ns, CWR after 25 ns, CCALL  after 35 ns, CWR after 45 ns, CCALL after 55 ns, CWR after 65 ns, CRET after 75 ns, CRET after 85 ns, CNULL after 95 ns;
102 132 
         my_RST <= '0' after 125 ns;
103 133 
         wait;
104 134 
     end process;

+ 42
- 53
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File 

@@ -29,8 +29,6 @@ entity Etage4_Memoire is
29 29 
               Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
30 30 
               Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
31 31 
               Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
32 
-              Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
33 
-              Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
34 32 
               Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
35 33 
               Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
36 34 
               Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
 
@@ -44,7 +42,8 @@ entity Etage4_Memoire is
44 42 
            IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
45 43 
            OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
46 44 
            OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
47 
-           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
45 
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
46 
+           OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
48 47 
 end Etage4_Memoire;
49 48
50 49 
 architecture Structural of Etage4_Memoire is
 
@@ -52,26 +51,18 @@ architecture Structural of Etage4_Memoire is
52 51 
     Generic (Nb_bits : Natural;
53 52 
              Addr_size : Natural;
54 53 
              Mem_size : Natural);
55 
-    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
56 
-           RW : in STD_LOGIC;
57 
-           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
58 
-           RST : in STD_LOGIC;
59 
-           CLK : in STD_LOGIC;
60 
-           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
61 
-    end component;
62 
-
63 
-    component MemoireAdressesRetour is
64 
-        Generic (Nb_bits : Natural;
65 
-                 Addr_size : Natural;
66 
-                 Mem_size : Natural);
67 
-        Port ( R : in STD_LOGIC;
68 
-               W : in STD_LOGIC;
69 
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
70 
-               RST : in STD_LOGIC;
71 
-               CLK : in STD_LOGIC;
72 
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
73 
-               E : out STD_LOGIC;
74 
-               F : out STD_LOGIC);
54 
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
55 
+           RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
56 
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
57 
+           CALL : in STD_LOGIC; -- '1' -> CALL en cours
58 
+           IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
59 
+           IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
60 
+           RET : in STD_LOGIC; -- '1' -> RET en cours
61 
+           OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
62 
+           OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
63 
+           RST : in STD_LOGIC; -- Reset
64 
+           CLK : in STD_LOGIC; -- Clock
65 
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
75 66 
     end component;
76 67
77 68 
     component LC is
 
@@ -94,7 +85,9 @@ architecture Structural of Etage4_Memoire is
94 85
95 86
96 87 
     signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse)
88 
+    signal Last_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Ancien EBP, valeur récupérée en mémoire lors d'un RET
97 89 
     signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd)
90 
+    signal IN_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- EBP à stocker ne mémoire (ajout de 0)
98 91
99 92 
     signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees
100 93 
     signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B
 
@@ -106,11 +99,9 @@ architecture Structural of Etage4_Memoire is
106 99
107 100 
     signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne
108 101
109 
-    -- Signaux de la memoire de contexte
110 
-    signal R_Aux : STD_LOGIC := '0';
111 
-    signal W_Aux : STD_LOGIC := '0';
112 
-    signal E : STD_LOGIC;
113 
-    signal F : STD_LOGIC;
102 
+    -- Signaux de contrôle de la mémoire
103 
+    signal CALL_Aux : STD_LOGIC := '0';
104 
+    signal RET_Aux : STD_LOGIC := '0';
114 105
115 106
116 107 
 begin
 
@@ -152,27 +143,18 @@ begin
152 143 
     generic map (Nb_bits => Nb_bits,
153 144 
                  Addr_size => Adresse_mem_size,
154 145 
                  Mem_size => Mem_size)
155 
-    port map ( Addr => Addr_MemoireDonnees,
156 
-               RW => Commande_MemoireDonnees(0),
157 
-               D_IN => IN_B,
158 
-               RST => RST,
159 
-               CLK => CLK,
160 
-               D_OUT => Sortie_MemoireDonnees);
161 
-
162 
-    instance_MemoireEBP : MemoireAdressesRetour
163 
-    generic map (Nb_bits => Adresse_mem_size,
164 
-                 Addr_size => Adresse_size_mem_EBP,
165 
-                 Mem_size => Mem_EBP_size
166 
-    )
167 
-    port map ( R => R_Aux,
168 
-               W => W_Aux,
169 
-               D_IN => New_EBP,
170 
-               RST => RST,
171 
-               CLK => CLK,
172 
-               D_OUT => EBP,
173 
-               E => E,
174 
-               F => F
175 
-    );
146 
+    port map (Addr => Addr_MemoireDonnees,
147 
+              RW => Commande_MemoireDonnees(0),
148 
+              D_IN => IN_B,
149 
+              CALL => CALL_Aux,
150 
+              IN_EBP => IN_EBP,
151 
+              IN_AddrRet => IN_A,
152 
+              RET => RET_Aux,
153 
+              OUT_EBP => Last_EBP,
154 
+              OUT_AddrRet => OUT_AddrRetour,
155 
+              RST => RST,
156 
+              CLK => CLK,
157 
+              D_OUT => Sortie_MemoireDonnees);
176 158
177 159 
     OUT_A <= (others => '0') when RST = '0' else
178 160 
              IN_A;
 
@@ -181,12 +163,19 @@ begin
181 163 
     OUT_Instruction <= (others => '0') when RST = '0' else
182 164 
              IN_Instruction;
183 165
184 
-    -- Controle de la mémoire de contexte (ici aussi un LC aurait été disproportionné)
185 
-    R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
166 
+    -- Controle de la gestion des appels de fonctions (ici aussi un LC aurait été disproportionné)
167 
+    RET_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
186 168 
              '0';
187 
-    W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
169 
+    CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
188 170 
              '0';
189 171
172 
+    New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
173 
+    EBP <= New_EBP when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_CALL else
174 
+           Last_EBP (Adresse_mem_size - 1 downto 0) when CLK'event and CLK='1' and IN_Instruction = Code_Instruction_RET else
175 
+           (others => '0') when RST = '0' else
176 
+           EBP;
177 
+    IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
178 
+
190 179 
     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
191 
-    New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
180 
+
192 181 
 end Structural;

+ 13
- 1
Processeur.srcs/sources_1/new/MemoireDonnees.vhd View File 

@@ -23,6 +23,12 @@ entity MemoireDonnees is
23 23 
     Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
24 24 
            RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
25 25 
            D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
26 
+           CALL : in STD_LOGIC; -- '1' -> CALL en cours
27 
+           IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
28 
+           IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
29 
+           RET : in STD_LOGIC; -- '1' -> RET en cours
30 
+           OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
31 
+           OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
26 32 
            RST : in STD_LOGIC; -- Reset
27 33 
            CLK : in STD_LOGIC; -- Clock
28 34 
            D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire 
@@ -37,7 +43,13 @@ begin
37 43 
         if (RST = '0') then
38 44 
             MEMORY <= (others => '0');
39 45 
         else
40 
-            if (RW = '0') then
46 
+            if (CALL = '1') then
47 
+                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
48 
+                MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
49 
+            elsif (RET = '1') then
50 
+                OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2));
51 
+                OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1));
52 
+            elsif (RW = '0') then
41 53 
                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
42 54 
             end if;
43 55 
         end if;

+ 8
- 2
Processeur.xpr View File 

@@ -32,7 +32,7 @@
32 32 
     <Option Name="EnableBDX" Val="FALSE"/>
33 33 
     <Option Name="DSABoardId" Val="basys3"/>
34 34 
     <Option Name="DSANumComputeUnits" Val="16"/>
35 
-    <Option Name="WTXSimLaunchSim" Val="235"/>
35 
+    <Option Name="WTXSimLaunchSim" Val="287"/>
36 36 
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37 
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38 
     <Option Name="WTIesLaunchSim" Val="0"/>
 
@@ -233,9 +233,14 @@
233 233 
           <Attr Name="UsedIn" Val="simulation"/>
234 234 
         </FileInfo>
235 235 
       </File>
236 
+      <File Path="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg">
237 
+        <FileInfo>
238 
+          <Attr Name="UsedIn" Val="simulation"/>
239 
+        </FileInfo>
240 
+      </File>
236 241 
       <Config>
237 242 
         <Option Name="DesignMode" Val="RTL"/>
238 
-        <Option Name="TopModule" Val="Test_Pipeline"/>
243 
+        <Option Name="TopModule" Val="Test_Etage4_Memoire"/>
239 244 
         <Option Name="TopLib" Val="xil_defaultlib"/>
240 245 
         <Option Name="TransportPathDelay" Val="0"/>
241 246 
         <Option Name="TransportIntDelay" Val="0"/>
 
@@ -243,6 +248,7 @@
243 248 
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg"/>
244 249 
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
245 250 
         <Option Name="XSimWcfgFile" Val="$PSIMDIR/sim_1/behav/Test_Pipeline_behav.wcfg"/>
251 
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/SimulationsConfig/Test_Etage4_Memoire_behav.wcfg"/>
246 252 
       </Config>
247 253 
     </FileSet>
248 254 
   </FileSets>

+ 103
- 0
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg View File 

@@ -0,0 +1,103 @@
1 
+<?xml version="1.0" encoding="UTF-8"?>
2 
+<wave_config>
3 
+   <wave_state>
4 
+   </wave_state>
5 
+   <db_ref_list>
6 
+      <db_ref path="Test_Etage4_Memoire_behav.wdb" id="1">
7 
+         <top_modules>
8 
+            <top_module name="Test_Etage4_Memoire" />
9 
+         </top_modules>
10 
+      </db_ref>
11 
+   </db_ref_list>
12 
+   <zoom_setting>
13 
+      <ZoomStartTime time="0fs"></ZoomStartTime>
14 
+      <ZoomEndTime time="79200001fs"></ZoomEndTime>
15 
+      <Cursor1Time time="50600000fs"></Cursor1Time>
16 
+   </zoom_setting>
17 
+   <column_width_setting>
18 
+      <NameColumnWidth column_width="146"></NameColumnWidth>
19 
+      <ValueColumnWidth column_width="327"></ValueColumnWidth>
20 
+   </column_width_setting>
21 
+   <WVObjectSize size="18" />
22 
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_CLK">
23 
+      <obj_property name="ElementShortName">my_CLK</obj_property>
24 
+      <obj_property name="ObjectShortName">my_CLK</obj_property>
25 
+   </wvobject>
26 
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/my_RST">
27 
+      <obj_property name="ElementShortName">my_RST</obj_property>
28 
+      <obj_property name="ObjectShortName">my_RST</obj_property>
29 
+   </wvobject>
30 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_A">
31 
+      <obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
32 
+      <obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
33 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
34 
+   </wvobject>
35 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
36 
+      <obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
37 
+      <obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
38 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
39 
+   </wvobject>
40 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_Instruction">
41 
+      <obj_property name="ElementShortName">my_IN_Instruction[4:0]</obj_property>
42 
+      <obj_property name="ObjectShortName">my_IN_Instruction[4:0]</obj_property>
43 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
44 
+   </wvobject>
45 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_A">
46 
+      <obj_property name="ElementShortName">my_OUT_A[7:0]</obj_property>
47 
+      <obj_property name="ObjectShortName">my_OUT_A[7:0]</obj_property>
48 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
49 
+   </wvobject>
50 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_B">
51 
+      <obj_property name="ElementShortName">my_OUT_B[7:0]</obj_property>
52 
+      <obj_property name="ObjectShortName">my_OUT_B[7:0]</obj_property>
53 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
54 
+   </wvobject>
55 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_Instruction">
56 
+      <obj_property name="ElementShortName">my_OUT_Instruction[4:0]</obj_property>
57 
+      <obj_property name="ObjectShortName">my_OUT_Instruction[4:0]</obj_property>
58 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
59 
+   </wvobject>
60 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_AddrRetour">
61 
+      <obj_property name="ElementShortName">my_OUT_AddrRetour[7:0]</obj_property>
62 
+      <obj_property name="ObjectShortName">my_OUT_AddrRetour[7:0]</obj_property>
63 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
64 
+   </wvobject>
65 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/EBP">
66 
+      <obj_property name="ElementShortName">EBP[3:0]</obj_property>
67 
+      <obj_property name="ObjectShortName">EBP[3:0]</obj_property>
68 
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
69 
+   </wvobject>
70 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Last_EBP">
71 
+      <obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
72 
+      <obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
73 
+   </wvobject>
74 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/OUT_EBP">
75 
+      <obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
76 
+      <obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
77 
+   </wvobject>
78 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
79 
+      <obj_property name="ElementShortName">MEMORY[127:0]</obj_property>
80 
+      <obj_property name="ObjectShortName">MEMORY[127:0]</obj_property>
81 
+      <obj_property name="Radix">HEXRADIX</obj_property>
82 
+   </wvobject>
83 
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
84 
+      <obj_property name="ElementShortName">RW</obj_property>
85 
+      <obj_property name="ObjectShortName">RW</obj_property>
86 
+   </wvobject>
87 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
88 
+      <obj_property name="ElementShortName">Addr[3:0]</obj_property>
89 
+      <obj_property name="ObjectShortName">Addr[3:0]</obj_property>
90 
+   </wvobject>
91 
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
92 
+      <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
93 
+      <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
94 
+   </wvobject>
95 
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/CALL">
96 
+      <obj_property name="ElementShortName">CALL</obj_property>
97 
+      <obj_property name="ObjectShortName">CALL</obj_property>
98 
+   </wvobject>
99 
+   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RET">
100 
+      <obj_property name="ElementShortName">RET</obj_property>
101 
+      <obj_property name="ObjectShortName">RET</obj_property>
102 
+   </wvobject>
103 
+</wave_config>

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