Browse Source

Suppression fichiers inutiles

Paul Faure 4 months ago
parent
commit
4f64f6664a
96 changed files with 7 additions and 10690 deletions
  1. 7
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      .gitignore
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      Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
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      Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd
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      Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd
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      Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
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      Compteur8BitsBasys3.xpr
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      proj/GPIO.cache/wt/gui_resources.wdf
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      proj/GPIO.cache/wt/synthesis.wdf
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      proj/GPIO.cache/wt/webtalk_pa.xml
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      proj/GPIO.hw/GPIO.lpr
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      proj/GPIO.hw/hw_1/hw.xml
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      proj/GPIO.runs/.jobs/vrs_config_1.xml
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      proj/GPIO.runs/impl_1/.vivado.begin.rst
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      proj/GPIO.runs/impl_1/.write_bitstream.begin.rst
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      proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt
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      proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt
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      proj/GPIO.runs/impl_1/GPIO_demo_power_summary_routed.pb
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      proj/GPIO.runs/impl_1/gen_run.xml
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      proj/GPIO.runs/impl_1/htr.txt
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      proj/GPIO.runs/impl_1/init_design.pb
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      proj/GPIO.runs/impl_1/opt_design.pb
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      proj/GPIO.runs/impl_1/vivado.jou
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      proj/GPIO.runs/synth_1/.Vivado_Synthesis.queue.rst
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      proj/GPIO.runs/synth_1/.Xil/GPIO_demo_propImpl.xdc
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      proj/GPIO.runs/synth_1/ISEWrap.js
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      proj/GPIO.runs/synth_1/gen_run.xml
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      proj/GPIO.runs/synth_1/htr.txt
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+ 7
- 5
.gitignore View File

@@ -1,5 +1,7 @@
1
-Compteur8BitsBasys3.ip_user_files/*
2
-Compteur8BitsBasys3.cache/*
3
-Compteur8BitsBasys3.hw/*
4
-Compteur8BitsBasys3.runs/*
5
-Compteur8BitsBasys3.sim/*
1
+Processeur.ip_user_files/*
2
+Processeur.cache/*
3
+Processeur.hw/*
4
+Processeur.runs/*
5
+Processeur.sim/*
6
+vivado*
7
+.Xil

+ 0
- 299
Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -1,299 +0,0 @@
1
-## This file is a general .xdc for the Basys3 rev B board
2
-## To use it in a project:
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-## - uncomment the lines corresponding to used pins
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-## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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-
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-## Clock signal
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-set_property PACKAGE_PIN W5 [get_ports CLK]
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-set_property IOSTANDARD LVCMOS33 [get_ports CLK]
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-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
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-
11
-## Switches
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-set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
13
-set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
14
-set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
15
-set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
16
-set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
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-set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
19
-set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
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-set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
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-set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
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-set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
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-set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
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-#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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-#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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-#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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-#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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-#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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-#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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-#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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-#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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-
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-
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-## LEDs
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-set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
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-set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
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-set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
52
-set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
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-set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
54
-set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
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-set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
56
-set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
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-set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
59
-set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
60
-set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
61
-set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
63
-#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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-#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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-#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69
-#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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-#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
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-#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
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-#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
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-#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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-
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-
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-##7 segment display
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-#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
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-#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
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-#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
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-#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
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-#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
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-#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
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-#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
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-
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-#set_property PACKAGE_PIN V7 [get_ports dp]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
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-
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-#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
101
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
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-#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
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-#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
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-#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
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-
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-
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-##Buttons
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-set_property PACKAGE_PIN U18 [get_ports btnC]
112
-set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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-#set_property PACKAGE_PIN T18 [get_ports btnU]
114
-#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115
-set_property PACKAGE_PIN W19 [get_ports btnL]
116
-set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
-set_property PACKAGE_PIN T17 [get_ports btnR]
118
-set_property IOSTANDARD LVCMOS33 [get_ports btnR]
119
-set_property PACKAGE_PIN U17 [get_ports btnD]
120
-set_property IOSTANDARD LVCMOS33 [get_ports btnD]
121
-
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-
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-
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-##Pmod Header JA
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-##Sch name = JA1
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-#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
127
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
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-##Sch name = JA2
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-#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
130
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
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-##Sch name = JA3
132
-#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
133
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
134
-##Sch name = JA4
135
-#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
136
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
137
-##Sch name = JA7
138
-#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
139
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
140
-##Sch name = JA8
141
-#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
142
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
143
-##Sch name = JA9
144
-#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
145
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
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-##Sch name = JA10
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-#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
148
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
149
-
150
-
151
-
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-##Pmod Header JB
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-##Sch name = JB1
154
-#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
155
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
156
-##Sch name = JB2
157
-#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
158
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
159
-##Sch name = JB3
160
-#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
161
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
162
-##Sch name = JB4
163
-#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
164
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
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-##Sch name = JB7
166
-#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
167
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
168
-##Sch name = JB8
169
-#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
170
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
171
-##Sch name = JB9
172
-#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
173
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
174
-##Sch name = JB10
175
-#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
176
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
177
-
178
-
179
-
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-##Pmod Header JC
181
-##Sch name = JC1
182
-#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
183
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
184
-##Sch name = JC2
185
-#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
186
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
187
-##Sch name = JC3
188
-#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
189
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
190
-##Sch name = JC4
191
-#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
192
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
193
-##Sch name = JC7
194
-#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
195
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
196
-##Sch name = JC8
197
-#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
198
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
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-##Sch name = JC9
200
-#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
201
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
202
-##Sch name = JC10
203
-#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
204
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
205
-
206
-
207
-##Pmod Header JXADC
208
-##Sch name = XA1_P
209
-#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
210
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
211
-##Sch name = XA2_P
212
-#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
213
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
214
-##Sch name = XA3_P
215
-#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
216
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
217
-##Sch name = XA4_P
218
-#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
219
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
220
-##Sch name = XA1_N
221
-#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
222
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
223
-##Sch name = XA2_N
224
-#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
225
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
226
-##Sch name = XA3_N
227
-#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
228
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
229
-##Sch name = XA4_N
230
-#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
231
-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
232
-
233
-
234
-
235
-##VGA Connector
236
-#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
237
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
238
-#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
239
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
240
-#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
241
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
242
-#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
243
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
244
-#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
245
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
246
-#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
247
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
248
-#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
249
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
250
-#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
251
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
252
-#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
253
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
254
-#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
255
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
256
-#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
257
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
258
-#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
259
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
260
-#set_property PACKAGE_PIN P19 [get_ports Hsync]
261
-	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
262
-#set_property PACKAGE_PIN R19 [get_ports Vsync]
263
-	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
264
-
265
-
266
-##USB-RS232 Interface
267
-#set_property PACKAGE_PIN B18 [get_ports RsRx]
268
-	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
269
-#set_property PACKAGE_PIN A18 [get_ports RsTx]
270
-	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
271
-
272
-
273
-##USB HID (PS/2)
274
-#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
275
-	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
276
-	#set_property PULLUP true [get_ports PS2Clk]
277
-#set_property PACKAGE_PIN B17 [get_ports PS2Data]
278
-	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
279
-	#set_property PULLUP true [get_ports PS2Data]
280
-
281
-
282
-##Quad SPI Flash
283
-##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
284
-##STARTUPE2 primitive.
285
-#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
286
-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
287
-#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
288
-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
289
-#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
290
-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
291
-#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
292
-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
293
-#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
294
-	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
295
-
296
-
297
-## Configuration options, can be used for all designs
298
-set_property CONFIG_VOLTAGE 3.3 [current_design]
299
-set_property CFGBVS VCCO [current_design]

+ 0
- 33
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd View File

@@ -1,54 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-
8
---use IEEE.NUMERIC_STD.ALL;
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity ClockDivider10 is
14
-    Port ( clk_in : in STD_LOGIC;
15
-           clk_out : out STD_LOGIC);
16
-end ClockDivider10;
17
-
18
-architecture Behavioral of ClockDivider10 is
19
-    subtype int10 is INTEGER range 0 to 10;
20
-    signal N : int10 := 0;
21
-    signal aux : STD_LOGIC;
22
-begin
23
-    process
24
-    begin
25
-        wait until clk_in'event and clk_in = '1';
26
-        N <= N + 1;
27
-        if N = 10 then
28
-            aux <= not aux;
29
-            N <= 0;
30
-        end if;
31
-    end process;
32
-    clk_out <= aux;
33
-end Behavioral;

+ 0
- 29
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd View File

@@ -1,50 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-
8
---use IEEE.NUMERIC_STD.ALL;
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity ClockDivider1000 is
14
-    Port ( clk_in : in STD_LOGIC;
15
-           clk_out : out STD_LOGIC);
16
-end ClockDivider1000;
17
-
18
-architecture Structural of ClockDivider1000 is
19
-    component ClockDivider10
20
-        Port ( clk_in : in STD_LOGIC;
21
-               clk_out : out STD_LOGIC);
22
-    end component;
23
-    
24
-    signal aux1, aux2 : STD_LOGIC;
25
-begin
26
-    U1: ClockDivider10 port map(clk_in, aux1);
27
-    U2: ClockDivider10 port map(aux1, aux2);
28
-    U3: ClockDivider10 port map(aux2, clk_out);
29
-end Structural;

+ 0
- 42
Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd View File

@@ -1,64 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
8
-
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity Compteur is
14
-    Port ( CK : in STD_LOGIC;
15
-           RST : in STD_LOGIC;
16
-           SENS : in STD_LOGIC;
17
-           LOAD : in STD_LOGIC;
18
-           EN : in STD_LOGIC;
19
-           Din : in STD_LOGIC_VECTOR (7 downto 0);
20
-           Dout : out STD_LOGIC_VECTOR (7 downto 0));
21
-end Compteur;
22
-
23
-architecture Behavioral of Compteur is
24
-    signal aux: STD_LOGIC_VECTOR (7 downto 0);
25
-begin
26
-    Dout <= aux;
27
-    process
28
-    begin
29
-        wait until CK'event and CK='1';
30
-        if RST = '0' then
31
-            aux <= (others => '0');
32
-        elsif LOAD = '1' then
33
-            aux <= Din;
34
-        elsif EN = '0' then
35
-            if SENS = '1' then
36
-                aux <= aux + 1;
37
-            else 
38
-                aux <= aux - 1;
39
-            end if;
40
-        end if;
41
-    end process;
42
-end Behavioral;

+ 0
- 45
Compteur8BitsBasys3.srcs/sources_1/new/System.vhd View File

@@ -1,66 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-
8
---use IEEE.NUMERIC_STD.ALL;
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity System is
14
-    Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
15
-           btnL : in STD_LOGIC;
16
-           btnC : in STD_LOGIC;
17
-           btnR : in STD_LOGIC;
18
-           btnD : in STD_LOGIC;
19
-           LED : out STD_LOGIC_VECTOR (0 to 7);
20
-           CLK : in STD_LOGIC);
21
-end System;
22
-
23
-architecture Structural of System is
24
-
25
-    component ClockDivider1000
26
-        Port ( clk_in : in STD_LOGIC;
27
-               clk_out : out STD_LOGIC);
28
-    end component;
29
-    
30
-    component Compteur
31
-        Port ( CK : in STD_LOGIC;
32
-               RST : in STD_LOGIC;
33
-               SENS : in STD_LOGIC;
34
-               LOAD : in STD_LOGIC;
35
-               EN : in STD_LOGIC;
36
-               Din : in STD_LOGIC_VECTOR (7 downto 0);
37
-               Dout : out STD_LOGIC_VECTOR (7 downto 0));
38
-    end component;
39
-    
40
-    signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
41
-begin
42
-    DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
43
-    DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
44
-    CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
45
-end Structural;

+ 0
- 159
Compteur8BitsBasys3.xpr View File

@@ -1,159 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)              -->
3
-<!--                                                         -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
5
-
6
-<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr">
7
-  <DefaultLaunch Dir="$PRUNDIR"/>
8
-  <Configuration>
9
-    <Option Name="Id" Val="b3843060a8224f8699d89033689dec00"/>
10
-    <Option Name="Part" Val="xc7a35tcpg236-1"/>
11
-    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
12
-    <Option Name="CompiledLibDirXSim" Val=""/>
13
-    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
14
-    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
15
-    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
16
-    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
17
-    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
18
-    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
19
-    <Option Name="TargetLanguage" Val="VHDL"/>
20
-    <Option Name="SimulatorLanguage" Val="VHDL"/>
21
-    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
22
-    <Option Name="ActiveSimSet" Val="sim_1"/>
23
-    <Option Name="DefaultLib" Val="xil_defaultlib"/>
24
-    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
25
-    <Option Name="IPCachePermission" Val="read"/>
26
-    <Option Name="IPCachePermission" Val="write"/>
27
-    <Option Name="EnableCoreContainer" Val="FALSE"/>
28
-    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
29
-    <Option Name="IPUserFilesDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files"/>
30
-    <Option Name="IPStaticSourceDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files/ipstatic"/>
31
-    <Option Name="EnableBDX" Val="FALSE"/>
32
-    <Option Name="DSABoardId" Val="basys3"/>
33
-    <Option Name="DSANumComputeUnits" Val="16"/>
34
-    <Option Name="WTXSimLaunchSim" Val="0"/>
35
-    <Option Name="WTModelSimLaunchSim" Val="0"/>
36
-    <Option Name="WTQuestaLaunchSim" Val="0"/>
37
-    <Option Name="WTIesLaunchSim" Val="0"/>
38
-    <Option Name="WTVcsLaunchSim" Val="0"/>
39
-    <Option Name="WTRivieraLaunchSim" Val="0"/>
40
-    <Option Name="WTActivehdlLaunchSim" Val="0"/>
41
-    <Option Name="WTXSimExportSim" Val="0"/>
42
-    <Option Name="WTModelSimExportSim" Val="0"/>
43
-    <Option Name="WTQuestaExportSim" Val="0"/>
44
-    <Option Name="WTIesExportSim" Val="0"/>
45
-    <Option Name="WTVcsExportSim" Val="0"/>
46
-    <Option Name="WTRivieraExportSim" Val="0"/>
47
-    <Option Name="WTActivehdlExportSim" Val="0"/>
48
-    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
49
-    <Option Name="XSimRadix" Val="hex"/>
50
-    <Option Name="XSimTimeUnit" Val="ns"/>
51
-    <Option Name="XSimArrayDisplayLimit" Val="64"/>
52
-    <Option Name="XSimTraceLimit" Val="65536"/>
53
-  </Configuration>
54
-  <FileSets Version="1" Minor="31">
55
-    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
56
-      <Filter Type="Srcs"/>
57
-      <File Path="$PSRCDIR/sources_1/new/ClockDivider10.vhd">
58
-        <FileInfo>
59
-          <Attr Name="UsedIn" Val="synthesis"/>
60
-          <Attr Name="UsedIn" Val="simulation"/>
61
-        </FileInfo>
62
-      </File>
63
-      <File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
64
-        <FileInfo>
65
-          <Attr Name="UsedIn" Val="synthesis"/>
66
-          <Attr Name="UsedIn" Val="simulation"/>
67
-        </FileInfo>
68
-      </File>
69
-      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
70
-        <FileInfo>
71
-          <Attr Name="UsedIn" Val="synthesis"/>
72
-          <Attr Name="UsedIn" Val="simulation"/>
73
-        </FileInfo>
74
-      </File>
75
-      <File Path="$PSRCDIR/sources_1/new/System.vhd">
76
-        <FileInfo>
77
-          <Attr Name="UsedIn" Val="synthesis"/>
78
-          <Attr Name="UsedIn" Val="simulation"/>
79
-        </FileInfo>
80
-      </File>
81
-      <Config>
82
-        <Option Name="DesignMode" Val="RTL"/>
83
-        <Option Name="TopModule" Val="System"/>
84
-        <Option Name="TopAutoSet" Val="TRUE"/>
85
-      </Config>
86
-    </FileSet>
87
-    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
88
-      <Filter Type="Constrs"/>
89
-      <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
90
-        <FileInfo>
91
-          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
92
-          <Attr Name="ImportTime" Val="1614979917"/>
93
-          <Attr Name="UsedIn" Val="synthesis"/>
94
-          <Attr Name="UsedIn" Val="implementation"/>
95
-        </FileInfo>
96
-      </File>
97
-      <Config>
98
-        <Option Name="ConstrsType" Val="XDC"/>
99
-      </Config>
100
-    </FileSet>
101
-    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
102
-      <Filter Type="Srcs"/>
103
-      <Config>
104
-        <Option Name="DesignMode" Val="RTL"/>
105
-        <Option Name="TopModule" Val="System"/>
106
-        <Option Name="TopLib" Val="xil_defaultlib"/>
107
-        <Option Name="TopAutoSet" Val="TRUE"/>
108
-        <Option Name="TransportPathDelay" Val="0"/>
109
-        <Option Name="TransportIntDelay" Val="0"/>
110
-        <Option Name="SimMode" Val="post-implementation"/>
111
-        <Option Name="SrcSet" Val="sources_1"/>
112
-      </Config>
113
-    </FileSet>
114
-  </FileSets>
115
-  <Simulators>
116
-    <Simulator Name="XSim">
117
-      <Option Name="Description" Val="Vivado Simulator"/>
118
-      <Option Name="CompiledLib" Val="0"/>
119
-    </Simulator>
120
-    <Simulator Name="ModelSim">
121
-      <Option Name="Description" Val="ModelSim Simulator"/>
122
-    </Simulator>
123
-    <Simulator Name="Questa">
124
-      <Option Name="Description" Val="Questa Advanced Simulator"/>
125
-    </Simulator>
126
-    <Simulator Name="Riviera">
127
-      <Option Name="Description" Val="Riviera-PRO Simulator"/>
128
-    </Simulator>
129
-    <Simulator Name="ActiveHDL">
130
-      <Option Name="Description" Val="Active-HDL Simulator"/>
131
-    </Simulator>
132
-  </Simulators>
133
-  <Runs Version="1" Minor="10">
134
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
135
-      <Strategy Version="1" Minor="2">
136
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
137
-        <Step Id="synth_design"/>
138
-      </Strategy>
139
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
140
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
141
-    </Run>
142
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
143
-      <Strategy Version="1" Minor="2">
144
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
145
-        <Step Id="init_design"/>
146
-        <Step Id="opt_design"/>
147
-        <Step Id="power_opt_design"/>
148
-        <Step Id="place_design"/>
149
-        <Step Id="post_place_power_opt_design"/>
150
-        <Step Id="phys_opt_design"/>
151
-        <Step Id="route_design"/>
152
-        <Step Id="post_route_phys_opt_design"/>
153
-        <Step Id="write_bitstream"/>
154
-      </Strategy>
155
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
156
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
157
-    </Run>
158
-  </Runs>
159
-</Project>

+ 0
- 13
proj/GPIO.cache/wt/gui_resources.wdf View File

@@ -1,13 +0,0 @@
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proj/GPIO.cache/wt/synthesis_details.wdf View File

@@ -1,3 +0,0 @@
1
-version:1
2
-73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
3
-eof:2511430288

+ 0
- 48
proj/GPIO.cache/wt/webtalk_pa.xml View File

@@ -1,48 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8" ?>
2
-<document>
3
-<!--The data in this file is primarily intended for consumption by Xilinx tools.
4
-The structure and the elements are likely to change over the next few releases.
5
-This means code written to parse this file will need to be revisited each subsequent release.-->
6
-<application name="pa" timeStamp="Fri Apr 09 23:28:53 2021">
7
-<section name="Project Information" visible="false">
8
-<property name="ProjectID" value="f5d1f37f0c514482aeb99b8a58e27639" type="ProjectID"/>
9
-<property name="ProjectIteration" value="3" type="ProjectIteration"/>
10
-</section>
11
-<section name="PlanAhead Usage" visible="true">
12
-<item name="Project Data">
13
-<property name="SrcSetCount" value="1" type="SrcSetCount"/>
14
-<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
15
-<property name="DesignMode" value="RTL" type="DesignMode"/>
16
-<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
17
-<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
18
-</item>
19
-<item name="Java Command Handlers">
20
-<property name="AutoConnectTarget" value="1" type="JavaHandler"/>
21
-<property name="LaunchProgramFpga" value="1" type="JavaHandler"/>
22
-<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
23
-<property name="RunBitgen" value="1" type="JavaHandler"/>
24
-<property name="RunImplementation" value="1" type="JavaHandler"/>
25
-<property name="RunSynthesis" value="1" type="JavaHandler"/>
26
-<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
27
-</item>
28
-<item name="Gui Resources Info">
29
-<property name="BaseDialog_OK" value="6" type="GuiResourceData"/>
30
-<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiResourceData"/>
31
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiResourceData"/>
32
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="2" type="GuiResourceData"/>
33
-<property name="PACommandNames_AUTO_CONNECT_TARGET" value="1" type="GuiResourceData"/>
34
-<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiResourceData"/>
35
-<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiResourceData"/>
36
-<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiResourceData"/>
37
-<property name="ProgramDebugTab_PROGRAM_DEVICE" value="1" type="GuiResourceData"/>
38
-<property name="ProgramFpgaDialog_PROGRAM" value="1" type="GuiResourceData"/>
39
-<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiResourceData"/>
40
-</item>
41
-<item name="Other">
42
-<property name="GuiMode" value="4" type="GuiMode"/>
43
-<property name="BatchMode" value="0" type="BatchMode"/>
44
-<property name="TclMode" value="3" type="TclMode"/>
45
-</item>
46
-</section>
47
-</application>
48
-</document>

+ 0
- 8
proj/GPIO.hw/GPIO.lpr View File

@@ -1,8 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
3
-<!--                                                              -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
5
-
6
-<labtools version="1" minor="0">
7
-  <HWSession Dir="hw_1" File="hw.xml"/>
8
-</labtools>

+ 0
- 15
proj/GPIO.hw/hw_1/hw.xml View File

@@ -1,15 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
3
-<!--                                                              -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
5
-
6
-<hwsession version="1" minor="2">
7
-  <device name="xc7a35t_0" gui_info=""/>
8
-  <ObjectList object_type="hw_device" gui_info="">
9
-    <Object name="xc7a35t_0" gui_info="">
10
-      <Properties Property="PROBES.FILE" value=""/>
11
-      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name__demo.bit"/>
12
-    </Object>
13
-  </ObjectList>
14
-  <probeset name="hw project" active="false"/>
15
-</hwsession>

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_1.xml View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="synth_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
4
-</Runs>
5
-

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_2.xml View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
4
-</Runs>
5
-

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_3.xml View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
4
-</Runs>
5
-

+ 0
- 0
proj/GPIO.runs/impl_1/.Vivado_Implementation.queue.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.init_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.init_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.opt_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.opt_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.place_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.place_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.route_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.route_design.end.rst View File


+ 0
- 10
proj/GPIO.runs/impl_1/.vivado.begin.rst View File

@@ -1,10 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="2772">
4
-    </Process>
5
-</ProcessHandle>
6
-<?xml version="1.0"?>
7
-<ProcessHandle Version="1" Minor="0">
8
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="12740">
9
-    </Process>
10
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.vivado.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.write_bitstream.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="1988">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.write_bitstream.end.rst View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo.bit View File


+ 0
- 67
proj/GPIO.runs/impl_1/GPIO_demo.tcl View File

@@ -1,67 +0,0 @@
1
-proc start_step { step } {
2
-  set stopFile ".stop.rst"
3
-  if {[file isfile .stop.rst]} {
4
-    puts ""
5
-    puts "*** Halting run - EA reset detected ***"
6
-    puts ""
7
-    puts ""
8
-    return -code error
9
-  }
10
-  set beginFile ".$step.begin.rst"
11
-  set platform "$::tcl_platform(platform)"
12
-  set user "$::tcl_platform(user)"
13
-  set pid [pid]
14
-  set host ""
15
-  if { [string equal $platform unix] } {
16
-    if { [info exist ::env(HOSTNAME)] } {
17
-      set host $::env(HOSTNAME)
18
-    }
19
-  } else {
20
-    if { [info exist ::env(COMPUTERNAME)] } {
21
-      set host $::env(COMPUTERNAME)
22
-    }
23
-  }
24
-  set ch [open $beginFile w]
25
-  puts $ch "<?xml version=\"1.0\"?>"
26
-  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
27
-  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
28
-  puts $ch "    </Process>"
29
-  puts $ch "</ProcessHandle>"
30
-  close $ch
31
-}
32
-
33
-proc end_step { step } {
34
-  set endFile ".$step.end.rst"
35
-  set ch [open $endFile w]
36
-  close $ch
37
-}
38
-
39
-proc step_failed { step } {
40
-  set endFile ".$step.error.rst"
41
-  set ch [open $endFile w]
42
-  close $ch
43
-}
44
-
45
-set_msg_config -id {HDL 9-1061} -limit 100000
46
-set_msg_config -id {HDL 9-1654} -limit 100000
47
-
48
-start_step write_bitstream
49
-set ACTIVE_STEP write_bitstream
50
-set rc [catch {
51
-  create_msg_db write_bitstream.pb
52
-  open_checkpoint GPIO_demo_routed.dcp
53
-  set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
54
-  catch { write_mem_info -force GPIO_demo.mmi }
55
-  write_bitstream -force -no_partial_bitfile GPIO_demo.bit 
56
-  catch { write_sysdef -hwdef GPIO_demo.hwdef -bitfile GPIO_demo.bit -meminfo GPIO_demo.mmi -file GPIO_demo.sysdef }
57
-  catch {write_debug_probes -quiet -force debug_nets}
58
-  close_msg_db -file write_bitstream.pb
59
-} RESULT]
60
-if {$rc} {
61
-  step_failed write_bitstream
62
-  return -code error $RESULT
63
-} else {
64
-  end_step write_bitstream
65
-  unset ACTIVE_STEP 
66
-}
67
-

+ 0
- 475
proj/GPIO.runs/impl_1/GPIO_demo.vdi View File

@@ -1,475 +0,0 @@
1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Design is defaulting to srcset: sources_1
14
-Design is defaulting to constrset: constrs_1
15
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
16
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
17
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
18
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
19
-INFO: [Project 1-570] Preparing netlist for logic optimization
20
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
22
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
23
-INFO: [Project 1-111] Unisim Transformation Summary:
24
-  A total of 2 instances were transformed.
25
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
26
-
27
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
28
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
29
-Command: opt_design -directive RuntimeOptimized
30
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
31
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
32
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
33
-Running DRC as a precondition to command opt_design
34
-
35
-Starting DRC Task
36
-INFO: [DRC 23-27] Running DRC with 2 threads
37
-INFO: [Project 1-461] DRC finished with 0 Errors
38
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
39
-
40
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
41
-
42
-Starting Logic Optimization Task
43
-Implement Debug Cores | Checksum: 11fc7498c
44
-INFO: [Timing 38-35] Done setting XDC timing constraints.
45
-INFO: [Timing 38-2] Deriving generated clocks
46
-
47
-Phase 1 Retarget
48
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
49
-INFO: [Opt 31-49] Retargeted 0 cell(s).
50
-Phase 1 Retarget | Checksum: 16f269fca
51
-
52
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
53
-
54
-Phase 2 Constant propagation
55
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
56
-INFO: [Opt 31-10] Eliminated 6 cells.
57
-Phase 2 Constant propagation | Checksum: 233a26f9e
58
-
59
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
60
-
61
-Phase 3 Sweep
62
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
63
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
64
-Phase 3 Sweep | Checksum: 1bb596469
65
-
66
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
67
-
68
-Phase 4 BUFG optimization
69
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
70
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
71
-Phase 4 BUFG optimization | Checksum: 1bb596469
72
-
73
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
74
-
75
-Starting Connectivity Check Task
76
-
77
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
78
-Ending Logic Optimization Task | Checksum: 1bb596469
79
-
80
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
81
-INFO: [Common 17-83] Releasing license: Implementation
82
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
83
-opt_design completed successfully
84
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
85
-Writing placer database...
86
-Writing XDEF routing.
87
-Writing XDEF routing logical nets.
88
-Writing XDEF routing special nets.
89
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
90
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
91
-INFO: [DRC 23-27] Running DRC with 2 threads
92
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
93
-INFO: [Chipscope 16-241] No debug cores found in the current design.
94
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
95
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
96
-Command: place_design -directive RuntimeOptimized
97
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
99
-INFO: [DRC 23-27] Running DRC with 2 threads
100
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
101
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
102
-Running DRC as a precondition to command place_design
103
-INFO: [DRC 23-27] Running DRC with 2 threads
104
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
105
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
106
-
107
-Starting Placer Task
108
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
109
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
110
-
111
-Phase 1 Placer Initialization
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
114
-
115
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
116
-INFO: [Timing 38-35] Done setting XDC timing constraints.
117
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
118
-
119
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
120
-
121
-Phase 1.2 Build Placer Netlist Model
122
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
123
-
124
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
125
-
126
-Phase 1.3 Constrain Clocks/Macros
127
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
128
-
129
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
130
-Phase 1 Placer Initialization | Checksum: f331096b
131
-
132
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
133
-
134
-Phase 2 Global Placement
135
-Phase 2 Global Placement | Checksum: 7e244a0f
136
-
137
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
138
-
139
-Phase 3 Detail Placement
140
-
141
-Phase 3.1 Commit Multi Column Macros
142
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
143
-
144
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
145
-
146
-Phase 3.2 Commit Most Macros & LUTRAMs
147
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
148
-
149
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
150
-
151
-Phase 3.3 Area Swap Optimization
152
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
153
-
154
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
155
-
156
-Phase 3.4 Pipeline Register Optimization
157
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
158
-
159
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
160
-
161
-Phase 3.5 Timing Path Optimizer
162
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
163
-
164
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
165
-
166
-Phase 3.6 Small Shape Detail Placement
167
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
168
-
169
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
170
-
171
-Phase 3.7 Re-assign LUT pins
172
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
173
-
174
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
175
-
176
-Phase 3.8 Pipeline Register Optimization
177
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
178
-
179
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
180
-Phase 3 Detail Placement | Checksum: 1c30709cd
181
-
182
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
183
-
184
-Phase 4 Post Placement Optimization and Clean-Up
185
-
186
-Phase 4.1 Post Commit Optimization
187
-INFO: [Timing 38-35] Done setting XDC timing constraints.
188
-
189
-Phase 4.1.1 Post Placement Optimization
190
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
191
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
192
-
193
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
194
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
195
-
196
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
197
-
198
-Phase 4.2 Post Placement Cleanup
199
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
200
-
201
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
202
-
203
-Phase 4.3 Placer Reporting
204
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
205
-
206
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
207
-
208
-Phase 4.4 Final Placement Cleanup
209
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
210
-
211
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
212
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
213
-
214
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
215
-Ending Placer Task | Checksum: dd20239e
216
-
217
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
218
-INFO: [Common 17-83] Releasing license: Implementation
219
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
220
-place_design completed successfully
221
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
222
-Writing placer database...
223
-Writing XDEF routing.
224
-Writing XDEF routing logical nets.
225
-Writing XDEF routing special nets.
226
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
227
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
228
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
231
-Command: route_design -directive RuntimeOptimized
232
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
233
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
234
-Running DRC as a precondition to command route_design
235
-INFO: [DRC 23-27] Running DRC with 2 threads
236
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
237
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
238
-
239
-
240
-Starting Routing Task
241
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
242
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
243
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
244
-
245
-Phase 1 Build RT Design
246
-Phase 1 Build RT Design | Checksum: be9a9a9a
247
-
248
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
249
-
250
-Phase 2 Router Initialization
251
-
252
-Phase 2.1 Create Timer
253
-Phase 2.1 Create Timer | Checksum: be9a9a9a
254
-
255
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
256
-
257
-Phase 2.2 Fix Topology Constraints
258
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
259
-
260
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
261
-
262
-Phase 2.3 Pre Route Cleanup
263
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
264
-
265
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
266
- Number of Nodes with overlaps = 0
267
-
268
-Phase 2.4 Update Timing
269
-Phase 2.4 Update Timing | Checksum: 111c71c3e
270
-
271
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
272
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
273
-
274
-Phase 2 Router Initialization | Checksum: 1ee683561
275
-
276
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
277
-
278
-Phase 3 Initial Routing
279
-Phase 3 Initial Routing | Checksum: 10e02a291
280
-
281
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
282
-
283
-Phase 4 Rip-up And Reroute
284
-
285
-Phase 4.1 Global Iteration 0
286
- Number of Nodes with overlaps = 107
287
- Number of Nodes with overlaps = 0
288
-
289
-Phase 4.1.1 Update Timing
290
-Phase 4.1.1 Update Timing | Checksum: da308246
291
-
292
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
293
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
294
-
295
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
296
-
297
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
298
-
299
-Phase 4.2 Global Iteration 1
300
- Number of Nodes with overlaps = 1
301
- Number of Nodes with overlaps = 0
302
-
303
-Phase 4.2.1 Update Timing
304
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
305
-
306
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
307
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
308
-
309
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
310
-
311
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
312
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
313
-
314
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
315
-
316
-Phase 5 Delay and Skew Optimization
317
-
318
-Phase 5.1 Delay CleanUp
319
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
320
-
321
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
322
-
323
-Phase 5.2 Clock Skew Optimization
324
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
325
-
326
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
327
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
328
-
329
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
330
-
331
-Phase 6 Post Hold Fix
332
-
333
-Phase 6.1 Hold Fix Iter
334
-
335
-Phase 6.1.1 Update Timing
336
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
337
-
338
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
339
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
340
-
341
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
342
-
343
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
344
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
345
-
346
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
347
-
348
-Phase 7 Route finalize
349
-
350
-Router Utilization Summary
351
-  Global Vertical Routing Utilization    = 0.234075 %
352
-  Global Horizontal Routing Utilization  = 0.228267 %
353
-  Routable Net Status*
354
-  *Does not include unroutable nets such as driverless and loadless.
355
-  Run report_route_status for detailed report.
356
-  Number of Failed Nets               = 0
357
-  Number of Unrouted Nets             = 0
358
-  Number of Partially Routed Nets     = 0
359
-  Number of Node Overlaps             = 0
360
-
361
-Phase 7 Route finalize | Checksum: 1af3f3601
362
-
363
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
364
-
365
-Phase 8 Verifying routed nets
366
-
367
- Verification completed successfully
368
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
369
-
370
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
371
-
372
-Phase 9 Depositing Routes
373
-Phase 9 Depositing Routes | Checksum: 15d59118d
374
-
375
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
376
-
377
-Phase 10 Post Router Timing
378
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
379
-
380
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
381
-Phase 10 Post Router Timing | Checksum: 15d59118d
382
-
383
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
384
-INFO: [Route 35-16] Router Completed Successfully
385
-
386
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
387
-
388
-Routing Is Done.
389
-INFO: [Common 17-83] Releasing license: Implementation
390
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
391
-route_design completed successfully
392
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
393
-Writing placer database...
394
-Writing XDEF routing.
395
-Writing XDEF routing logical nets.
396
-Writing XDEF routing special nets.
397
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
398
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
399
-INFO: [DRC 23-27] Running DRC with 2 threads
400
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
401
-INFO: [Timing 38-35] Done setting XDC timing constraints.
402
-INFO: [DRC 23-133] Running Methodology with 2 threads
403
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
404
-INFO: [Timing 38-35] Done setting XDC timing constraints.
405
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
406
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
407
-INFO: [Timing 38-35] Done setting XDC timing constraints.
408
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
409
-Running Vector-less Activity Propagation...
410
-
411
-Finished Running Vector-less Activity Propagation
412
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
413
-report_power completed successfully
414
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
415
-#-----------------------------------------------------------
416
-# Vivado v2016.4 (64-bit)
417
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
418
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
419
-# Start of session at: Fri Apr 09 23:19:20 2021
420
-# Process ID: 1988
421
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
422
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
423
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
424
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
425
-#-----------------------------------------------------------
426
-source GPIO_demo.tcl -notrace
427
-Command: open_checkpoint GPIO_demo_routed.dcp
428
-
429
-Starting open_checkpoint Task
430
-
431
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
432
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
433
-INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
434
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
435
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
436
-INFO: [Project 1-570] Preparing netlist for logic optimization
437
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
438
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
439
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
440
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
441
-Reading XDEF placement.
442
-Reading placer database...
443
-Reading XDEF routing.
444
-Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
445
-Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
446
-Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
447
-INFO: [Project 1-111] Unisim Transformation Summary:
448
-  A total of 2 instances were transformed.
449
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
450
-
451
-INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
452
-open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
453
-Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
454
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
455
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
456
-Running DRC as a precondition to command write_bitstream
457
-INFO: [DRC 23-27] Running DRC with 2 threads
458
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
459
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
460
-Loading data files...
461
-Loading site data...
462
-Loading route data...
463
-Processing options...
464
-Creating bitmap...
465
-Creating bitstream...
466
-Bitstream compression saved 13383552 bits.
467
-Writing bitstream ./GPIO_demo.bit...
468
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
469
-INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
470
-INFO: [Common 17-83] Releasing license: Implementation
471
-14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
472
-write_bitstream completed successfully
473
-write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
474
-INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
475
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...

+ 0
- 414
proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi View File

@@ -1,414 +0,0 @@
1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Design is defaulting to srcset: sources_1
14
-Design is defaulting to constrset: constrs_1
15
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
16
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
17
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
18
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
19
-INFO: [Project 1-570] Preparing netlist for logic optimization
20
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
22
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
23
-INFO: [Project 1-111] Unisim Transformation Summary:
24
-  A total of 2 instances were transformed.
25
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
26
-
27
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
28
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
29
-Command: opt_design -directive RuntimeOptimized
30
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
31
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
32
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
33
-Running DRC as a precondition to command opt_design
34
-
35
-Starting DRC Task
36
-INFO: [DRC 23-27] Running DRC with 2 threads
37
-INFO: [Project 1-461] DRC finished with 0 Errors
38
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
39
-
40
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
41
-
42
-Starting Logic Optimization Task
43
-Implement Debug Cores | Checksum: 11fc7498c
44
-INFO: [Timing 38-35] Done setting XDC timing constraints.
45
-INFO: [Timing 38-2] Deriving generated clocks
46
-
47
-Phase 1 Retarget
48
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
49
-INFO: [Opt 31-49] Retargeted 0 cell(s).
50
-Phase 1 Retarget | Checksum: 16f269fca
51
-
52
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
53
-
54
-Phase 2 Constant propagation
55
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
56
-INFO: [Opt 31-10] Eliminated 6 cells.
57
-Phase 2 Constant propagation | Checksum: 233a26f9e
58
-
59
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
60
-
61
-Phase 3 Sweep
62
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
63
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
64
-Phase 3 Sweep | Checksum: 1bb596469
65
-
66
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
67
-
68
-Phase 4 BUFG optimization
69
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
70
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
71
-Phase 4 BUFG optimization | Checksum: 1bb596469
72
-
73
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
74
-
75
-Starting Connectivity Check Task
76
-
77
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
78
-Ending Logic Optimization Task | Checksum: 1bb596469
79
-
80
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
81
-INFO: [Common 17-83] Releasing license: Implementation
82
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
83
-opt_design completed successfully
84
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
85
-Writing placer database...
86
-Writing XDEF routing.
87
-Writing XDEF routing logical nets.
88
-Writing XDEF routing special nets.
89
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
90
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
91
-INFO: [DRC 23-27] Running DRC with 2 threads
92
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
93
-INFO: [Chipscope 16-241] No debug cores found in the current design.
94
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
95
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
96
-Command: place_design -directive RuntimeOptimized
97
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
99
-INFO: [DRC 23-27] Running DRC with 2 threads
100
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
101
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
102
-Running DRC as a precondition to command place_design
103
-INFO: [DRC 23-27] Running DRC with 2 threads
104
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
105
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
106
-
107
-Starting Placer Task
108
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
109
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
110
-
111
-Phase 1 Placer Initialization
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
114
-
115
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
116
-INFO: [Timing 38-35] Done setting XDC timing constraints.
117
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
118
-
119
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
120
-
121
-Phase 1.2 Build Placer Netlist Model
122
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
123
-
124
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
125
-
126
-Phase 1.3 Constrain Clocks/Macros
127
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
128
-
129
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
130
-Phase 1 Placer Initialization | Checksum: f331096b
131
-
132
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
133
-
134
-Phase 2 Global Placement
135
-Phase 2 Global Placement | Checksum: 7e244a0f
136
-
137
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
138
-
139
-Phase 3 Detail Placement
140
-
141
-Phase 3.1 Commit Multi Column Macros
142
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
143
-
144
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
145
-
146
-Phase 3.2 Commit Most Macros & LUTRAMs
147
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
148
-
149
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
150
-
151
-Phase 3.3 Area Swap Optimization
152
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
153
-
154
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
155
-
156
-Phase 3.4 Pipeline Register Optimization
157
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
158
-
159
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
160
-
161
-Phase 3.5 Timing Path Optimizer
162
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
163
-
164
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
165
-
166
-Phase 3.6 Small Shape Detail Placement
167
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
168
-
169
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
170
-
171
-Phase 3.7 Re-assign LUT pins
172
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
173
-
174
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
175
-
176
-Phase 3.8 Pipeline Register Optimization
177
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
178
-
179
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
180
-Phase 3 Detail Placement | Checksum: 1c30709cd
181
-
182
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
183
-
184
-Phase 4 Post Placement Optimization and Clean-Up
185
-
186
-Phase 4.1 Post Commit Optimization
187
-INFO: [Timing 38-35] Done setting XDC timing constraints.
188
-
189
-Phase 4.1.1 Post Placement Optimization
190
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
191
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
192
-
193
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
194
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
195
-
196
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
197
-
198
-Phase 4.2 Post Placement Cleanup
199
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
200
-
201
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
202
-
203
-Phase 4.3 Placer Reporting
204
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
205
-
206
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
207
-
208
-Phase 4.4 Final Placement Cleanup
209
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
210
-
211
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
212
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
213
-
214
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
215
-Ending Placer Task | Checksum: dd20239e
216
-
217
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
218
-INFO: [Common 17-83] Releasing license: Implementation
219
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
220
-place_design completed successfully
221
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
222
-Writing placer database...
223
-Writing XDEF routing.
224
-Writing XDEF routing logical nets.
225
-Writing XDEF routing special nets.
226
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
227
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
228
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
231
-Command: route_design -directive RuntimeOptimized
232
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
233
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
234
-Running DRC as a precondition to command route_design
235
-INFO: [DRC 23-27] Running DRC with 2 threads
236
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
237
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
238
-
239
-
240
-Starting Routing Task
241
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
242
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
243
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
244
-
245
-Phase 1 Build RT Design
246
-Phase 1 Build RT Design | Checksum: be9a9a9a
247
-
248
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
249
-
250
-Phase 2 Router Initialization
251
-
252
-Phase 2.1 Create Timer
253
-Phase 2.1 Create Timer | Checksum: be9a9a9a
254
-
255
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
256
-
257
-Phase 2.2 Fix Topology Constraints
258
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
259
-
260
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
261
-
262
-Phase 2.3 Pre Route Cleanup
263
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
264
-
265
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
266
- Number of Nodes with overlaps = 0
267
-
268
-Phase 2.4 Update Timing
269
-Phase 2.4 Update Timing | Checksum: 111c71c3e
270
-
271
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
272
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
273
-
274
-Phase 2 Router Initialization | Checksum: 1ee683561
275
-
276
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
277
-
278
-Phase 3 Initial Routing
279
-Phase 3 Initial Routing | Checksum: 10e02a291
280
-
281
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
282
-
283
-Phase 4 Rip-up And Reroute
284
-
285
-Phase 4.1 Global Iteration 0
286
- Number of Nodes with overlaps = 107
287
- Number of Nodes with overlaps = 0
288
-
289
-Phase 4.1.1 Update Timing
290
-Phase 4.1.1 Update Timing | Checksum: da308246
291
-
292
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
293
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
294
-
295
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
296
-
297
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
298
-
299
-Phase 4.2 Global Iteration 1
300
- Number of Nodes with overlaps = 1
301
- Number of Nodes with overlaps = 0
302
-
303
-Phase 4.2.1 Update Timing
304
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
305
-
306
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
307
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
308
-
309
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
310
-
311
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
312
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
313
-
314
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
315
-
316
-Phase 5 Delay and Skew Optimization
317
-
318
-Phase 5.1 Delay CleanUp
319
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
320
-
321
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
322
-
323
-Phase 5.2 Clock Skew Optimization
324
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
325
-
326
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
327
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
328
-
329
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
330
-
331
-Phase 6 Post Hold Fix
332
-
333
-Phase 6.1 Hold Fix Iter
334
-
335
-Phase 6.1.1 Update Timing
336
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
337
-
338
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
339
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
340
-
341
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
342
-
343
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
344
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
345
-
346
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
347
-
348
-Phase 7 Route finalize
349
-
350
-Router Utilization Summary
351
-  Global Vertical Routing Utilization    = 0.234075 %
352
-  Global Horizontal Routing Utilization  = 0.228267 %
353
-  Routable Net Status*
354
-  *Does not include unroutable nets such as driverless and loadless.
355
-  Run report_route_status for detailed report.
356
-  Number of Failed Nets               = 0
357
-  Number of Unrouted Nets             = 0
358
-  Number of Partially Routed Nets     = 0
359
-  Number of Node Overlaps             = 0
360
-
361
-Phase 7 Route finalize | Checksum: 1af3f3601
362
-
363
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
364
-
365
-Phase 8 Verifying routed nets
366
-
367
- Verification completed successfully
368
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
369
-
370
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
371
-
372
-Phase 9 Depositing Routes
373
-Phase 9 Depositing Routes | Checksum: 15d59118d
374
-
375
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
376
-
377
-Phase 10 Post Router Timing
378
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
379
-
380
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
381
-Phase 10 Post Router Timing | Checksum: 15d59118d
382
-
383
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
384
-INFO: [Route 35-16] Router Completed Successfully
385
-
386
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
387
-
388
-Routing Is Done.
389
-INFO: [Common 17-83] Releasing license: Implementation
390
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
391
-route_design completed successfully
392
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
393
-Writing placer database...
394
-Writing XDEF routing.
395
-Writing XDEF routing logical nets.
396
-Writing XDEF routing special nets.
397
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
398
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
399
-INFO: [DRC 23-27] Running DRC with 2 threads
400
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
401
-INFO: [Timing 38-35] Done setting XDC timing constraints.
402
-INFO: [DRC 23-133] Running Methodology with 2 threads
403
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
404
-INFO: [Timing 38-35] Done setting XDC timing constraints.
405
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
406
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
407
-INFO: [Timing 38-35] Done setting XDC timing constraints.
408
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
409
-Running Vector-less Activity Propagation...
410
-
411
-Finished Running Vector-less Activity Propagation
412
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
413
-report_power completed successfully
414
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...

+ 0
- 235
proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt View File

@@ -1,235 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:39 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : 7a35t-cpg236
9
-| Speed File   : -1  PRODUCTION 1.16 2016-11-09
10
----------------------------------------------------------------------------------------
11
-
12
-Clock Utilization Report
13
-
14
-Table of Contents
15
------------------
16
-1. Clock Primitive Utilization
17
-2. Global Clock Resources
18
-3. Global Clock Source Details
19
-4. Clock Regions: Key Resource Utilization
20
-5. Clock Regions : Global Clock Summary
21
-6. Cell Type Counts per Global Clock: Region X0Y0
22
-7. Cell Type Counts per Global Clock: Region X1Y0
23
-8. Cell Type Counts per Global Clock: Region X0Y1
24
-9. Load Cell Placement Summary for Global Clock g0
25
-10. Load Cell Placement Summary for Global Clock g1
26
-11. Load Cell Placement Summary for Global Clock g2
27
-
28
-1. Clock Primitive Utilization
29
-------------------------------
30
-
31
-+----------+------+-----------+-----+--------------+--------+
32
-| Type     | Used | Available | LOC | Clock Region | Pblock |
33
-+----------+------+-----------+-----+--------------+--------+
34
-| BUFGCTRL |    3 |        32 |   0 |            0 |      0 |
35
-| BUFH     |    0 |        72 |   0 |            0 |      0 |
36
-| BUFIO    |    0 |        20 |   0 |            0 |      0 |
37
-| BUFMR    |    0 |        10 |   0 |            0 |      0 |
38
-| BUFR     |    0 |        20 |   0 |            0 |      0 |
39
-| MMCM     |    1 |         5 |   0 |            0 |      0 |
40
-| PLL      |    0 |         5 |   0 |            0 |      0 |
41
-+----------+------+-----------+-----+--------------+--------+
42
-
43
-
44
-2. Global Clock Resources
45
--------------------------
46
-
47
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
48
-| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock              | Driver Pin                                    | Net                                                    |
49
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
50
-| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |      |                   |                 2 |         336 |               0 |        9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1               |
51
-| g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |      |                   |                 2 |         243 |               0 |       10.000 | sys_clk_pin        | CLK_IBUF_BUFG_inst/O                          | CLK_IBUF_BUFG                                          |
52
-| g2        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y2 | n/a          |      |                   |                 1 |           1 |               0 |       10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O    | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
53
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
54
-* Clock Loads column represents the clock pin loads (pin count)
55
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
56
-
57
-
58
-3. Global Clock Source Details
59
-------------------------------
60
-
61
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
62
-| Source Id | Global Id | Driver Type/Pin     | Constraint | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock       | Driver Pin                                             | Net                                                |
63
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
64
-| src0      | g0        | MMCME2_ADV/CLKOUT0  | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |               9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0  | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
65
-| src0      | g2        | MMCME2_ADV/CLKFBOUT | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |              10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
66
-| src1      | g1        | IBUF/O              | IOB_X1Y26  | IOB_X1Y26       | X1Y0         |           1 |               0 |              10.000 | sys_clk_pin        | CLK_IBUF_inst/O                                        | CLK_IBUF                                           |
67
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
68
-* Clock Loads column represents the clock pin loads (pin count)
69
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
70
-
71
-
72
-4. Clock Regions: Key Resource Utilization
73
-------------------------------------------
74
-
75
-+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
76
-|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
77
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
78
-| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
79
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
80
-| X0Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  484 |  1200 |  206 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
81
-| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   31 |  1500 |    2 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
82
-| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   63 |  1200 |   21 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
83
-| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
84
-| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
85
-| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
86
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
87
-* Global Clock column represents track count; while other columns represents cell counts
88
-
89
-
90
-5. Clock Regions : Global Clock Summary
91
----------------------------------------
92
-
93
-+----+----+----+
94
-|    | X0 | X1 |
95
-+----+----+----+
96
-| Y2 |  0 |  0 |
97
-| Y1 |  1 |  0 |
98
-| Y0 |  2 |  2 |
99
-+----+----+----+
100
-
101
-
102
-6. Cell Type Counts per Global Clock: Region X0Y0
103
--------------------------------------------------
104
-
105
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
106
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
107
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
108
-| g0        | n/a   | BUFG/O          | None       |         273 |               0 | 273 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
109
-| g1        | n/a   | BUFG/O          | None       |         211 |               0 | 211 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | CLK_IBUF_BUFG                            |
110
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
111
-* Clock Loads column represents the clock pin loads (pin count)
112
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
113
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
114
-
115
-
116
-7. Cell Type Counts per Global Clock: Region X1Y0
117
--------------------------------------------------
118
-
119
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
120
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                                    |
121
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
122
-| g1        | n/a   | BUFG/O          | None       |          32 |               0 | 31 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | CLK_IBUF_BUFG                                          |
123
-| g2        | n/a   | BUFG/O          | None       |           1 |               0 |  0 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
124
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
125
-* Clock Loads column represents the clock pin loads (pin count)
126
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
127
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
128
-
129
-
130
-8. Cell Type Counts per Global Clock: Region X0Y1
131
--------------------------------------------------
132
-
133
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
134
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
135
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
136
-| g0        | n/a   | BUFG/O          | None       |          63 |               0 | 63 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
137
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
138
-* Clock Loads column represents the clock pin loads (pin count)
139
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
140
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
141
-
142
-
143
-9. Load Cell Placement Summary for Global Clock g0
144
---------------------------------------------------
145
-
146
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
147
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                      |
148
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
149
-| g0        | BUFG/O          | n/a               | clk_out1_clk_wiz_0 |       9.259 | {0.000 4.630} |          |         336 |        0 |              0 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
150
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
151
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
152
-** IO Loads column represents load cell count of IO types
153
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
154
-**** GT Loads column represents load cell count of GT types
155
-
156
-
157
-+----+------+----+
158
-|    | X0   | X1 |
159
-+----+------+----+
160
-| Y2 |    0 |  0 |
161
-| Y1 |   63 |  0 |
162
-| Y0 |  273 |  0 |
163
-+----+------+----+
164
-
165
-
166
-10. Load Cell Placement Summary for Global Clock g1
167
----------------------------------------------------
168
-
169
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
170
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
171
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
172
-| g1        | BUFG/O          | n/a               | sys_clk_pin |      10.000 | {0.000 5.000} |          |         242 |        0 |              1 |        0 | CLK_IBUF_BUFG |
173
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
174
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
175
-** IO Loads column represents load cell count of IO types
176
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
177
-**** GT Loads column represents load cell count of GT types
178
-
179
-
180
-+----+------+-----+
181
-|    | X0   | X1  |
182
-+----+------+-----+
183
-| Y2 |    0 |   0 |
184
-| Y1 |    0 |   0 |
185
-| Y0 |  211 |  32 |
186
-+----+------+-----+
187
-
188
-
189
-11. Load Cell Placement Summary for Global Clock g2
190
----------------------------------------------------
191
-
192
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
193
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                                    |
194
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
195
-| g2        | BUFG/O          | n/a               | clkfbout_clk_wiz_0 |      10.000 | {0.000 5.000} |          |           0 |        0 |              1 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
196
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
197
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
198
-** IO Loads column represents load cell count of IO types
199
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
200
-**** GT Loads column represents load cell count of GT types
201
-
202
-
203
-+----+----+----+
204
-|    | X0 | X1 |
205
-+----+----+----+
206
-| Y2 |  0 |  0 |
207
-| Y1 |  0 |  0 |
208
-| Y0 |  0 |  1 |
209
-+----+----+----+
210
-
211
-
212
-
213
-# Location of BUFG Primitives 
214
-set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
215
-set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
216
-set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
217
-
218
-# Location of IO Primitives which is load of clock spine
219
-
220
-# Location of clock ports
221
-set_property LOC IOB_X1Y26 [get_ports CLK]
222
-
223
-# Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
224
-#startgroup
225
-create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
226
-add_cells_to_pblock [get_pblocks  {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
227
-resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
228
-#endgroup
229
-
230
-# Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
231
-#startgroup
232
-create_pblock {CLKAG_CLK_IBUF_BUFG}
233
-add_cells_to_pblock [get_pblocks  {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
234
-resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
235
-#endgroup

+ 0
- 104
proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt View File

@@ -1,104 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
---------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35t
9
---------------------------------------------------------------------------------------
10
-
11
-Control Set Information
12
-
13
-Table of Contents
14
------------------
15
-1. Summary
16
-2. Flip-Flop Distribution
17
-3. Detailed Control Set Information
18
-
19
-1. Summary
20
-----------
21
-
22
-+----------------------------------------------------------+-------+
23
-|                          Status                          | Count |
24
-+----------------------------------------------------------+-------+
25
-| Number of unique control sets                            |    36 |
26
-| Unused register locations in slices containing registers |    94 |
27
-+----------------------------------------------------------+-------+
28
-
29
-
30
-2. Flip-Flop Distribution
31
--------------------------
32
-
33
-+--------------+-----------------------+------------------------+-----------------+--------------+
34
-| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
35
-+--------------+-----------------------+------------------------+-----------------+--------------+
36
-| No           | No                    | No                     |             132 |           57 |
37
-| No           | No                    | Yes                    |               0 |            0 |
38
-| No           | Yes                   | No                     |             226 |           57 |
39
-| Yes          | No                    | No                     |             105 |           40 |
40
-| Yes          | No                    | Yes                    |               0 |            0 |
41
-| Yes          | Yes                   | No                     |             115 |           32 |
42
-+--------------+-----------------------+------------------------+-----------------+--------------+
43
-
44
-
45
-3. Detailed Control Set Information
46
------------------------------------
47
-
48
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
49
-|                Clock Signal               |                                Enable Signal                               |                              Set/Reset Signal                              | Slice Load Count | Bel Load Count |
50
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
51
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0                   |                1 |              4 |
52
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0                  |                1 |              4 |
53
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0                             |                                                                            |                2 |              4 |
54
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame                  | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count              |                1 |              4 |
55
-|  CLK_IBUF_BUFG                            | eqOp2_in                                                                   | tmrVal[3]_i_1_n_0                                                          |                2 |              4 |
56
-|  CLK_IBUF_BUFG                            |                                                                            | sendStr[3][0]                                                              |                1 |              5 |
57
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 |                2 |              7 |
58
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0                                      |                                                                            |                2 |              7 |
59
-|  CLK_IBUF_BUFG                            | uartSend                                                                   |                                                                            |                2 |              7 |
60
-|  CLK_IBUF_BUFG                            | uartData                                                                   |                                                                            |                6 |              7 |
61
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0         |                                                                            |                2 |              8 |
62
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0                               |                                                                            |                3 |              8 |
63
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0                               |                                                                            |                4 |              8 |
64
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0             |                                                                            |                2 |             10 |
65
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0                                  |                                                                            |                3 |             11 |
66
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 |                3 |             11 |
67
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in                                                     | Inst_vga_ctrl/v_cntr_reg0                                                  |                3 |             12 |
68
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0                                       |                2 |             12 |
69
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/eqOp4_in                                                     |                3 |             12 |
70
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0                                  |                                                                            |                4 |             12 |
71
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 |                4 |             14 |
72
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0                                        |                4 |             14 |
73
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0                              |                4 |             16 |
74
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0                              |                4 |             16 |
75
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0                              |                4 |             16 |
76
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0                              |                4 |             16 |
77
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0                              |                4 |             16 |
78
-|  CLK_IBUF_BUFG                            |                                                                            |                                                                            |               10 |             17 |
79
-|  CLK_IBUF_BUFG                            |                                                                            | reset_cntr0                                                                |                5 |             18 |
80
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg                                                   |                                                                            |               10 |             23 |
81
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0                      |                7 |             24 |
82
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt                       |                6 |             26 |
83
-|  CLK_IBUF_BUFG                            |                                                                            | tmrCntr0                                                                   |                7 |             27 |
84
-|  CLK_IBUF_BUFG                            | uartData                                                                   | strIndex0                                                                  |                8 |             31 |
85
-|  CLK_IBUF_BUFG                            | Inst_UART_TX_CTRL/txBit_i_1_n_0                                            | Inst_UART_TX_CTRL/READY                                                    |                9 |             32 |
86
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            |                                                                            |               47 |            115 |
87
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
88
-
89
-
90
-+--------+-----------------------+
91
-| Fanout | Number of ControlSets |
92
-+--------+-----------------------+
93
-| 4      |                     5 |
94
-| 5      |                     1 |
95
-| 7      |                     4 |
96
-| 8      |                     3 |
97
-| 10     |                     1 |
98
-| 11     |                     2 |
99
-| 12     |                     4 |
100
-| 14     |                     2 |
101
-| 16+    |                    14 |
102
-+--------+-----------------------+
103
-
104
-

+ 0
- 35
proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt View File

@@ -1,35 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
-------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:01 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_drc -file GPIO_demo_drc_opted.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Synthesized
11
-------------------------------------------------------------------------------------
12
-
13
-Report DRC
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-           Ruledeck: default
26
-             Max violations: <unlimited>
27
-             Violations found: 0
28
-+------+----------+-------------+------------+
29
-| Rule | Severity | Description | Violations |
30
-+------+----------+-------------+------------+
31
-+------+----------+-------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb View File


+ 0
- 35
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt View File

@@ -1,35 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:37 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_drc -file GPIO_demo_drc_routed.rpt -pb GPIO_demo_drc_routed.pb -rpx GPIO_demo_drc_routed.rpx
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Routed
11
----------------------------------------------------------------------------------------------------------------------
12
-
13
-Report DRC
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-           Ruledeck: default
26
-             Max violations: <unlimited>
27
-             Violations found: 0
28
-+------+----------+-------------+------------+
29
-| Rule | Severity | Description | Violations |
30
-+------+----------+-------------+------------+
31
-+------+----------+-------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx View File


+ 0
- 277
proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt View File

@@ -1,277 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
-------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_io -file GPIO_demo_io_placed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35t
9
-| Speed File   : -1
10
-| Package      : cpg236
11
-------------------------------------------------------------------------------------
12
-
13
-IO Information
14
-
15
-Table of Contents
16
------------------
17
-1. Summary
18
-2. IO Assignments by Package Pin
19
-
20
-1. Summary
21
-----------
22
-
23
-+---------------+
24
-| Total User IO |
25
-+---------------+
26
-|            67 |
27
-+---------------+
28
-
29
-
30
-2. IO Assignments by Package Pin
31
---------------------------------
32
-
33
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
34
-| Pin Number | Signal Name  | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity |
35
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
36
-| A1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
37
-| A2         |              |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
38
-| A3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
39
-| A4         |              |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
40
-| A5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
41
-| A6         |              |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
42
-| A7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
43
-| A8         |              |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
44
-| A9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
45
-| A10        |              |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
46
-| A11        |              | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
47
-| A12        |              | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
48
-| A13        |              | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
49
-| A14        |              | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |