No Description
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

GPIO_demo_control_sets_placed.rpt 12KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104
  1. Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  2. --------------------------------------------------------------------------------------
  3. | Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
  4. | Date : Fri Apr 09 23:16:08 2021
  5. | Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
  6. | Command : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
  7. | Design : GPIO_demo
  8. | Device : xc7a35t
  9. --------------------------------------------------------------------------------------
  10. Control Set Information
  11. Table of Contents
  12. -----------------
  13. 1. Summary
  14. 2. Flip-Flop Distribution
  15. 3. Detailed Control Set Information
  16. 1. Summary
  17. ----------
  18. +----------------------------------------------------------+-------+
  19. | Status | Count |
  20. +----------------------------------------------------------+-------+
  21. | Number of unique control sets | 36 |
  22. | Unused register locations in slices containing registers | 94 |
  23. +----------------------------------------------------------+-------+
  24. 2. Flip-Flop Distribution
  25. -------------------------
  26. +--------------+-----------------------+------------------------+-----------------+--------------+
  27. | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
  28. +--------------+-----------------------+------------------------+-----------------+--------------+
  29. | No | No | No | 132 | 57 |
  30. | No | No | Yes | 0 | 0 |
  31. | No | Yes | No | 226 | 57 |
  32. | Yes | No | No | 105 | 40 |
  33. | Yes | No | Yes | 0 | 0 |
  34. | Yes | Yes | No | 115 | 32 |
  35. +--------------+-----------------------+------------------------+-----------------+--------------+
  36. 3. Detailed Control Set Information
  37. -----------------------------------
  38. +-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
  39. | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
  40. +-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
  41. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0 | 1 | 4 |
  42. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0 | 1 | 4 |
  43. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0 | | 2 | 4 |
  44. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count | 1 | 4 |
  45. | CLK_IBUF_BUFG | eqOp2_in | tmrVal[3]_i_1_n_0 | 2 | 4 |
  46. | CLK_IBUF_BUFG | | sendStr[3][0] | 1 | 5 |
  47. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 | 2 | 7 |
  48. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0 | | 2 | 7 |
  49. | CLK_IBUF_BUFG | uartSend | | 2 | 7 |
  50. | CLK_IBUF_BUFG | uartData | | 6 | 7 |
  51. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0 | | 2 | 8 |
  52. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0 | | 3 | 8 |
  53. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0 | | 4 | 8 |
  54. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0 | | 2 | 10 |
  55. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0 | | 3 | 11 |
  56. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 | 3 | 11 |
  57. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in | Inst_vga_ctrl/v_cntr_reg0 | 3 | 12 |
  58. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0 | 2 | 12 |
  59. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/eqOp4_in | 3 | 12 |
  60. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0 | | 4 | 12 |
  61. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 | 4 | 14 |
  62. | CLK_IBUF_BUFG | | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0 | 4 | 14 |
  63. | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0 | 4 | 16 |
  64. | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0 | 4 | 16 |
  65. | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0 | 4 | 16 |
  66. | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0 | 4 | 16 |
  67. | CLK_IBUF_BUFG | | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0 | 4 | 16 |
  68. | CLK_IBUF_BUFG | | | 10 | 17 |
  69. | CLK_IBUF_BUFG | | reset_cntr0 | 5 | 18 |
  70. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg | | 10 | 23 |
  71. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0 | 7 | 24 |
  72. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt | 6 | 26 |
  73. | CLK_IBUF_BUFG | | tmrCntr0 | 7 | 27 |
  74. | CLK_IBUF_BUFG | uartData | strIndex0 | 8 | 31 |
  75. | CLK_IBUF_BUFG | Inst_UART_TX_CTRL/txBit_i_1_n_0 | Inst_UART_TX_CTRL/READY | 9 | 32 |
  76. | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | | | 47 | 115 |
  77. +-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
  78. +--------+-----------------------+
  79. | Fanout | Number of ControlSets |
  80. +--------+-----------------------+
  81. | 4 | 5 |
  82. | 5 | 1 |
  83. | 7 | 4 |
  84. | 8 | 3 |
  85. | 10 | 1 |
  86. | 11 | 2 |
  87. | 12 | 4 |
  88. | 14 | 2 |
  89. | 16+ | 14 |
  90. +--------+-----------------------+