2891 lines
225 KiB
Text
2891 lines
225 KiB
Text
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
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| Date : Fri Apr 09 23:16:38 2021
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| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
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| Command : report_timing_summary -warn_on_violation -max_paths 10 -file GPIO_demo_timing_summary_routed.rpt -rpx GPIO_demo_timing_summary_routed.rpx
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| Design : GPIO_demo
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| Device : 7a35t-cpg236
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| Speed File : -1 PRODUCTION 1.16 2016-11-09
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : false
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock
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2. checking constant_clock
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3. checking pulse_width_clock
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4. checking unconstrained_internal_endpoints
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5. checking no_input_delay
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6. checking no_output_delay
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7. checking multiple_clock
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8. checking generated_clocks
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9. checking loops
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10. checking partial_input_delay
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11. checking partial_output_delay
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12. checking latch_loops
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1. checking no_clock
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--------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock
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--------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock
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-----------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints
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--------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay
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--------------------------
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There are 7 input ports with no input delay specified. (HIGH)
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay
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---------------------------
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There are 29 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock
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--------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks
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----------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops
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-----------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay
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--------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay
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---------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops
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------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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3.744 0.000 0 1137 0.064 0.000 0 1137 3.000 0.000 0 585
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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sys_clk_pin {0.000 5.000} 10.000 100.000
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clk_out1_clk_wiz_0 {0.000 4.630} 9.259 108.000
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clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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sys_clk_pin 4.802 0.000 0 534 0.183 0.000 0 534 3.000 0.000 0 244
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clk_out1_clk_wiz_0 3.744 0.000 0 603 0.064 0.000 0 603 4.130 0.000 0 338
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clkfbout_clk_wiz_0 7.845 0.000 0 3
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Timing Details
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: sys_clk_pin
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To Clock: sys_clk_pin
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Setup : 0 Failing Endpoints, Worst Slack 4.802ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.183ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 4.802ns (required time - arrival time)
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Source: tmrCntr_reg[7]/C
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: tmrCntr_reg[0]/R
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: sys_clk_pin
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
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Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
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Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
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Clock Path Skew: -0.023ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
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Source Clock Delay (SCD): 5.147ns
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Clock Pessimism Removal (CPR): 0.274ns
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.000ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk_pin rise edge)
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0.000 0.000 r
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W5 0.000 0.000 r CLK (IN)
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net (fo=0) 0.000 0.000 CLK
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W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
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net (fo=1, routed) 1.967 3.425 CLK_IBUF
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BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
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net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
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SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
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------------------------------------------------------------------- -------------------
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SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
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net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
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SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
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net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
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SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
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net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
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SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
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net (fo=6, routed) 0.736 8.867 eqOp2_in
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SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
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net (fo=27, routed) 0.867 9.858 tmrCntr0
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SLICE_X62Y18 FDRE r tmrCntr_reg[0]/R
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------------------------------------------------------------------- -------------------
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(clock sys_clk_pin rise edge)
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10.000 10.000 r
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W5 0.000 10.000 r CLK (IN)
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net (fo=0) 0.000 10.000 CLK
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W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
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net (fo=1, routed) 1.862 13.250 CLK_IBUF
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BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
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net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
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SLICE_X62Y18 FDRE r tmrCntr_reg[0]/C
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clock pessimism 0.274 15.124
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clock uncertainty -0.035 15.089
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SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[0]
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-------------------------------------------------------------------
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required time 14.660
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arrival time -9.858
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-------------------------------------------------------------------
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slack 4.802
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Slack (MET) : 4.802ns (required time - arrival time)
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Source: tmrCntr_reg[7]/C
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: tmrCntr_reg[1]/R
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: sys_clk_pin
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
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Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
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Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
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Clock Path Skew: -0.023ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
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Source Clock Delay (SCD): 5.147ns
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Clock Pessimism Removal (CPR): 0.274ns
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.000ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk_pin rise edge)
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0.000 0.000 r
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W5 0.000 0.000 r CLK (IN)
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net (fo=0) 0.000 0.000 CLK
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W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
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net (fo=1, routed) 1.967 3.425 CLK_IBUF
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BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
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net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
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SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
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------------------------------------------------------------------- -------------------
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SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
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net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
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SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
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net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
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SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
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net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
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SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
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net (fo=6, routed) 0.736 8.867 eqOp2_in
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SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
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net (fo=27, routed) 0.867 9.858 tmrCntr0
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SLICE_X62Y18 FDRE r tmrCntr_reg[1]/R
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------------------------------------------------------------------- -------------------
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(clock sys_clk_pin rise edge)
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10.000 10.000 r
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W5 0.000 10.000 r CLK (IN)
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net (fo=0) 0.000 10.000 CLK
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W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
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net (fo=1, routed) 1.862 13.250 CLK_IBUF
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BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
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net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
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SLICE_X62Y18 FDRE r tmrCntr_reg[1]/C
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clock pessimism 0.274 15.124
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clock uncertainty -0.035 15.089
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SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[1]
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-------------------------------------------------------------------
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required time 14.660
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arrival time -9.858
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-------------------------------------------------------------------
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slack 4.802
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Slack (MET) : 4.802ns (required time - arrival time)
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Source: tmrCntr_reg[7]/C
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: tmrCntr_reg[2]/R
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: sys_clk_pin
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
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Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
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Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
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Clock Path Skew: -0.023ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
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Source Clock Delay (SCD): 5.147ns
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Clock Pessimism Removal (CPR): 0.274ns
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.000ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk_pin rise edge)
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0.000 0.000 r
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W5 0.000 0.000 r CLK (IN)
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net (fo=0) 0.000 0.000 CLK
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W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
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net (fo=1, routed) 1.967 3.425 CLK_IBUF
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BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
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net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
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SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
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------------------------------------------------------------------- -------------------
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SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
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net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
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SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
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net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
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SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
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net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
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SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
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net (fo=6, routed) 0.736 8.867 eqOp2_in
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SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
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net (fo=27, routed) 0.867 9.858 tmrCntr0
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SLICE_X62Y18 FDRE r tmrCntr_reg[2]/R
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------------------------------------------------------------------- -------------------
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(clock sys_clk_pin rise edge)
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10.000 10.000 r
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W5 0.000 10.000 r CLK (IN)
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net (fo=0) 0.000 10.000 CLK
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W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
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net (fo=1, routed) 1.862 13.250 CLK_IBUF
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BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
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net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
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SLICE_X62Y18 FDRE r tmrCntr_reg[2]/C
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clock pessimism 0.274 15.124
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clock uncertainty -0.035 15.089
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SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[2]
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-------------------------------------------------------------------
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required time 14.660
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arrival time -9.858
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-------------------------------------------------------------------
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slack 4.802
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Slack (MET) : 4.802ns (required time - arrival time)
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Source: tmrCntr_reg[7]/C
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: tmrCntr_reg[3]/R
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(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: sys_clk_pin
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
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Data Path Delay: 4.711ns (logic 0.952ns (20.210%) route 3.759ns (79.790%))
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Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
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Clock Path Skew: -0.023ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.850ns = ( 14.850 - 10.000 )
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Source Clock Delay (SCD): 5.147ns
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Clock Pessimism Removal (CPR): 0.274ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.867 9.858 tmrCntr0
|
|
SLICE_X62Y18 FDRE r tmrCntr_reg[3]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.509 14.850 CLK_IBUF_BUFG
|
|
SLICE_X62Y18 FDRE r tmrCntr_reg[3]/C
|
|
clock pessimism 0.274 15.124
|
|
clock uncertainty -0.035 15.089
|
|
SLICE_X62Y18 FDRE (Setup_fdre_C_R) -0.429 14.660 tmrCntr_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.660
|
|
arrival time -9.858
|
|
-------------------------------------------------------------------
|
|
slack 4.802
|
|
|
|
Slack (MET) : 4.965ns (required time - arrival time)
|
|
Source: tmrCntr_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: tmrCntr_reg[4]/R
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
|
|
Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
|
|
Source Clock Delay (SCD): 5.147ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.727 9.718 tmrCntr0
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[4]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[4]/C
|
|
clock pessimism 0.298 15.147
|
|
clock uncertainty -0.035 15.112
|
|
SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.683
|
|
arrival time -9.718
|
|
-------------------------------------------------------------------
|
|
slack 4.965
|
|
|
|
Slack (MET) : 4.965ns (required time - arrival time)
|
|
Source: tmrCntr_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: tmrCntr_reg[5]/R
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
|
|
Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
|
|
Source Clock Delay (SCD): 5.147ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.727 9.718 tmrCntr0
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[5]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[5]/C
|
|
clock pessimism 0.298 15.147
|
|
clock uncertainty -0.035 15.112
|
|
SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 14.683
|
|
arrival time -9.718
|
|
-------------------------------------------------------------------
|
|
slack 4.965
|
|
|
|
Slack (MET) : 4.965ns (required time - arrival time)
|
|
Source: tmrCntr_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: tmrCntr_reg[6]/R
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
|
|
Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
|
|
Source Clock Delay (SCD): 5.147ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.727 9.718 tmrCntr0
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[6]/C
|
|
clock pessimism 0.298 15.147
|
|
clock uncertainty -0.035 15.112
|
|
SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 14.683
|
|
arrival time -9.718
|
|
-------------------------------------------------------------------
|
|
slack 4.965
|
|
|
|
Slack (MET) : 4.965ns (required time - arrival time)
|
|
Source: tmrCntr_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: tmrCntr_reg[7]/R
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 4.571ns (logic 0.952ns (20.828%) route 3.619ns (79.172%))
|
|
Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 )
|
|
Source Clock Delay (SCD): 5.147ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.727 9.718 tmrCntr0
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.508 14.849 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
clock pessimism 0.298 15.147
|
|
clock uncertainty -0.035 15.112
|
|
SLICE_X62Y19 FDRE (Setup_fdre_C_R) -0.429 14.683 tmrCntr_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 14.683
|
|
arrival time -9.718
|
|
-------------------------------------------------------------------
|
|
slack 4.965
|
|
|
|
Slack (MET) : 4.994ns (required time - arrival time)
|
|
Source: tmrCntr_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: tmrCntr_reg[24]/R
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 4.511ns (logic 0.952ns (21.102%) route 3.559ns (78.898%))
|
|
Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.030ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.843ns = ( 14.843 - 10.000 )
|
|
Source Clock Delay (SCD): 5.147ns
|
|
Clock Pessimism Removal (CPR): 0.274ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.668 9.659 tmrCntr0
|
|
SLICE_X62Y24 FDRE r tmrCntr_reg[24]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.502 14.843 CLK_IBUF_BUFG
|
|
SLICE_X62Y24 FDRE r tmrCntr_reg[24]/C
|
|
clock pessimism 0.274 15.117
|
|
clock uncertainty -0.035 15.082
|
|
SLICE_X62Y24 FDRE (Setup_fdre_C_R) -0.429 14.653 tmrCntr_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 14.653
|
|
arrival time -9.659
|
|
-------------------------------------------------------------------
|
|
slack 4.994
|
|
|
|
Slack (MET) : 4.994ns (required time - arrival time)
|
|
Source: tmrCntr_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: tmrCntr_reg[25]/R
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 4.511ns (logic 0.952ns (21.102%) route 3.559ns (78.898%))
|
|
Logic Levels: 4 (LUT2=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.030ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.843ns = ( 14.843 - 10.000 )
|
|
Source Clock Delay (SCD): 5.147ns
|
|
Clock Pessimism Removal (CPR): 0.274ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.626 5.147 CLK_IBUF_BUFG
|
|
SLICE_X62Y19 FDRE r tmrCntr_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y19 FDRE (Prop_fdre_C_Q) 0.456 5.603 f tmrCntr_reg[7]/Q
|
|
net (fo=2, routed) 0.812 6.415 tmrCntr_reg[7]
|
|
SLICE_X63Y20 LUT4 (Prop_lut4_I1_O) 0.124 6.539 r tmrVal[3]_i_7/O
|
|
net (fo=1, routed) 0.403 6.942 tmrVal[3]_i_7_n_0
|
|
SLICE_X63Y22 LUT5 (Prop_lut5_I4_O) 0.124 7.066 r tmrVal[3]_i_4/O
|
|
net (fo=1, routed) 0.941 8.007 tmrVal[3]_i_4_n_0
|
|
SLICE_X63Y19 LUT6 (Prop_lut6_I0_O) 0.124 8.131 r tmrVal[3]_i_2/O
|
|
net (fo=6, routed) 0.736 8.867 eqOp2_in
|
|
SLICE_X63Y21 LUT2 (Prop_lut2_I1_O) 0.124 8.991 r tmrCntr[0]_i_1/O
|
|
net (fo=27, routed) 0.668 9.659 tmrCntr0
|
|
SLICE_X62Y24 FDRE r tmrCntr_reg[25]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
10.000 10.000 r
|
|
W5 0.000 10.000 r CLK (IN)
|
|
net (fo=0) 0.000 10.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 13.250 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 13.341 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.502 14.843 CLK_IBUF_BUFG
|
|
SLICE_X62Y24 FDRE r tmrCntr_reg[25]/C
|
|
clock pessimism 0.274 15.117
|
|
clock uncertainty -0.035 15.082
|
|
SLICE_X62Y24 FDRE (Setup_fdre_C_R) -0.429 14.653 tmrCntr_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 14.653
|
|
arrival time -9.659
|
|
-------------------------------------------------------------------
|
|
slack 4.994
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.183ns (arrival time - required time)
|
|
Source: Inst_UART_TX_CTRL/bitIndex_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txBit_reg/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.319ns (logic 0.186ns (58.233%) route 0.133ns (41.767%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.498ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.565 1.448 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X9Y8 FDRE r Inst_UART_TX_CTRL/bitIndex_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X9Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r Inst_UART_TX_CTRL/bitIndex_reg[2]/Q
|
|
net (fo=3, routed) 0.133 1.723 Inst_UART_TX_CTRL/bitIndex_reg[2]
|
|
SLICE_X8Y9 LUT6 (Prop_lut6_I4_O) 0.045 1.768 r Inst_UART_TX_CTRL/txBit_i_2/O
|
|
net (fo=1, routed) 0.000 1.768 Inst_UART_TX_CTRL/txBit_i_2_n_0
|
|
SLICE_X8Y9 FDSE r Inst_UART_TX_CTRL/txBit_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y9 FDSE r Inst_UART_TX_CTRL/txBit_reg/C
|
|
clock pessimism -0.498 1.464
|
|
SLICE_X8Y9 FDSE (Hold_fdse_C_D) 0.120 1.584 Inst_UART_TX_CTRL/txBit_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.584
|
|
arrival time 1.768
|
|
-------------------------------------------------------------------
|
|
slack 0.183
|
|
|
|
Slack (MET) : 0.197ns (arrival time - required time)
|
|
Source: uartData_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txData_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.276ns (logic 0.164ns (59.419%) route 0.112ns (40.581%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.498ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
|
|
SLICE_X8Y7 FDRE r uartData_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X8Y7 FDRE (Prop_fdre_C_Q) 0.164 1.612 r uartData_reg[3]/Q
|
|
net (fo=1, routed) 0.112 1.724 Inst_UART_TX_CTRL/DATA[3]
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/C
|
|
clock pessimism -0.498 1.464
|
|
SLICE_X8Y8 FDRE (Hold_fdre_C_D) 0.063 1.527 Inst_UART_TX_CTRL/txData_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.527
|
|
arrival time 1.724
|
|
-------------------------------------------------------------------
|
|
slack 0.197
|
|
|
|
Slack (MET) : 0.207ns (arrival time - required time)
|
|
Source: Inst_btn_debounce/sig_out_reg_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: btnReg_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.273ns (logic 0.141ns (51.608%) route 0.132ns (48.392%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.955ns
|
|
Source Clock Delay (SCD): 1.443ns
|
|
Clock Pessimism Removal (CPR): 0.498ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.560 1.443 Inst_btn_debounce/CLK_I
|
|
SLICE_X13Y17 FDRE r Inst_btn_debounce/sig_out_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 1.584 r Inst_btn_debounce/sig_out_reg_reg[1]/Q
|
|
net (fo=5, routed) 0.132 1.716 btnDeBnc[1]
|
|
SLICE_X14Y17 FDRE r btnReg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.828 1.955 CLK_IBUF_BUFG
|
|
SLICE_X14Y17 FDRE r btnReg_reg[1]/C
|
|
clock pessimism -0.498 1.457
|
|
SLICE_X14Y17 FDRE (Hold_fdre_C_D) 0.052 1.509 btnReg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.509
|
|
arrival time 1.716
|
|
-------------------------------------------------------------------
|
|
slack 0.207
|
|
|
|
Slack (MET) : 0.221ns (arrival time - required time)
|
|
Source: Inst_btn_debounce/sig_out_reg_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_btn_debounce/sig_out_reg_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.186ns (59.538%) route 0.126ns (40.462%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.957ns
|
|
Source Clock Delay (SCD): 1.445ns
|
|
Clock Pessimism Removal (CPR): 0.512ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.562 1.445 Inst_btn_debounce/CLK_I
|
|
SLICE_X11Y15 FDRE r Inst_btn_debounce/sig_out_reg_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X11Y15 FDRE (Prop_fdre_C_Q) 0.141 1.586 r Inst_btn_debounce/sig_out_reg_reg[3]/Q
|
|
net (fo=5, routed) 0.126 1.713 Inst_btn_debounce/SIGNAL_O[3]
|
|
SLICE_X11Y15 LUT5 (Prop_lut5_I4_O) 0.045 1.758 r Inst_btn_debounce/sig_out_reg[3]_i_1/O
|
|
net (fo=1, routed) 0.000 1.758 Inst_btn_debounce/sig_out_reg[3]_i_1_n_0
|
|
SLICE_X11Y15 FDRE r Inst_btn_debounce/sig_out_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.830 1.957 Inst_btn_debounce/CLK_I
|
|
SLICE_X11Y15 FDRE r Inst_btn_debounce/sig_out_reg_reg[3]/C
|
|
clock pessimism -0.512 1.445
|
|
SLICE_X11Y15 FDRE (Hold_fdre_C_D) 0.091 1.536 Inst_btn_debounce/sig_out_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 1.758
|
|
-------------------------------------------------------------------
|
|
slack 0.221
|
|
|
|
Slack (MET) : 0.223ns (arrival time - required time)
|
|
Source: uartData_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txData_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.318ns (logic 0.141ns (44.389%) route 0.177ns (55.611%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.035ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.449ns
|
|
Clock Pessimism Removal (CPR): 0.478ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.566 1.449 CLK_IBUF_BUFG
|
|
SLICE_X11Y6 FDRE r uartData_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X11Y6 FDRE (Prop_fdre_C_Q) 0.141 1.590 r uartData_reg[5]/Q
|
|
net (fo=1, routed) 0.177 1.767 Inst_UART_TX_CTRL/DATA[5]
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[6]/C
|
|
clock pessimism -0.478 1.484
|
|
SLICE_X8Y8 FDRE (Hold_fdre_C_D) 0.060 1.544 Inst_UART_TX_CTRL/txData_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.544
|
|
arrival time 1.767
|
|
-------------------------------------------------------------------
|
|
slack 0.223
|
|
|
|
Slack (MET) : 0.235ns (arrival time - required time)
|
|
Source: Inst_btn_debounce/sig_out_reg_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: uartState_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.343ns (logic 0.209ns (60.852%) route 0.134ns (39.148%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.961ns
|
|
Source Clock Delay (SCD): 1.447ns
|
|
Clock Pessimism Removal (CPR): 0.498ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.564 1.447 Inst_btn_debounce/CLK_I
|
|
SLICE_X14Y11 FDRE r Inst_btn_debounce/sig_out_reg_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y11 FDRE (Prop_fdre_C_Q) 0.164 1.611 f Inst_btn_debounce/sig_out_reg_reg[4]/Q
|
|
net (fo=5, routed) 0.134 1.746 btnDeBnc[4]
|
|
SLICE_X13Y11 LUT6 (Prop_lut6_I5_O) 0.045 1.791 r uartState[2]_i_1/O
|
|
net (fo=1, routed) 0.000 1.791 uartState[2]_i_1_n_0
|
|
SLICE_X13Y11 FDRE r uartState_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.834 1.961 CLK_IBUF_BUFG
|
|
SLICE_X13Y11 FDRE r uartState_reg[2]/C
|
|
clock pessimism -0.498 1.463
|
|
SLICE_X13Y11 FDRE (Hold_fdre_C_D) 0.092 1.555 uartState_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.555
|
|
arrival time 1.791
|
|
-------------------------------------------------------------------
|
|
slack 0.235
|
|
|
|
Slack (MET) : 0.244ns (arrival time - required time)
|
|
Source: uartData_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txData_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.313ns (logic 0.141ns (45.028%) route 0.172ns (54.972%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.498ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
|
|
SLICE_X9Y7 FDRE r uartData_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X9Y7 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartData_reg[6]/Q
|
|
net (fo=1, routed) 0.172 1.761 Inst_UART_TX_CTRL/DATA[6]
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[7]/C
|
|
clock pessimism -0.498 1.464
|
|
SLICE_X8Y8 FDRE (Hold_fdre_C_D) 0.053 1.517 Inst_UART_TX_CTRL/txData_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 1.761
|
|
-------------------------------------------------------------------
|
|
slack 0.244
|
|
|
|
Slack (MET) : 0.249ns (arrival time - required time)
|
|
Source: uartSend_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txData_reg[1]/CE
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.269ns (logic 0.141ns (52.505%) route 0.128ns (47.495%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.478ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
|
|
SLICE_X11Y8 FDRE r uartSend_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X11Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartSend_reg/Q
|
|
net (fo=8, routed) 0.128 1.717 Inst_UART_TX_CTRL/SEND
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[1]/C
|
|
clock pessimism -0.478 1.484
|
|
SLICE_X8Y8 FDRE (Hold_fdre_C_CE) -0.016 1.468 Inst_UART_TX_CTRL/txData_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.468
|
|
arrival time 1.717
|
|
-------------------------------------------------------------------
|
|
slack 0.249
|
|
|
|
Slack (MET) : 0.249ns (arrival time - required time)
|
|
Source: uartSend_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txData_reg[3]/CE
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.269ns (logic 0.141ns (52.505%) route 0.128ns (47.495%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.478ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
|
|
SLICE_X11Y8 FDRE r uartSend_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X11Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartSend_reg/Q
|
|
net (fo=8, routed) 0.128 1.717 Inst_UART_TX_CTRL/SEND
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[3]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[3]/C
|
|
clock pessimism -0.478 1.484
|
|
SLICE_X8Y8 FDRE (Hold_fdre_C_CE) -0.016 1.468 Inst_UART_TX_CTRL/txData_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.468
|
|
arrival time 1.717
|
|
-------------------------------------------------------------------
|
|
slack 0.249
|
|
|
|
Slack (MET) : 0.249ns (arrival time - required time)
|
|
Source: uartSend_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: Inst_UART_TX_CTRL/txData_reg[4]/CE
|
|
(rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: sys_clk_pin
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
|
|
Data Path Delay: 0.269ns (logic 0.141ns (52.505%) route 0.128ns (47.495%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.962ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.478ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.565 1.448 CLK_IBUF_BUFG
|
|
SLICE_X11Y8 FDRE r uartSend_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X11Y8 FDRE (Prop_fdre_C_Q) 0.141 1.589 r uartSend_reg/Q
|
|
net (fo=8, routed) 0.128 1.717 Inst_UART_TX_CTRL/SEND
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk_pin rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.835 1.962 Inst_UART_TX_CTRL/CLK
|
|
SLICE_X8Y8 FDRE r Inst_UART_TX_CTRL/txData_reg[4]/C
|
|
clock pessimism -0.478 1.484
|
|
SLICE_X8Y8 FDRE (Hold_fdre_C_CE) -0.016 1.468 Inst_UART_TX_CTRL/txData_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.468
|
|
arrival time 1.717
|
|
-------------------------------------------------------------------
|
|
slack 0.249
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: sys_clk_pin
|
|
Waveform(ns): { 0.000 5.000 }
|
|
Period(ns): 10.000
|
|
Sources: { CLK }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 CLK_IBUF_BUFG_inst/I
|
|
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y8 Inst_UART_TX_CTRL/bitIndex_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y10 Inst_UART_TX_CTRL/bitIndex_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y10 Inst_UART_TX_CTRL/bitIndex_reg[11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[14]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[15]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X9Y12 Inst_UART_TX_CTRL/bitIndex_reg[16]/C
|
|
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
|
|
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
|
|
Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[12]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[13]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[14]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y11 Inst_UART_TX_CTRL/bitIndex_reg[15]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y12 Inst_UART_TX_CTRL/bitIndex_reg[16]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y14 Inst_btn_debounce/sig_cntrs_ary_reg[2][0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y14 Inst_btn_debounce/sig_cntrs_ary_reg[2][1]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y14 Inst_btn_debounce/sig_cntrs_ary_reg[2][2]/C
|
|
High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
|
|
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKIN1
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X9Y8 Inst_UART_TX_CTRL/bitIndex_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[3]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[4]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[5]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y8 Inst_UART_TX_CTRL/txData_reg[6]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y16 Inst_btn_debounce/sig_cntrs_ary_reg[2][10]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X8Y16 Inst_btn_debounce/sig_cntrs_ary_reg[2][11]/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clk_out1_clk_wiz_0
|
|
To Clock: clk_out1_clk_wiz_0
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 3.744ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.064ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 4.130ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 3.744ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 5.474ns (logic 2.609ns (47.666%) route 2.865ns (52.334%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 1.047 10.298 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.630 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[2]_i_1/O
|
|
net (fo=1, routed) 0.000 10.630 Inst_vga_ctrl/Inst_MouseCtl/x_pos[2]_i_1_n_0
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]/C
|
|
clock pessimism 0.298 14.416
|
|
clock uncertainty -0.072 14.343
|
|
SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.031 14.374 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.374
|
|
arrival time -10.630
|
|
-------------------------------------------------------------------
|
|
slack 3.744
|
|
|
|
Slack (MET) : 3.938ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 5.252ns (logic 2.569ns (48.913%) route 2.683ns (51.087%))
|
|
Logic Levels: 5 (CARRY4=3 LUT4=1 LUT5=1)
|
|
Clock Path Skew: -0.026ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.158ns
|
|
Clock Pessimism Removal (CPR): 0.274ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.637 5.158 Inst_vga_ctrl/pxl_clk
|
|
SLICE_X1Y42 FDRE r Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y42 FDRE (Prop_fdre_C_Q) 0.456 5.614 r Inst_vga_ctrl/MOUSE_X_POS_REG_reg[5]/Q
|
|
net (fo=2, routed) 0.875 6.489 Inst_vga_ctrl/Inst_MouseDisplay/xpos[5]
|
|
SLICE_X4Y44 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.656 7.145 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_35/CO[3]
|
|
net (fo=1, routed) 0.000 7.145 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_35_n_0
|
|
SLICE_X4Y45 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.334 7.479 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_34/O[1]
|
|
net (fo=2, routed) 0.872 8.351 Inst_vga_ctrl/Inst_MouseDisplay/plusOp26[10]
|
|
SLICE_X7Y45 LUT4 (Prop_lut4_I1_O) 0.303 8.654 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_9/O
|
|
net (fo=1, routed) 0.000 8.654 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_9_n_0
|
|
SLICE_X7Y45 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.491 9.145 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg_i_2/CO[1]
|
|
net (fo=1, routed) 0.936 10.081 Inst_vga_ctrl/Inst_MouseDisplay/geqOp
|
|
SLICE_X3Y39 LUT5 (Prop_lut5_I0_O) 0.329 10.410 r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_1/O
|
|
net (fo=1, routed) 0.000 10.410 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_i_1_n_0
|
|
SLICE_X3Y39 FDRE r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseDisplay/pixel_clk
|
|
SLICE_X3Y39 FDRE r Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg/C
|
|
clock pessimism 0.274 14.392
|
|
clock uncertainty -0.072 14.319
|
|
SLICE_X3Y39 FDRE (Setup_fdre_C_D) 0.029 14.348 Inst_vga_ctrl/Inst_MouseDisplay/enable_mouse_display_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.348
|
|
arrival time -10.410
|
|
-------------------------------------------------------------------
|
|
slack 3.938
|
|
|
|
Slack (MET) : 4.066ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 5.150ns (logic 2.609ns (50.660%) route 2.541ns (49.340%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.723 9.974 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.306 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]_i_1/O
|
|
net (fo=1, routed) 0.000 10.306 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]_i_1_n_0
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
clock pessimism 0.298 14.416
|
|
clock uncertainty -0.072 14.343
|
|
SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.029 14.372 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.372
|
|
arrival time -10.306
|
|
-------------------------------------------------------------------
|
|
slack 4.066
|
|
|
|
Slack (MET) : 4.148ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 5.070ns (logic 2.609ns (51.464%) route 2.461ns (48.536%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.643 9.894 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.226 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_1/O
|
|
net (fo=1, routed) 0.000 10.226 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_1_n_0
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]/C
|
|
clock pessimism 0.298 14.416
|
|
clock uncertainty -0.072 14.343
|
|
SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.031 14.374 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.374
|
|
arrival time -10.226
|
|
-------------------------------------------------------------------
|
|
slack 4.148
|
|
|
|
Slack (MET) : 4.150ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 5.069ns (logic 2.609ns (51.474%) route 2.460ns (48.526%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.298ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.642 9.893 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X5Y43 LUT5 (Prop_lut5_I3_O) 0.332 10.225 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[4]_i_1/O
|
|
net (fo=1, routed) 0.000 10.225 Inst_vga_ctrl/Inst_MouseCtl/x_pos[4]_i_1_n_0
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]/C
|
|
clock pessimism 0.298 14.416
|
|
clock uncertainty -0.072 14.343
|
|
SLICE_X5Y43 FDRE (Setup_fdre_C_D) 0.032 14.375 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.375
|
|
arrival time -10.225
|
|
-------------------------------------------------------------------
|
|
slack 4.150
|
|
|
|
Slack (MET) : 4.278ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 4.902ns (logic 2.609ns (53.218%) route 2.293ns (46.782%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: -0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.860ns = ( 14.120 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.260ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.476 9.727 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X1Y44 LUT5 (Prop_lut5_I3_O) 0.332 10.059 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[0]_i_1/O
|
|
net (fo=1, routed) 0.000 10.059 Inst_vga_ctrl/Inst_MouseCtl/x_pos[0]_i_1_n_0
|
|
SLICE_X1Y44 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.519 14.120 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X1Y44 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]/C
|
|
clock pessimism 0.260 14.380
|
|
clock uncertainty -0.072 14.307
|
|
SLICE_X1Y44 FDRE (Setup_fdre_C_D) 0.029 14.336 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.336
|
|
arrival time -10.059
|
|
-------------------------------------------------------------------
|
|
slack 4.278
|
|
|
|
Slack (MET) : 4.294ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 4.888ns (logic 2.609ns (53.372%) route 2.279ns (46.628%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: -0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.860ns = ( 14.120 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.260ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 f Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.462 9.713 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X3Y46 LUT5 (Prop_lut5_I4_O) 0.332 10.045 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[9]_i_1/O
|
|
net (fo=1, routed) 0.000 10.045 Inst_vga_ctrl/Inst_MouseCtl/x_pos[9]_i_1_n_0
|
|
SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.519 14.120 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]/C
|
|
clock pessimism 0.260 14.380
|
|
clock uncertainty -0.072 14.307
|
|
SLICE_X3Y46 FDRE (Setup_fdre_C_D) 0.031 14.338 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.338
|
|
arrival time -10.045
|
|
-------------------------------------------------------------------
|
|
slack 4.294
|
|
|
|
Slack (MET) : 4.296ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 4.884ns (logic 2.609ns (53.416%) route 2.275ns (46.584%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: -0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.860ns = ( 14.120 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.260ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 f Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.458 9.709 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X3Y46 LUT5 (Prop_lut5_I4_O) 0.332 10.041 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[8]_i_1/O
|
|
net (fo=1, routed) 0.000 10.041 Inst_vga_ctrl/Inst_MouseCtl/x_pos[8]_i_1_n_0
|
|
SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.519 14.120 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X3Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]/C
|
|
clock pessimism 0.260 14.380
|
|
clock uncertainty -0.072 14.307
|
|
SLICE_X3Y46 FDRE (Setup_fdre_C_D) 0.029 14.336 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 14.336
|
|
arrival time -10.041
|
|
-------------------------------------------------------------------
|
|
slack 4.296
|
|
|
|
Slack (MET) : 4.393ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 4.798ns (logic 2.609ns (54.374%) route 2.189ns (45.626%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.273ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.371 9.623 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X4Y46 LUT5 (Prop_lut5_I3_O) 0.332 9.955 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[10]_i_1/O
|
|
net (fo=1, routed) 0.000 9.955 Inst_vga_ctrl/Inst_MouseCtl/x_pos[10]_i_1_n_0
|
|
SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/C
|
|
clock pessimism 0.273 14.391
|
|
clock uncertainty -0.072 14.318
|
|
SLICE_X4Y46 FDRE (Setup_fdre_C_D) 0.029 14.347 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 14.347
|
|
arrival time -9.955
|
|
-------------------------------------------------------------------
|
|
slack 4.393
|
|
|
|
Slack (MET) : 4.396ns (required time - arrival time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 9.259ns (clk_out1_clk_wiz_0 rise@9.259ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 4.798ns (logic 2.609ns (54.374%) route 2.189ns (45.626%))
|
|
Logic Levels: 7 (CARRY4=4 LUT2=1 LUT3=1 LUT5=1)
|
|
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.858ns = ( 14.118 - 9.259 )
|
|
Source Clock Delay (SCD): 5.156ns
|
|
Clock Pessimism Removal (CPR): 0.273ns
|
|
Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.126ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.967 3.425 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 3.521 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.575 5.096 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.333 1.763 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.661 3.425 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.635 5.156 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X5Y43 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.456 5.612 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[1]/Q
|
|
net (fo=5, routed) 0.967 6.579 Inst_vga_ctrl/Inst_MouseCtl/x_pos[1]
|
|
SLICE_X5Y44 LUT3 (Prop_lut3_I0_O) 0.124 6.703 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10/O
|
|
net (fo=1, routed) 0.000 6.703 Inst_vga_ctrl/Inst_MouseCtl/x_pos[3]_i_10_n_0
|
|
SLICE_X5Y44 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 7.253 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.253 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[3]_i_3_n_0
|
|
SLICE_X5Y45 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 7.367 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3/CO[3]
|
|
net (fo=1, routed) 0.000 7.367 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]_i_3_n_0
|
|
SLICE_X5Y46 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 7.606 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_3/O[2]
|
|
net (fo=2, routed) 0.851 8.457 Inst_vga_ctrl/Inst_MouseCtl/plusOp16[10]
|
|
SLICE_X2Y46 LUT2 (Prop_lut2_I0_O) 0.302 8.759 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5/O
|
|
net (fo=1, routed) 0.000 8.759 Inst_vga_ctrl/Inst_MouseCtl/x_pos[11]_i_5_n_0
|
|
SLICE_X2Y46 CARRY4 (Prop_carry4_S[1]_CO[1])
|
|
0.492 9.251 r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[11]_i_2/CO[1]
|
|
net (fo=12, routed) 0.371 9.623 Inst_vga_ctrl/Inst_MouseCtl/gtOp
|
|
SLICE_X4Y46 LUT5 (Prop_lut5_I3_O) 0.332 9.955 r Inst_vga_ctrl/Inst_MouseCtl/x_pos[7]_i_1/O
|
|
net (fo=1, routed) 0.000 9.955 Inst_vga_ctrl/Inst_MouseCtl/x_pos[7]_i_1_n_0
|
|
SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
9.259 9.259 r
|
|
W5 0.000 9.259 r CLK (IN)
|
|
net (fo=0) 0.000 9.259 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 1.388 10.647 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 1.862 12.509 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 12.600 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 1.457 14.058 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-3.129 10.928 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.581 12.509 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 12.600 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 1.517 14.118 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X4Y46 FDRE r Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]/C
|
|
clock pessimism 0.273 14.391
|
|
clock uncertainty -0.072 14.318
|
|
SLICE_X4Y46 FDRE (Setup_fdre_C_D) 0.032 14.350 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 14.350
|
|
arrival time -9.955
|
|
-------------------------------------------------------------------
|
|
slack 4.396
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.064ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.354ns (logic 0.148ns (41.815%) route 0.206ns (58.185%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.273ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.992ns
|
|
Source Clock Delay (SCD): 1.475ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y50 FDRE (Prop_fdre_C_Q) 0.148 1.623 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/Q
|
|
net (fo=3, routed) 0.206 1.829 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[6]
|
|
SLICE_X7Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X7Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]/C
|
|
clock pessimism -0.244 1.748
|
|
SLICE_X7Y49 FDRE (Hold_fdre_C_D) 0.017 1.765 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_data_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.765
|
|
arrival time 1.829
|
|
-------------------------------------------------------------------
|
|
slack 0.064
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.209ns (42.827%) route 0.279ns (57.173%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.300ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.992ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.565 1.448 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X8Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X8Y50 FDRE (Prop_fdre_C_Q) 0.164 1.612 r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[0]/Q
|
|
net (fo=2, routed) 0.279 1.891 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_data[0]
|
|
SLICE_X6Y49 LUT3 (Prop_lut3_I1_O) 0.045 1.936 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[1]_i_1/O
|
|
net (fo=1, routed) 0.000 1.936 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[1]_i_1_n_0
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]/C
|
|
clock pessimism -0.244 1.748
|
|
SLICE_X6Y49 FDRE (Hold_fdre_C_D) 0.120 1.868 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.868
|
|
arrival time 1.936
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.090ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.448ns (logic 0.209ns (46.656%) route 0.239ns (53.344%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.267ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.990ns
|
|
Source Clock Delay (SCD): 1.479ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.596 1.479 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X2Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 1.643 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg[2]/Q
|
|
net (fo=28, routed) 0.239 1.882 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/state_reg_n_0_[2]
|
|
SLICE_X5Y50 LUT6 (Prop_lut6_I1_O) 0.045 1.927 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_inv_i_2/O
|
|
net (fo=1, routed) 0.000 1.927 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_inv_i_1_n_0
|
|
SLICE_X5Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X5Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv/C
|
|
clock pessimism -0.244 1.746
|
|
SLICE_X5Y50 FDRE (Hold_fdre_C_D) 0.091 1.837 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/ps2_data_h_reg_inv
|
|
-------------------------------------------------------------------
|
|
required time -1.837
|
|
arrival time 1.927
|
|
-------------------------------------------------------------------
|
|
slack 0.090
|
|
|
|
Slack (MET) : 0.091ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.485ns (logic 0.246ns (50.728%) route 0.239ns (49.272%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.273ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.992ns
|
|
Source Clock Delay (SCD): 1.475ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y50 FDRE (Prop_fdre_C_Q) 0.148 1.623 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/Q
|
|
net (fo=3, routed) 0.239 1.862 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[6]
|
|
SLICE_X6Y48 LUT5 (Prop_lut5_I3_O) 0.098 1.960 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_i_1/O
|
|
net (fo=1, routed) 0.000 1.960 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_i_1_n_0
|
|
SLICE_X6Y48 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y48 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg/C
|
|
clock pessimism -0.244 1.748
|
|
SLICE_X6Y48 FDRE (Hold_fdre_C_D) 0.121 1.869 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/rx_parity_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.869
|
|
arrival time 1.960
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
Slack (MET) : 0.102ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.506ns (logic 0.185ns (36.583%) route 0.321ns (63.417%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.273ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.992ns
|
|
Source Clock Delay (SCD): 1.475ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X7Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y50 FDRE (Prop_fdre_C_Q) 0.141 1.616 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_parity_reg/Q
|
|
net (fo=1, routed) 0.321 1.937 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/p_1_in[9]
|
|
SLICE_X6Y49 LUT3 (Prop_lut3_I0_O) 0.044 1.981 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_2/O
|
|
net (fo=1, routed) 0.000 1.981 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_2_n_0
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]/C
|
|
clock pessimism -0.244 1.748
|
|
SLICE_X6Y49 FDRE (Hold_fdre_C_D) 0.131 1.879 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time -1.879
|
|
arrival time 1.981
|
|
-------------------------------------------------------------------
|
|
slack 0.102
|
|
|
|
Slack (MET) : 0.104ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.534ns (logic 0.250ns (46.773%) route 0.284ns (53.227%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.300ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.992ns
|
|
Source Clock Delay (SCD): 1.448ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.565 1.448 Inst_vga_ctrl/Inst_MouseCtl/clk
|
|
SLICE_X8Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X8Y50 FDRE (Prop_fdre_C_Q) 0.148 1.596 r Inst_vga_ctrl/Inst_MouseCtl/tx_data_reg[7]/Q
|
|
net (fo=2, routed) 0.284 1.881 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/tx_data[7]
|
|
SLICE_X6Y49 LUT3 (Prop_lut3_I0_O) 0.102 1.983 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[8]_i_1/O
|
|
net (fo=1, routed) 0.000 1.983 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[8]_i_1_n_0
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.865 1.992 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
|
|
clock pessimism -0.244 1.748
|
|
SLICE_X6Y49 FDRE (Hold_fdre_C_D) 0.131 1.879 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.879
|
|
arrival time 1.983
|
|
-------------------------------------------------------------------
|
|
slack 0.104
|
|
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.355ns (72.708%) route 0.133ns (27.292%))
|
|
Logic Levels: 2 (CARRY4=2)
|
|
Clock Path Skew: 0.269ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.990ns
|
|
Source Clock Delay (SCD): 1.477ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.594 1.477 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X4Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y49 FDRE (Prop_fdre_C_Q) 0.141 1.618 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/Q
|
|
net (fo=2, routed) 0.133 1.751 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]
|
|
SLICE_X4Y49 CARRY4 (Prop_carry4_S[2]_CO[3])
|
|
0.160 1.911 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3/CO[3]
|
|
net (fo=1, routed) 0.001 1.911 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3_n_0
|
|
SLICE_X4Y50 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.054 1.965 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 1.965 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1_n_7
|
|
SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]/C
|
|
clock pessimism -0.244 1.746
|
|
SLICE_X4Y50 FDRE (Hold_fdre_C_D) 0.105 1.851 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.851
|
|
arrival time 1.965
|
|
-------------------------------------------------------------------
|
|
slack 0.114
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/h_sync_reg_reg/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/h_sync_reg_dly_reg/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.990ns
|
|
Source Clock Delay (SCD): 1.475ns
|
|
Clock Pessimism Removal (CPR): 0.515ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.592 1.475 Inst_vga_ctrl/pxl_clk
|
|
SLICE_X7Y40 FDRE r Inst_vga_ctrl/h_sync_reg_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y40 FDRE (Prop_fdre_C_Q) 0.141 1.616 r Inst_vga_ctrl/h_sync_reg_reg/Q
|
|
net (fo=1, routed) 0.056 1.672 Inst_vga_ctrl/h_sync_reg
|
|
SLICE_X7Y40 FDRE r Inst_vga_ctrl/h_sync_reg_dly_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/pxl_clk
|
|
SLICE_X7Y40 FDRE r Inst_vga_ctrl/h_sync_reg_dly_reg/C
|
|
clock pessimism -0.515 1.475
|
|
SLICE_X7Y40 FDRE (Hold_fdre_C_D) 0.075 1.550 Inst_vga_ctrl/h_sync_reg_dly_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.550
|
|
arrival time 1.672
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.125ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.499ns (logic 0.366ns (73.309%) route 0.133ns (26.691%))
|
|
Logic Levels: 2 (CARRY4=2)
|
|
Clock Path Skew: 0.269ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.990ns
|
|
Source Clock Delay (SCD): 1.477ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.594 1.477 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X4Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y49 FDRE (Prop_fdre_C_Q) 0.141 1.618 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]/Q
|
|
net (fo=2, routed) 0.133 1.751 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[2]
|
|
SLICE_X4Y49 CARRY4 (Prop_carry4_S[2]_CO[3])
|
|
0.160 1.911 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3/CO[3]
|
|
net (fo=1, routed) 0.001 1.911 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[0]_i_3_n_0
|
|
SLICE_X4Y50 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.065 1.976 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 1.976 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[4]_i_1_n_5
|
|
SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X4Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]/C
|
|
clock pessimism -0.244 1.746
|
|
SLICE_X4Y50 FDRE (Hold_fdre_C_D) 0.105 1.851 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.851
|
|
arrival time 1.976
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.144ns (arrival time - required time)
|
|
Source: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Destination: Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@4.630ns period=9.259ns})
|
|
Path Group: clk_out1_clk_wiz_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
|
|
Data Path Delay: 0.544ns (logic 0.249ns (45.767%) route 0.295ns (54.233%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.269ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.990ns
|
|
Source Clock Delay (SCD): 1.477ns
|
|
Clock Pessimism Removal (CPR): 0.244ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.631 0.858 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 0.884 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.549 1.432 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.061 0.372 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.486 0.858 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.594 1.477 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y49 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y49 FDRE (Prop_fdre_C_Q) 0.148 1.625 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[8]/Q
|
|
net (fo=3, routed) 0.295 1.920 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/CONV_INTEGER[7]
|
|
SLICE_X6Y50 LUT3 (Prop_lut3_I2_O) 0.101 2.021 r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[7]_i_1/O
|
|
net (fo=1, routed) 0.000 2.021 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[7]_i_1_n_0
|
|
SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_clk_wiz_0 rise edge)
|
|
0.000 0.000 r
|
|
W5 0.000 0.000 r CLK (IN)
|
|
net (fo=0) 0.000 0.000 CLK
|
|
W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r CLK_IBUF_inst/O
|
|
net (fo=1, routed) 0.685 1.099 CLK_IBUF
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.128 r CLK_IBUF_BUFG_inst/O
|
|
net (fo=243, routed) 0.817 1.944 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_in1
|
|
MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.375 0.569 r Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.530 1.099 Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O
|
|
net (fo=336, routed) 0.863 1.990 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk
|
|
SLICE_X6Y50 FDRE r Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]/C
|
|
clock pessimism -0.244 1.746
|
|
SLICE_X6Y50 FDRE (Hold_fdre_C_D) 0.131 1.877 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame_reg[7]
|
|
-------------------------------------------------------------------
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required time -1.877
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arrival time 2.021
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-------------------------------------------------------------------
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slack 0.144
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: clk_out1_clk_wiz_0
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Waveform(ns): { 0.000 4.630 }
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Period(ns): 9.259
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Sources: { Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0 }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a BUFG/I n/a 2.155 9.259 7.104 BUFGCTRL_X0Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/I
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Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 9.259 8.010 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X12Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[10]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X14Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[1]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X14Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[2]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[3]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[4]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[5]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X12Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[6]/C
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Min Period n/a FDRE/C n/a 1.000 9.259 8.259 SLICE_X13Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count_reg[7]/C
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Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 9.259 204.101 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0
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Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[0]/C
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Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[1]/C
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Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[2]/C
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Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X1Y31 Inst_vga_ctrl/cntDyn_reg[3]/C
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Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X4Y46 Inst_vga_ctrl/Inst_MouseCtl/x_pos_reg[10]/C
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Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[1]/C
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Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[2]/C
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Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[5]/C
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Low Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X5Y42 Inst_vga_ctrl/Inst_MouseCtl/y_pos_reg[7]/C
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Low Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X6Y45 Inst_vga_ctrl/MOUSE_X_POS_REG_reg[10]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X7Y50 Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_done_reg/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[13]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X9Y44 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[14]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[15]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[16]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[17]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X9Y44 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[18]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y45 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[19]/C
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High Pulse Width Slow FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y42 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[1]/C
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High Pulse Width Fast FDRE/C n/a 0.500 4.630 4.130 SLICE_X11Y42 Inst_vga_ctrl/Inst_MouseCtl/periodic_check_cnt_reg[1]/C
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---------------------------------------------------------------------------------------------------
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From Clock: clkfbout_clk_wiz_0
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To Clock: clkfbout_clk_wiz_0
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: clkfbout_clk_wiz_0
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Waveform(ns): { 0.000 5.000 }
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Period(ns): 10.000
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Sources: { Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y2 Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/I
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Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT
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Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBIN
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Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBIN
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Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y0 Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT
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