205 lines
6.8 KiB
Text
205 lines
6.8 KiB
Text
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
|
|
| Date : Fri Apr 09 23:16:38 2021
|
|
| Host : DESKTOP-GN6T5R2 running 64-bit major release (build 9200)
|
|
| Command : report_methodology -file GPIO_demo_methodology_drc_routed.rpt -rpx GPIO_demo_methodology_drc_routed.rpx
|
|
| Design : GPIO_demo
|
|
| Device : xc7a35tcpg236-1
|
|
| Speed File : -1
|
|
| Design State : Routed
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
|
|
Report Methodology
|
|
|
|
Table of Contents
|
|
-----------------
|
|
1. REPORT SUMMARY
|
|
2. REPORT DETAILS
|
|
|
|
1. REPORT SUMMARY
|
|
-----------------
|
|
Netlist: netlist
|
|
Floorplan: design_1
|
|
Design limits: <entire design considered>
|
|
Max violations: <unlimited>
|
|
Violations found: 34
|
|
+-----------+----------+-------------------------------+------------+
|
|
| Rule | Severity | Description | Violations |
|
|
+-----------+----------+-------------------------------+------------+
|
|
| TIMING-18 | Warning | Missing input or output delay | 34 |
|
|
+-----------+----------+-------------------------------+------------+
|
|
|
|
2. REPORT DETAILS
|
|
-----------------
|
|
TIMING-18#1 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on BTN[0] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#2 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on BTN[1] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#3 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on BTN[2] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#4 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on BTN[3] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#5 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on BTN[4] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#6 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on PS2_CLK relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#7 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on PS2_DATA relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#8 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_AN[0] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#9 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_AN[1] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#10 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_AN[2] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#11 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_AN[3] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#12 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[0] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#13 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[1] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#14 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[2] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#15 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[3] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#16 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[4] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#17 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[5] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#18 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[6] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#19 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on SSEG_CA[7] relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#20 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on UART_TXD relative to clock(s) sys_clk_pin
|
|
Related violations: <none>
|
|
|
|
TIMING-18#21 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_BLUE[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#22 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_BLUE[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#23 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_BLUE[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#24 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_BLUE[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#25 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_GREEN[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#26 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_GREEN[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#27 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_GREEN[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#28 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_GREEN[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#29 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_HS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#30 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_RED[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#31 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_RED[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#32 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_RED[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#33 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_RED[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
TIMING-18#34 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on VGA_VS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0
|
|
Related violations: <none>
|
|
|
|
|