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System.vhd 1.8KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 09.04.2021 22:03:10
  6. -- Design Name:
  7. -- Module Name: System - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity System is
  30. Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
  31. btnL : in STD_LOGIC;
  32. btnC : in STD_LOGIC;
  33. btnR : in STD_LOGIC;
  34. btnD : in STD_LOGIC;
  35. LED : out STD_LOGIC_VECTOR (0 to 7);
  36. CLK : in STD_LOGIC);
  37. end System;
  38. architecture Structural of System is
  39. component ClockDivider1000
  40. Port ( clk_in : in STD_LOGIC;
  41. clk_out : out STD_LOGIC);
  42. end component;
  43. component Compteur
  44. Port ( CK : in STD_LOGIC;
  45. RST : in STD_LOGIC;
  46. SENS : in STD_LOGIC;
  47. LOAD : in STD_LOGIC;
  48. EN : in STD_LOGIC;
  49. Din : in STD_LOGIC_VECTOR (7 downto 0);
  50. Dout : out STD_LOGIC_VECTOR (7 downto 0));
  51. end component;
  52. signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
  53. begin
  54. DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
  55. DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
  56. CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
  57. end Structural;