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Merge processeur non securise et securise

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This commit is contained in:
Paul Faure 2021-06-24 13:42:08 +02:00
commit 961344803c
11 changed files with 254 additions and 188 deletions
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5
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd
View file

@ -100,7 +100,8 @@ begin
IN_Instruction => my_IN_Instruction,
OUT_A => my_OUT_A,
OUT_B => my_OUT_B,
OUT_Instruction => my_OUT_Instruction);
OUT_Instruction => my_OUT_Instruction,
OUT_AddrRetour => my_OUT_AddrRetour);
CLK_process :process
begin
@ -118,4 +119,4 @@ begin
my_RST <= '0' after 125 ns;
wait;
end process;
end Behavioral;
end Behavioral;

4
Processeur.srcs/sim_1/new/Test_Pipeline.vhd
View file

@ -45,9 +45,7 @@ architecture Behavioral of Test_Pipeline is
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Memoire_Size : Natural := 32);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);

85
Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd → Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd
View file

@ -3,7 +3,7 @@
-- Engineer: Paul Faure
--
-- Create Date: 18.04.2021 21:19:41
-- Module Name: Etage1_LectureInstruction - Behavioral
-- Module Name: Etage1_LectureInstruction_NS - Behavioral
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
@ -24,15 +24,13 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Etage1_LectureInstruction is
entity Etage1_LectureInstruction_NS is
Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
Nb_bits : Natural; -- Taille d'un mot binaire
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Nb_registres : Natural; -- Nombre de registres du processeurs
Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale)
Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA)
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB)
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC)
@ -58,15 +56,16 @@ entity Etage1_LectureInstruction is
Port ( CLK : in STD_LOGIC; -- Clock
RST : in STD_LOGIC; -- Reset
Z : in STD_LOGIC; -- Flag Zero de l'ALU (utile pour le JMZ)
Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
end Etage1_LectureInstruction;
end Etage1_LectureInstruction_NS;
architecture Behavioral of Etage1_LectureInstruction is
architecture Behavioral of Etage1_LectureInstruction_NS is
component MemoireInstructions is
Generic (Nb_bits : Natural;
Addr_size : Natural;
@ -75,23 +74,8 @@ architecture Behavioral of Etage1_LectureInstruction is
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
end component;
-- Signaux pour récuperer l'instruction de la mémoire
signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
@ -99,13 +83,6 @@ architecture Behavioral of Etage1_LectureInstruction is
subtype Registre is integer range -1 to Nb_registres - 1;
type Tab_registres is array (1 to 3) of Registre;
signal Tableau : Tab_registres := (others => - 1);
-- Signaux de gestion pour la mémoire des adresses de retour
signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
signal E : STD_LOGIC;
signal F : STD_LOGIC;
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
-- constantes pour injecter des bulles dans le pipeline
constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
@ -127,21 +104,6 @@ begin
Mem_size => Mem_instruction_size)
port map (Addr => Pointeur_Instruction,
D_OUT => Instruction_courante);
instance_MemoireAdressesRetour : MemoireAdressesRetour
generic map (Nb_bits => Addr_size_mem_instruction,
Addr_size => Adresse_size_mem_adresse_retour,
Mem_size => Mem_adresse_retour_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => Pointeur_instruction_next,
RST => RST,
CLK => CLK,
D_OUT => Adresse_Retour,
E => E,
F => F
);
process
@ -166,19 +128,29 @@ begin
if (not bulles) then
-- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
-- CAS PARTICULIER : CALL ou JMP, on transmet et on saute
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
-- CAS PARTICULIER : CALL ou JMP, on transmet (en modifiant le paramètre A pour le CALL (addr de retour à stocker))et on saute
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); -- STOCKER
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
A <= ((Nb_bits - 1 downto Addr_size_mem_instruction => '0') & Pointeur_Instruction) + 1;
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
-- CAS PARTICULIER : RET, on transmet et on revient
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
Pointeur_Instruction <= Adresse_Retour;
-- CAS PARTICULIER : RET, on transmet une seule fois, on attend et on revient
compteur <= compteur + 1;
if (compteur = 1) then
C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
elsif (compteur = 5) then
Pointeur_Instruction <= Addr_Retour (Addr_size_mem_instruction - 1 downto 0);
compteur <= 0;
else
C <= Argument_nul;
B <= Argument_nul;
A <= Argument_nul;
Instruction <= Instruction_nulle;
end if;
elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
-- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement
compteur <= compteur + 1;
@ -278,12 +250,5 @@ begin
)
);
-- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
'0';
W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
'0';
Pointeur_instruction_next <= Pointeur_instruction + 1;
end Behavioral;

113
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd → Processeur.srcs/sources_1/new/Etage4_Memoire_NS.vhd
View file

@ -3,7 +3,7 @@
-- Engineer: Paul Faure
--
-- Create Date: 18.04.2021 21:19:41
-- Module Name: Etage4_Memoire - Structural
-- Module Name: Etage4_Memoire_NS - Structural
-- Project Name: Processeur sécurisé
-- Target Devices: Basys 3 ARTIX7
-- Tool Versions: Vivado 2016.4
@ -24,13 +24,11 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Etage4_Memoire is
entity Etage4_Memoire_NS is
Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
@ -44,34 +42,27 @@ entity Etage4_Memoire is
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
end Etage4_Memoire;
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
end Etage4_Memoire_NS;
architecture Structural of Etage4_Memoire is
architecture Structural of Etage4_Memoire_NS is
component MemoireDonnees is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
RW : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
end component;
component MemoireAdressesRetour is
Generic (Nb_bits : Natural;
Addr_size : Natural;
Mem_size : Natural);
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
E : out STD_LOGIC;
F : out STD_LOGIC);
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
CALL : in STD_LOGIC; -- '1' -> CALL en cours
IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
RET : in STD_LOGIC; -- '1' -> RET en cours
OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
RST : in STD_LOGIC; -- Reset
CLK : in STD_LOGIC; -- Clock
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
end component;
component LC is
@ -94,7 +85,9 @@ architecture Structural of Etage4_Memoire is
signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse)
signal Last_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Ancien EBP, valeur récupérée en mémoire lors d'un RET
signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd)
signal IN_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- EBP à stocker ne mémoire (ajout de 0)
signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees
signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B
@ -106,11 +99,9 @@ architecture Structural of Etage4_Memoire is
signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne
-- Signaux de la memoire de contexte
signal R_Aux : STD_LOGIC := '0';
signal W_Aux : STD_LOGIC := '0';
signal E : STD_LOGIC;
signal F : STD_LOGIC;
-- Signaux de contrôle de la mémoire
signal CALL_Aux : STD_LOGIC := '0';
signal RET_Aux : STD_LOGIC := '0';
begin
@ -152,27 +143,18 @@ begin
generic map (Nb_bits => Nb_bits,
Addr_size => Adresse_mem_size,
Mem_size => Mem_size)
port map ( Addr => Addr_MemoireDonnees,
RW => Commande_MemoireDonnees(0),
D_IN => IN_B,
RST => RST,
CLK => CLK,
D_OUT => Sortie_MemoireDonnees);
instance_MemoireEBP : MemoireAdressesRetour
generic map (Nb_bits => Adresse_mem_size,
Addr_size => Adresse_size_mem_EBP,
Mem_size => Mem_EBP_size
)
port map ( R => R_Aux,
W => W_Aux,
D_IN => New_EBP,
RST => RST,
CLK => CLK,
D_OUT => EBP,
E => E,
F => F
);
port map (Addr => Addr_MemoireDonnees,
RW => Commande_MemoireDonnees(0),
D_IN => IN_B,
CALL => CALL_Aux,
IN_EBP => IN_EBP,
IN_AddrRet => IN_A,
RET => RET_Aux,
OUT_EBP => Last_EBP,
OUT_AddrRet => OUT_AddrRetour,
RST => RST,
CLK => CLK,
D_OUT => Sortie_MemoireDonnees);
OUT_A <= (others => '0') when RST = '0' else
IN_A;
@ -181,12 +163,27 @@ begin
OUT_Instruction <= (others => '0') when RST = '0' else
IN_Instruction;
-- Controle de la mémoire de contexte (ici aussi un LC aurait été disproportionné)
R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
-- Controle de la gestion des appels de fonctions (ici aussi un LC aurait été disproportionné)
RET_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
'0';
W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
'0';
process
begin
wait until CLK'event and CLK = '1';
if (IN_Instruction = Code_Instruction_CALL) then
EBP <= New_EBP;
elsif (IN_Instruction = Code_Instruction_RET) then
EBP <= Last_EBP (Adresse_mem_size - 1 downto 0);
elsif (RST = '0') then
EBP <= (others => '0');
end if;
end process;
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
end Structural;
end Structural;

19
Processeur.srcs/sources_1/new/MemoireDonnees.vhd
View file

@ -23,6 +23,12 @@ entity MemoireDonnees is
Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
CALL : in STD_LOGIC; -- '1' -> CALL en cours
IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
RET : in STD_LOGIC; -- '1' -> RET en cours
OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
RST : in STD_LOGIC; -- Reset
CLK : in STD_LOGIC; -- Clock
D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
@ -37,7 +43,12 @@ begin
if (RST = '0') then
MEMORY <= (others => '0');
else
if (RW = '0') then
if (CALL = '1') then
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
elsif (RET = '1') then
MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto ((to_integer(unsigned(Addr)) - 2) * Nb_bits)) <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr)));
elsif (RW = '0') then
MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
end if;
end if;
@ -45,4 +56,10 @@ begin
-- Lecture assynchrone et en permanence
D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
-- Sortie lors du ret en assynchrone
OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)) when (RET = '1') else
(others => '0');
OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)) when (RET = '1') else
(others => '0');
end Behavioral;

2
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
View file

File diff suppressed because one or more lines are too long

44
Processeur.srcs/sources_1/new/Pipeline.vhd → Processeur.srcs/sources_1/new/Pipeline_NS.vhd
View file

@ -4,7 +4,7 @@
--
-- Create Date: 19.04.2021 16:57:41
-- Design Name:
-- Module Name: Pipeline - Behavioral
-- Module Name: Pipeline_NS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity Pipeline is
entity Pipeline_NS is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
@ -41,26 +41,22 @@ entity Pipeline is
Nb_Registres : Natural := 16;
Addr_registres_size : Natural := 4;
Memoire_Size : Natural := 32;
Adresse_mem_size : Natural := 5;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Adresse_mem_size : Natural := 5);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end Pipeline;
end Pipeline_NS;
architecture Behavioral of Pipeline is
architecture Behavioral of Pipeline_NS is
component Etage1_LectureInstruction is
component Etage1_LectureInstruction_NS is
Generic (Instruction_size_in_memory : Natural;
Addr_size_mem_instruction : Natural;
Mem_instruction_size : Natural;
Nb_bits : Natural;
Instruction_bus_size : Natural;
Nb_registres : Natural;
Mem_adresse_retour_size : Natural;
Adresse_size_mem_adresse_retour : Natural;
Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
@ -73,6 +69,7 @@ architecture Behavioral of Pipeline is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Z : in STD_LOGIC;
Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -125,13 +122,11 @@ architecture Behavioral of Pipeline is
C : out STD_LOGIC);
end component;
component Etage4_Memoire is
component Etage4_Memoire_NS is
Generic ( Nb_bits : Natural;
Mem_size : Natural;
Adresse_mem_size : Natural;
Instruction_bus_size : Natural;
Mem_EBP_size : Natural;
Adresse_size_mem_EBP : Natural;
Bits_Controle_LC : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
@ -145,7 +140,8 @@ architecture Behavioral of Pipeline is
IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
end component;
signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
@ -180,14 +176,15 @@ architecture Behavioral of Pipeline is
signal Z : STD_LOGIC := '0';
signal O : STD_LOGIC := '0';
signal C : STD_LOGIC := '0';
signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC
constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111";
constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP
constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
@ -203,15 +200,13 @@ architecture Behavioral of Pipeline is
constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
begin
instance_Etage1 : Etage1_LectureInstruction
instance_Etage1 : Etage1_LectureInstruction_NS
generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
Mem_instruction_size => Memoire_Instruction_Size,
Nb_bits => Nb_bits,
Instruction_bus_size => Instruction_Bus_Size,
Nb_registres => Nb_Registres,
Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
@ -226,6 +221,7 @@ begin
CLK => CLK,
RST => RST,
Z => Z,
Addr_Retour => AdresseRetour,
A => A_from_1,
B => B_from_1,
C => C_from_1,
@ -280,13 +276,11 @@ begin
C => C
);
instance_Etage4 : Etage4_Memoire
instance_Etage4 : Etage4_Memoire_NS
generic map( Nb_bits => Nb_bits,
Mem_size => Memoire_Size,
Adresse_mem_size => Adresse_mem_size,
Instruction_bus_size => Instruction_Bus_Size,
Mem_EBP_size => Memoire_Adresses_Retour_Size,
Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
Bits_Controle_LC => Bits_Controle_LC_4,
Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
@ -301,7 +295,8 @@ begin
IN_Instruction => Instruction_to_4,
OUT_A => A_from_4,
OUT_B => B_from_4,
OUT_Instruction => Instruction_from_4
OUT_Instruction => Instruction_from_4,
OUT_AddrRetour => AdresseRetour
);
process
@ -326,3 +321,4 @@ begin
Instruction_to_5 <= Instruction_from_4;
end process;
end Behavioral;

10
Processeur.srcs/sources_1/new/System.vhd
View file

@ -31,7 +31,7 @@ entity System is
end System;
architecture Structural of System is
component Pipeline is
component Pipeline_NS is
Generic (Nb_bits : Natural := 8;
Instruction_En_Memoire_Size : Natural := 29;
Addr_Memoire_Instruction_Size : Natural := 3;
@ -39,9 +39,7 @@ architecture Structural of System is
Instruction_Bus_Size : Natural := 5;
Nb_Instructions : Natural := 32;
Nb_Registres : Natural := 16;
Memoire_Size : Natural := 32;
Memoire_Adresses_Retour_Size : Natural := 16;
Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
Memoire_Size : Natural := 32);
Port (CLK : STD_LOGIC;
RST : STD_LOGIC;
STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@ -57,14 +55,14 @@ architecture Structural of System is
signal my_RST : STD_LOGIC;
signal my_CLK : STD_LOGIC;
begin
begin
-- Diviseur de clock
clk_div : Clock_Divider
port map (CLK_IN => CLK,
CLK_OUT => my_CLK);
-- Le processeur, augmentation de la taille de la mémoire d'instruction
instance : Pipeline
instance : Pipeline_NS
generic map (Addr_Memoire_Instruction_Size => 8,
Memoire_Instruction_Size => 256)
port map (CLK => my_CLK,

30
Processeur.xpr
View file

@ -32,7 +32,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="258"/>
<Option Name="WTXSimLaunchSim" Val="339"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -103,37 +103,37 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
<File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>

31
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg
View file

@ -30,38 +30,49 @@
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_A">
<obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
</wvobject>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
<obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_Instruction">
<obj_property name="ElementShortName">my_IN_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">my_IN_Instruction[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_A">
<obj_property name="ElementShortName">my_OUT_A[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_A[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_B">
<obj_property name="ElementShortName">my_OUT_B[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_B[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_Instruction">
<obj_property name="ElementShortName">my_OUT_Instruction[4:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_Instruction[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
<obj_property name="ElementShortName">Addr[3:0]</obj_property>
<obj_property name="ObjectShortName">Addr[3:0]</obj_property>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_AddrRetour">
<obj_property name="ElementShortName">my_OUT_AddrRetour[7:0]</obj_property>
<obj_property name="ObjectShortName">my_OUT_AddrRetour[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/EBP">
<obj_property name="ElementShortName">EBP[3:0]</obj_property>
<obj_property name="ObjectShortName">EBP[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">RW</obj_property>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Last_EBP">
<obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/OUT_EBP">
<obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
<obj_property name="ElementShortName">MEMORY[127:0]</obj_property>

99
SimulationsConfig/Test_Pipeline_behav1.wcfg
View file

@ -10,15 +10,15 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="1000913916666fs"></ZoomStartTime>
<ZoomEndTime time="1001017216667fs"></ZoomEndTime>
<Cursor1Time time="1001000000000fs"></Cursor1Time>
<ZoomStartTime time="9750000000fs"></ZoomStartTime>
<ZoomEndTime time="10289000001fs"></ZoomEndTime>
<Cursor1Time time="10000000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="146"></NameColumnWidth>
<ValueColumnWidth column_width="71"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="11" />
<WVObjectSize size="12" />
<wvobject type="logic" fp_name="/Test_Pipeline/my_CLK">
<obj_property name="ElementShortName">my_CLK</obj_property>
<obj_property name="ObjectShortName">my_CLK</obj_property>
@ -163,9 +163,10 @@
<obj_property name="ObjectShortName">DATA[7:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group57">
<wvobject type="group" fp_name="group115">
<obj_property name="label">Memoire</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/MEMORY">
<obj_property name="ElementShortName">MEMORY[255:0]</obj_property>
<obj_property name="ObjectShortName">MEMORY[255:0]</obj_property>
@ -174,17 +175,99 @@
<obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
<obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_AddrRet">
<obj_property name="ElementShortName">OUT_AddrRet[7:0]</obj_property>
<obj_property name="ObjectShortName">OUT_AddrRet[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_EBP">
<obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_AddrRet">
<obj_property name="ElementShortName">IN_AddrRet[7:0]</obj_property>
<obj_property name="ObjectShortName">IN_AddrRet[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_EBP">
<obj_property name="ElementShortName">IN_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">IN_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/CALL">
<obj_property name="ElementShortName">CALL</obj_property>
<obj_property name="ObjectShortName">CALL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RET">
<obj_property name="ElementShortName">RET</obj_property>
<obj_property name="ObjectShortName">RET</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/Addr">
<obj_property name="ElementShortName">Addr[4:0]</obj_property>
<obj_property name="ObjectShortName">Addr[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_IN">
<obj_property name="ElementShortName">D_IN[7:0]</obj_property>
<obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RW">
<obj_property name="ElementShortName">RW</obj_property>
<obj_property name="ObjectShortName">RW</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Last_EBP">
<obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
<obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/EBP">
<obj_property name="ElementShortName">EBP[4:0]</obj_property>
<obj_property name="ObjectShortName">EBP[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees">
<obj_property name="ElementShortName">Addr_MemoireDonnees[4:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/IN_Addr_MemoireDonnees">
<obj_property name="ElementShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
<obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees_EBP">
<obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
<obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group121">
<obj_property name="label">Instructions</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage1/Z">
<obj_property name="ElementShortName">Z</obj_property>
<obj_property name="ObjectShortName">Z</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Addr_Retour">
<obj_property name="ElementShortName">Addr_Retour[7:0]</obj_property>
<obj_property name="ObjectShortName">Addr_Retour[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Pointeur_instruction">
<obj_property name="ElementShortName">Pointeur_instruction[7:0]</obj_property>
<obj_property name="ObjectShortName">Pointeur_instruction[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Instruction_courante">
<obj_property name="ElementShortName">Instruction_courante[28:0]</obj_property>
<obj_property name="ObjectShortName">Instruction_courante[28:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Tableau">
<obj_property name="ElementShortName">Tableau[1:3]</obj_property>
<obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/bulles">
<obj_property name="ElementShortName">bulles</obj_property>
<obj_property name="ObjectShortName">bulles</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/compteur">
<obj_property name="ElementShortName">compteur</obj_property>
<obj_property name="ObjectShortName">compteur</obj_property>
</wvobject>
<wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/locked">
<obj_property name="ElementShortName">locked</obj_property>
<obj_property name="ObjectShortName">locked</obj_property>
</wvobject>
</wvobject>
</wave_config>