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Merge processeur non securise et securise

Paul Faure 3 months ago
parent
commit
961344803c

+ 3
- 2
Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd View File

@@ -100,7 +100,8 @@ begin
100 100
                  IN_Instruction => my_IN_Instruction,
101 101
                  OUT_A => my_OUT_A,
102 102
                  OUT_B => my_OUT_B,
103
-                 OUT_Instruction => my_OUT_Instruction);
103
+                 OUT_Instruction => my_OUT_Instruction,
104
+                 OUT_AddrRetour => my_OUT_AddrRetour);
104 105
     
105 106
     CLK_process :process
106 107
     begin
@@ -118,4 +119,4 @@ begin
118 119
         my_RST <= '0' after 125 ns;
119 120
         wait;
120 121
     end process;    
121
-end Behavioral;
122
+end Behavioral;

+ 1
- 3
Processeur.srcs/sim_1/new/Test_Pipeline.vhd View File

@@ -45,9 +45,7 @@ architecture Behavioral of Test_Pipeline is
45 45
              Instruction_Bus_Size : Natural := 5;
46 46
              Nb_Instructions : Natural := 32;
47 47
              Nb_Registres : Natural := 16;
48
-             Memoire_Size : Natural := 32;
49
-             Memoire_Adresses_Retour_Size : Natural := 16;
50
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
48
+             Memoire_Size : Natural := 32);
51 49
     Port (CLK : STD_LOGIC;
52 50
           RST : STD_LOGIC;
53 51
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);

Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd → Processeur.srcs/sources_1/new/Etage1_LectureInstruction_NS.vhd View File

@@ -3,7 +3,7 @@
3 3
 -- Engineer: Paul Faure
4 4
 -- 
5 5
 -- Create Date: 18.04.2021 21:19:41
6
+-- Module Name: Etage1_LectureInstruction_NS - Behavioral
6 7
 -- Project Name: Processeur sécurisé
7 8
 -- Target Devices: Basys 3 ARTIX7
8 9
 -- Tool Versions: Vivado 2016.4
@@ -24,15 +24,13 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 24
 use IEEE.NUMERIC_STD.ALL;
25 25
 
26 26
 
27
-entity Etage1_LectureInstruction is
27
+entity Etage1_LectureInstruction_NS is
28 28
     Generic (Instruction_size_in_memory : Natural; -- Taille d'une instruction en mémoire (Taille d'un code instruction + 3*Taille d'un mot binaire)
29 29
              Addr_size_mem_instruction : Natural; -- Nombre de bits pour adresser la mémoire d'instruction
30 30
              Mem_instruction_size : Natural; -- Taille de la mémoire d'instruction (nombre d'instructions stockées)
31 31
              Nb_bits : Natural; -- Taille d'un mot binaire
32 32
              Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
33 33
              Nb_registres : Natural; -- Nombre de registres du processeurs
34
-             Mem_adresse_retour_size : Natural; -- Taille de la mémoire des adresses de retour (nombre d'adresse maximum) (profondeur d'appel maximale)
35
-             Adresse_size_mem_adresse_retour : Natural; -- Nombre de bits pour adresser la mémoire des adresses de retour
36 34
              Instructions_critiques_lecture_A : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande A (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeA)
37 35
              Instructions_critiques_lecture_B : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande B (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeB)
38 36
              Instructions_critiques_lecture_C : STD_LOGIC_VECTOR; -- Vecteur de bit représentant les instruction critiques sur l'opérande C (si le bit i est a un, l'instruction i lit une valeur dans le registre n°opérandeC)
@@ -58,15 +56,16 @@ entity Etage1_LectureInstruction is
58 56
     Port ( CLK : in STD_LOGIC; -- Clock
59 57
            RST : in STD_LOGIC; -- Reset
60 58
            Z : in STD_LOGIC;   -- Flag Zero de l'ALU (utile pour le JMZ)
59
+           Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
61 60
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
62 61
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
63 62
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande C
64 63
            Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie du code de l'instruction
65
-end Etage1_LectureInstruction;
64
+end Etage1_LectureInstruction_NS;
66 65
 
67 66
 
68 67
 
69
-architecture Behavioral of Etage1_LectureInstruction is
68
+architecture Behavioral of Etage1_LectureInstruction_NS is
70 69
     component MemoireInstructions is
71 70
     Generic (Nb_bits : Natural;
72 71
              Addr_size : Natural;
@@ -75,23 +74,8 @@ architecture Behavioral of Etage1_LectureInstruction is
75 74
            D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
76 75
     end component;
77 76
     
78
-    component MemoireAdressesRetour is
79
-        Generic (Nb_bits : Natural;
80
-                 Addr_size : Natural;
81
-                 Mem_size : Natural);
82
-        Port ( R : in STD_LOGIC;
83
-               W : in STD_LOGIC;
84
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
85
-               RST : in STD_LOGIC;
86
-               CLK : in STD_LOGIC;
87
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
88
-               E : out STD_LOGIC;
89
-               F : out STD_LOGIC);
90
-    end component;
91
-    
92 77
     -- Signaux pour récuperer l'instruction de la mémoire
93 78
     signal Pointeur_instruction : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
94
-    signal Pointeur_instruction_next : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (0 => '1', others => '0');
95 79
     signal Instruction_courante : STD_LOGIC_VECTOR (Instruction_size_in_memory - 1 downto 0) := (others => '0');
96 80
     
97 81
     
@@ -99,13 +83,6 @@ architecture Behavioral of Etage1_LectureInstruction is
99 83
     subtype Registre is integer range -1 to Nb_registres - 1;
100 84
     type Tab_registres is array (1 to 3) of Registre;
101 85
     signal Tableau : Tab_registres := (others => - 1);
102
-    
103
-    -- Signaux de gestion pour la mémoire des adresses de retour
104
-    signal Adresse_Retour : STD_LOGIC_VECTOR (Addr_size_mem_instruction - 1 downto 0) := (others => '0');
105
-    signal E : STD_LOGIC;
106
-    signal F : STD_LOGIC;
107
-    signal R_Aux : STD_LOGIC := '0';
108
-    signal W_Aux : STD_LOGIC := '0';
109 86
 
110 87
     -- constantes pour injecter des bulles dans le pipeline
111 88
     constant Instruction_nulle : STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0) := (others => '0');
@@ -127,21 +104,6 @@ begin
127 104
                  Mem_size => Mem_instruction_size)
128 105
     port map (Addr => Pointeur_Instruction,
129 106
               D_OUT => Instruction_courante);
130
-              
131
-    instance_MemoireAdressesRetour : MemoireAdressesRetour
132
-    generic map (Nb_bits => Addr_size_mem_instruction,
133
-                 Addr_size => Adresse_size_mem_adresse_retour,
134
-                 Mem_size => Mem_adresse_retour_size
135
-    )
136
-    port map ( R => R_Aux,
137
-               W => W_Aux,
138
-               D_IN => Pointeur_instruction_next,
139
-               RST => RST,
140
-               CLK => CLK,
141
-               D_OUT => Adresse_Retour,
142
-               E => E,
143
-               F => F
144
-    );
145 107
 
146 108
               
147 109
     process 
@@ -166,19 +128,29 @@ begin
166 128
             if (not bulles) then
167 129
                 -- S'il ne faut pas injecter de bulles ont traite l'instruction (Possible code factorisable sur ce if)
168 130
                 if ((Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_CALL) or (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMP)) then
169
-                    -- CAS PARTICULIER : CALL ou JMP, on transmet et on saute
170
-                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
131
+                    -- CAS PARTICULIER : CALL ou JMP, on transmet (en modifiant le paramètre A pour le CALL (addr de retour à stocker))et on saute
132
+                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits); -- STOCKER
171 133
                     B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
172
-                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
134
+                    A <= ((Nb_bits - 1 downto Addr_size_mem_instruction => '0') & Pointeur_Instruction) + 1;
173 135
                     Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
174 136
                     Pointeur_Instruction <= Instruction_courante (2 * Nb_bits + Addr_size_mem_instruction - 1 downto 2 * Nb_bits);
175 137
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET) then
176
-                    -- CAS PARTICULIER : RET, on transmet et on revient 
177
-                    C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
178
-                    B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
179
-                    A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
180
-                    Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
181
-                    Pointeur_Instruction <= Adresse_Retour;
138
+                    -- CAS PARTICULIER : RET, on transmet une seule fois, on attend et on revient 
139
+                    compteur <= compteur + 1;
140
+                    if (compteur = 1) then
141
+                        C <= Instruction_courante (1 * Nb_bits - 1 downto 0 * Nb_bits);
142
+                        B <= Instruction_courante (2 * Nb_bits - 1 downto 1 * Nb_bits);
143
+                        A <= Instruction_courante (3 * Nb_bits - 1 downto 2 * Nb_bits);
144
+                        Instruction <= Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits);
145
+                    elsif (compteur = 5) then
146
+                        Pointeur_Instruction <= Addr_Retour (Addr_size_mem_instruction - 1 downto 0);
147
+                        compteur <= 0;
148
+                    else 
149
+                        C <= Argument_nul;
150
+                        B <= Argument_nul;
151
+                        A <= Argument_nul;
152
+                        Instruction <= Instruction_nulle;
153
+                    end if;
182 154
                 elsif (Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_JMZ) then
183 155
                     -- CAS PARTICULIER : JMZ, on attends que l'instruction précedente arrive sur l'ALU, si le flag Zero est a un on saute, sinon on continue normalement
184 156
                     compteur <= compteur + 1;
@@ -278,12 +250,5 @@ begin
278 250
         )
279 251
     );
280 252
     
281
-    -- Gestion de l'écriture/lecture dans la mémoire des adresses de retour
282
-    R_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_Instruction_RET else
283
-             '0';
284
-    W_Aux <= '1' when Instruction_courante (Instruction_bus_size + 3 * Nb_bits - 1 downto 3 * Nb_bits) = Code_instruction_CALL else
285
-             '0';
286
-             
287
-             
288
-    Pointeur_instruction_next <= Pointeur_instruction + 1;
253
+
289 254
 end Behavioral;

Processeur.srcs/sources_1/new/Etage4_Memoire.vhd → Processeur.srcs/sources_1/new/Etage4_Memoire_NS.vhd View File

@@ -3,7 +3,7 @@
3 3
 -- Engineer: Paul Faure
4 4
 -- 
5 5
 -- Create Date: 18.04.2021 21:19:41
6
+-- Module Name: Etage4_Memoire_NS - Structural
6 7
 -- Project Name: Processeur sécurisé
7 8
 -- Target Devices: Basys 3 ARTIX7
8 9
 -- Tool Versions: Vivado 2016.4
@@ -24,13 +24,11 @@ library IEEE;
24 24
 use IEEE.STD_LOGIC_1164.ALL;
25 25
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 26
 
27
-entity Etage4_Memoire is
27
+entity Etage4_Memoire_NS is
28 28
     Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
29 29
               Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
30 30
               Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
31 31
               Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
32
-              Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
33
-              Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
34 32
               Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
35 33
               Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
36 34
               Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
@@ -44,34 +42,27 @@ entity Etage4_Memoire is
44 42
            IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
45 43
            OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
46 44
            OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
47
-           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
48
-end Etage4_Memoire;
45
+           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Sortie de l'instruction
46
+           OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); -- Sortie de l'adresse de retour vers l'étage 1
47
+end Etage4_Memoire_NS;
49 48
 
50
-architecture Structural of Etage4_Memoire is
49
+architecture Structural of Etage4_Memoire_NS is
51 50
     component MemoireDonnees is
52 51
     Generic (Nb_bits : Natural;
53 52
              Addr_size : Natural;
54 53
              Mem_size : Natural);
55
-    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0);
56
-           RW : in STD_LOGIC;
57
-           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
58
-           RST : in STD_LOGIC;
59
-           CLK : in STD_LOGIC;
60
-           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'));
61
-    end component;
62
-    
63
-    component MemoireAdressesRetour is
64
-        Generic (Nb_bits : Natural;
65
-                 Addr_size : Natural;
66
-                 Mem_size : Natural);
67
-        Port ( R : in STD_LOGIC;
68
-               W : in STD_LOGIC;
69
-               D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
70
-               RST : in STD_LOGIC;
71
-               CLK : in STD_LOGIC;
72
-               D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0');
73
-               E : out STD_LOGIC;
74
-               F : out STD_LOGIC);
54
+    Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
55
+           RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
56
+           D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
57
+           CALL : in STD_LOGIC; -- '1' -> CALL en cours
58
+           IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
59
+           IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
60
+           RET : in STD_LOGIC; -- '1' -> RET en cours
61
+           OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
62
+           OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
63
+           RST : in STD_LOGIC; -- Reset
64
+           CLK : in STD_LOGIC; -- Clock
65
+           D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire 
75 66
     end component;
76 67
     
77 68
     component LC is
@@ -94,7 +85,9 @@ architecture Structural of Etage4_Memoire is
94 85
     
95 86
     
96 87
     signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- EBP (offset à ajouter à l'adresse)
88
+    signal Last_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Ancien EBP, valeur récupérée en mémoire lors d'un RET
97 89
     signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Nouvelle valeur d'EBP, a stocker lors d'un CALL (Cf fonctionnement MemoireAdressesRetour.vhd)
90
+    signal IN_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- EBP à stocker ne mémoire (ajout de 0)
98 91
     
99 92
     signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Adresse entrante dans le composant de mémoire de donnees
100 93
     signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0'); -- Sortie du mux de choix d'adresse entre A et B
@@ -106,11 +99,9 @@ architecture Structural of Etage4_Memoire is
106 99
     
107 100
     signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0'); -- Signal interne
108 101
     
109
-    -- Signaux de la memoire de contexte
110
-    signal R_Aux : STD_LOGIC := '0';
111
-    signal W_Aux : STD_LOGIC := '0';
112
-    signal E : STD_LOGIC;
113
-    signal F : STD_LOGIC;
102
+    -- Signaux de contrôle de la mémoire
103
+    signal CALL_Aux : STD_LOGIC := '0';
104
+    signal RET_Aux : STD_LOGIC := '0';
114 105
     
115 106
     
116 107
 begin
@@ -152,27 +143,18 @@ begin
152 143
     generic map (Nb_bits => Nb_bits,
153 144
                  Addr_size => Adresse_mem_size,
154 145
                  Mem_size => Mem_size)
155
-    port map ( Addr => Addr_MemoireDonnees,
156
-               RW => Commande_MemoireDonnees(0),
157
-               D_IN => IN_B,
158
-               RST => RST,
159
-               CLK => CLK,
160
-               D_OUT => Sortie_MemoireDonnees);
161
-               
162
-    instance_MemoireEBP : MemoireAdressesRetour
163
-    generic map (Nb_bits => Adresse_mem_size,
164
-                 Addr_size => Adresse_size_mem_EBP,
165
-                 Mem_size => Mem_EBP_size
166
-    )
167
-    port map ( R => R_Aux,
168
-               W => W_Aux,
169
-               D_IN => New_EBP,
170
-               RST => RST,
171
-               CLK => CLK,
172
-               D_OUT => EBP,
173
-               E => E,
174
-               F => F
175
-    );
146
+    port map (Addr => Addr_MemoireDonnees,
147
+              RW => Commande_MemoireDonnees(0),
148
+              D_IN => IN_B,
149
+              CALL => CALL_Aux,
150
+              IN_EBP => IN_EBP,
151
+              IN_AddrRet => IN_A,
152
+              RET => RET_Aux,
153
+              OUT_EBP => Last_EBP,
154
+              OUT_AddrRet => OUT_AddrRetour,
155
+              RST => RST,
156
+              CLK => CLK,
157
+              D_OUT => Sortie_MemoireDonnees);
176 158
                  
177 159
     OUT_A <= (others => '0') when RST = '0' else
178 160
              IN_A;
@@ -181,12 +163,27 @@ begin
181 163
     OUT_Instruction <= (others => '0') when RST = '0' else
182 164
              IN_Instruction;
183 165
              
184
-    -- Controle de la mémoire de contexte (ici aussi un LC aurait été disproportionné)
185
-    R_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
166
+    -- Controle de la gestion des appels de fonctions (ici aussi un LC aurait été disproportionné)
167
+    RET_Aux <= '1' when IN_Instruction = Code_Instruction_RET else
186 168
              '0';
187
-    W_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
169
+    CALL_Aux <= '1' when IN_Instruction = Code_Instruction_CALL else
188 170
              '0';
189 171
              
172
+    process 
173
+    begin
174
+        wait until CLK'event and CLK = '1';
175
+        if (IN_Instruction = Code_Instruction_CALL) then
176
+            EBP <= New_EBP;
177
+        elsif (IN_Instruction = Code_Instruction_RET) then 
178
+            EBP <= Last_EBP (Adresse_mem_size - 1 downto 0);
179
+        elsif (RST = '0') then
180
+            EBP <= (others => '0');
181
+        end if;
182
+    end process;
183
+           
184
+   New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0) + 2;
185
+    IN_EBP <= (Nb_bits - 1 downto Adresse_mem_size => '0') & EBP;
186
+           
190 187
     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
191
-    New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
192
-end Structural;
188
+           
189
+end Structural;

+ 18
- 1
Processeur.srcs/sources_1/new/MemoireDonnees.vhd View File

@@ -23,6 +23,12 @@ entity MemoireDonnees is
23 23
     Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
24 24
            RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
25 25
            D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
26
+           CALL : in STD_LOGIC; -- '1' -> CALL en cours
27
+           IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
28
+           IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
29
+           RET : in STD_LOGIC; -- '1' -> RET en cours
30
+           OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
31
+           OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
26 32
            RST : in STD_LOGIC; -- Reset
27 33
            CLK : in STD_LOGIC; -- Clock
28 34
            D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire 
@@ -37,7 +43,12 @@ begin
37 43
         if (RST = '0') then
38 44
             MEMORY <= (others => '0');
39 45
         else 
40
-            if (RW = '0') then
46
+            if (CALL = '1') then
47
+                MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
48
+                MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
49
+            elsif (RET = '1') then
50
+                MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto ((to_integer(unsigned(Addr)) - 2) * Nb_bits)) <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr)));
51
+            elsif (RW = '0') then
41 52
                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
42 53
             end if;
43 54
         end if;
@@ -45,4 +56,10 @@ begin
45 56
     
46 57
     -- Lecture assynchrone et en permanence
47 58
     D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
59
+    
60
+    -- Sortie lors du ret en assynchrone
61
+    OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)) when (RET = '1') else 
62
+               (others => '0'); 
63
+    OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)) when (RET = '1') else 
64
+                   (others => '0');
48 65
 end Behavioral;

+ 1
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd
File diff suppressed because it is too large
View File


Processeur.srcs/sources_1/new/Pipeline.vhd → Processeur.srcs/sources_1/new/Pipeline_NS.vhd View File

@@ -4,7 +4,7 @@
4 4
 -- 
5 5
 -- Create Date: 19.04.2021 16:57:41
6 6
 -- Design Name: 
7
+-- Module Name: Pipeline_NS - Behavioral
7 8
 -- Project Name: 
8 9
 -- Target Devices: 
9 10
 -- Tool Versions: 
@@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
31 31
 --library UNISIM;
32 32
 --use UNISIM.VComponents.all;
33 33
 
34
-entity Pipeline is
34
+entity Pipeline_NS is
35 35
     Generic (Nb_bits : Natural := 8;
36 36
              Instruction_En_Memoire_Size : Natural := 29;
37 37
              Addr_Memoire_Instruction_Size : Natural := 3;
@@ -41,26 +41,22 @@ entity Pipeline is
41 41
              Nb_Registres : Natural := 16;
42 42
              Addr_registres_size : Natural := 4;
43 43
              Memoire_Size : Natural := 32;
44
-             Adresse_mem_size : Natural := 5;
45
-             Memoire_Adresses_Retour_Size : Natural := 16;
46
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
44
+             Adresse_mem_size : Natural := 5);
47 45
     Port (CLK : STD_LOGIC;
48 46
           RST : STD_LOGIC;
49 47
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
50 48
           STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
51
-end Pipeline;
49
+end Pipeline_NS;
52 50
 
53
-architecture Behavioral of Pipeline is
51
+architecture Behavioral of Pipeline_NS is
54 52
     
55
-    component Etage1_LectureInstruction is
53
+    component Etage1_LectureInstruction_NS is
56 54
     Generic (Instruction_size_in_memory : Natural;
57 55
              Addr_size_mem_instruction : Natural;
58 56
              Mem_instruction_size : Natural;
59 57
              Nb_bits : Natural;
60 58
              Instruction_bus_size : Natural;
61 59
              Nb_registres : Natural;
62
-             Mem_adresse_retour_size : Natural;
63
-             Adresse_size_mem_adresse_retour : Natural;
64 60
              Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
65 61
              Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
66 62
              Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
@@ -73,6 +69,7 @@ architecture Behavioral of Pipeline is
73 69
     Port ( CLK : in STD_LOGIC;
74 70
            RST : in STD_LOGIC;
75 71
            Z : in STD_LOGIC;
72
+           Addr_Retour : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'adresse de retour depuis l'étage 4
76 73
            A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
77 74
            B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
78 75
            C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -125,13 +122,11 @@ architecture Behavioral of Pipeline is
125 122
            C : out STD_LOGIC);
126 123
     end component;
127 124
         
128
-    component Etage4_Memoire is
125
+    component Etage4_Memoire_NS is
129 126
         Generic ( Nb_bits : Natural;
130 127
                   Mem_size : Natural;
131 128
                   Adresse_mem_size : Natural;
132 129
                   Instruction_bus_size : Natural;
133
-                  Mem_EBP_size : Natural;
134
-                  Adresse_size_mem_EBP : Natural;
135 130
                   Bits_Controle_LC : STD_LOGIC_VECTOR;
136 131
                   Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
137 132
                   Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
@@ -145,7 +140,8 @@ architecture Behavioral of Pipeline is
145 140
                IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
146 141
                OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
147 142
                OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
148
-               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
143
+               OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
144
+               OUT_AddrRetour : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0)); 
149 145
     end component;
150 146
     
151 147
     signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
@@ -180,14 +176,15 @@ architecture Behavioral of Pipeline is
180 176
     signal Z : STD_LOGIC := '0';
181 177
     signal O : STD_LOGIC := '0';
182 178
     signal C : STD_LOGIC := '0';
179
+    signal AdresseRetour : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
183 180
     
184 181
     constant Bits_Controle_MUX_2_A      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
185 182
     constant Bits_Controle_MUX_2_B      : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
186 183
     constant Bits_Controle_LC_3         : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
187 184
     constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
188
-    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
189
-    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
190
-    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
185
+    constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111"; -- LC
186
+    constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1101111110101111111111";
187
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1001111011001111111111"; -- EBP
191 188
     constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
192 189
     constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
193 190
     constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
@@ -203,15 +200,13 @@ architecture Behavioral of Pipeline is
203 200
     constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
204 201
     constant Instructions_critiques_ecriture  : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
205 202
 begin
206
-    instance_Etage1 : Etage1_LectureInstruction
203
+    instance_Etage1 : Etage1_LectureInstruction_NS
207 204
     generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
208 205
                  Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
209 206
                  Mem_instruction_size => Memoire_Instruction_Size,
210 207
                  Nb_bits => Nb_bits,
211 208
                  Instruction_bus_size => Instruction_Bus_Size,
212 209
                  Nb_registres => Nb_Registres,
213
-                 Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
214
-                 Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
215 210
                  Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
216 211
                  Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
217 212
                  Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
@@ -226,6 +221,7 @@ begin
226 221
         CLK => CLK,
227 222
         RST => RST,
228 223
         Z => Z,
224
+        Addr_Retour => AdresseRetour,
229 225
         A => A_from_1,
230 226
         B => B_from_1,
231 227
         C => C_from_1,
@@ -280,13 +276,11 @@ begin
280 276
                  C => C
281 277
     );
282 278
                       
283
-    instance_Etage4 : Etage4_Memoire
279
+    instance_Etage4 : Etage4_Memoire_NS
284 280
     generic map( Nb_bits => Nb_bits,
285 281
                  Mem_size => Memoire_Size,
286 282
                  Adresse_mem_size => Adresse_mem_size,
287 283
                  Instruction_bus_size => Instruction_Bus_Size,
288
-                 Mem_EBP_size => Memoire_Adresses_Retour_Size,
289
-                 Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
290 284
                  Bits_Controle_LC => Bits_Controle_LC_4,
291 285
                  Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
292 286
                  Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
@@ -301,7 +295,8 @@ begin
301 295
                  IN_Instruction => Instruction_to_4,
302 296
                  OUT_A => A_from_4,
303 297
                  OUT_B => B_from_4,
304
-                 OUT_Instruction => Instruction_from_4
298
+                 OUT_Instruction => Instruction_from_4,
299
+                 OUT_AddrRetour => AdresseRetour
305 300
     );
306 301
 
307 302
     process
@@ -326,3 +321,4 @@ begin
326 321
         Instruction_to_5 <= Instruction_from_4;
327 322
     end process;        
328 323
 end Behavioral;
324
+

+ 4
- 6
Processeur.srcs/sources_1/new/System.vhd View File

@@ -31,7 +31,7 @@ entity System is
31 31
 end System;
32 32
 
33 33
 architecture Structural of System is
34
-    component Pipeline is
34
+    component Pipeline_NS is
35 35
     Generic (Nb_bits : Natural := 8;
36 36
              Instruction_En_Memoire_Size : Natural := 29;
37 37
              Addr_Memoire_Instruction_Size : Natural := 3;
@@ -39,9 +39,7 @@ architecture Structural of System is
39 39
              Instruction_Bus_Size : Natural := 5;
40 40
              Nb_Instructions : Natural := 32;
41 41
              Nb_Registres : Natural := 16;
42
-             Memoire_Size : Natural := 32;
43
-             Memoire_Adresses_Retour_Size : Natural := 16;
44
-             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
42
+             Memoire_Size : Natural := 32);
45 43
     Port (CLK : STD_LOGIC;
46 44
           RST : STD_LOGIC;
47 45
           STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
@@ -57,14 +55,14 @@ architecture Structural of System is
57 55
     signal my_RST : STD_LOGIC;
58 56
     signal my_CLK : STD_LOGIC;
59 57
         
60
-begin              
58
+begin     
61 59
     -- Diviseur de clock
62 60
     clk_div : Clock_Divider
63 61
     port map (CLK_IN => CLK,
64 62
               CLK_OUT => my_CLK);
65 63
               
66 64
     -- Le processeur, augmentation de la taille de la mémoire d'instruction
67
-    instance : Pipeline
65
+    instance : Pipeline_NS
68 66
     generic map (Addr_Memoire_Instruction_Size => 8,
69 67
                  Memoire_Instruction_Size => 256)
70 68
     port map (CLK => my_CLK,

+ 7
- 7
Processeur.xpr View File

@@ -32,7 +32,7 @@
32 32
     <Option Name="EnableBDX" Val="FALSE"/>
33 33
     <Option Name="DSABoardId" Val="basys3"/>
34 34
     <Option Name="DSANumComputeUnits" Val="16"/>
35
-    <Option Name="WTXSimLaunchSim" Val="258"/>
35
+    <Option Name="WTXSimLaunchSim" Val="339"/>
36 36
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -103,37 +103,37 @@
103 103
           <Attr Name="UsedIn" Val="simulation"/>
104 104
         </FileInfo>
105 105
       </File>
106
-      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction.vhd">
106
+      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
107 107
         <FileInfo>
108 108
           <Attr Name="UsedIn" Val="synthesis"/>
109 109
           <Attr Name="UsedIn" Val="simulation"/>
110 110
         </FileInfo>
111 111
       </File>
112
-      <File Path="$PSRCDIR/sources_1/new/Etage2-5_Registres.vhd">
112
+      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
113 113
         <FileInfo>
114 114
           <Attr Name="UsedIn" Val="synthesis"/>
115 115
           <Attr Name="UsedIn" Val="simulation"/>
116 116
         </FileInfo>
117 117
       </File>
118
-      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire.vhd">
118
+      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
119 119
         <FileInfo>
120 120
           <Attr Name="UsedIn" Val="synthesis"/>
121 121
           <Attr Name="UsedIn" Val="simulation"/>
122 122
         </FileInfo>
123 123
       </File>
124
-      <File Path="$PSRCDIR/sources_1/new/Etage3_Calcul.vhd">
124
+      <File Path="$PSRCDIR/sources_1/new/Etage4_Memoire_NS.vhd">
125 125
         <FileInfo>
126 126
           <Attr Name="UsedIn" Val="synthesis"/>
127 127
           <Attr Name="UsedIn" Val="simulation"/>
128 128
         </FileInfo>
129 129
       </File>
130
-      <File Path="$PSRCDIR/sources_1/new/Pipeline.vhd">
130
+      <File Path="$PSRCDIR/sources_1/new/Pipeline_NS.vhd">
131 131
         <FileInfo>
132 132
           <Attr Name="UsedIn" Val="synthesis"/>
133 133
           <Attr Name="UsedIn" Val="simulation"/>
134 134
         </FileInfo>
135 135
       </File>
136
-      <File Path="$PSRCDIR/sources_1/new/Clock_Divider.vhd">
136
+      <File Path="$PSRCDIR/sources_1/new/Etage1_LectureInstruction_NS.vhd">
137 137
         <FileInfo>
138 138
           <Attr Name="UsedIn" Val="synthesis"/>
139 139
           <Attr Name="UsedIn" Val="simulation"/>

+ 21
- 10
SimulationsConfig/Test_Etage4_Memoire_behav.wcfg View File

@@ -30,38 +30,49 @@
30 30
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_A">
31 31
       <obj_property name="ElementShortName">my_IN_A[7:0]</obj_property>
32 32
       <obj_property name="ObjectShortName">my_IN_A[7:0]</obj_property>
33
-   </wvobject>
33
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
34 34
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_B">
35 35
       <obj_property name="ElementShortName">my_IN_B[7:0]</obj_property>
36 36
       <obj_property name="ObjectShortName">my_IN_B[7:0]</obj_property>
37
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
37 38
    </wvobject>
38 39
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_IN_Instruction">
39 40
       <obj_property name="ElementShortName">my_IN_Instruction[4:0]</obj_property>
40 41
       <obj_property name="ObjectShortName">my_IN_Instruction[4:0]</obj_property>
42
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
41 43
    </wvobject>
42 44
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_A">
43 45
       <obj_property name="ElementShortName">my_OUT_A[7:0]</obj_property>
44 46
       <obj_property name="ObjectShortName">my_OUT_A[7:0]</obj_property>
47
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
45 48
    </wvobject>
46 49
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_B">
47 50
       <obj_property name="ElementShortName">my_OUT_B[7:0]</obj_property>
48 51
       <obj_property name="ObjectShortName">my_OUT_B[7:0]</obj_property>
52
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
49 53
    </wvobject>
50 54
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_Instruction">
51 55
       <obj_property name="ElementShortName">my_OUT_Instruction[4:0]</obj_property>
52 56
       <obj_property name="ObjectShortName">my_OUT_Instruction[4:0]</obj_property>
57
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
53 58
    </wvobject>
54
-   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/Addr">
55
-      <obj_property name="ElementShortName">Addr[3:0]</obj_property>
56
-      <obj_property name="ObjectShortName">Addr[3:0]</obj_property>
59
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/my_OUT_AddrRetour">
60
+      <obj_property name="ElementShortName">my_OUT_AddrRetour[7:0]</obj_property>
61
+      <obj_property name="ObjectShortName">my_OUT_AddrRetour[7:0]</obj_property>
62
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
57 63
    </wvobject>
58
-   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/D_IN">
59
-      <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
60
-      <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
64
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/EBP">
65
+      <obj_property name="ElementShortName">EBP[3:0]</obj_property>
66
+      <obj_property name="ObjectShortName">EBP[3:0]</obj_property>
67
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
61 68
    </wvobject>
62
-   <wvobject type="logic" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/RW">
63
-      <obj_property name="ElementShortName">RW</obj_property>
64
-      <obj_property name="ObjectShortName">RW</obj_property>
69
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/Last_EBP">
70
+      <obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
71
+      <obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
72
+   </wvobject>
73
+   <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/OUT_EBP">
74
+      <obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
75
+      <obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
65 76
    </wvobject>
66 77
    <wvobject type="array" fp_name="/Test_Etage4_Memoire/instance/instance_MemoireDonnees/MEMORY">
67 78
       <obj_property name="ElementShortName">MEMORY[127:0]</obj_property>

+ 91
- 8
SimulationsConfig/Test_Pipeline_behav1.wcfg View File

@@ -10,15 +10,15 @@
10 10
       </db_ref>
11 11
    </db_ref_list>
12 12
    <zoom_setting>
13
-      <ZoomStartTime time="1000913916666fs"></ZoomStartTime>
14
-      <ZoomEndTime time="1001017216667fs"></ZoomEndTime>
15
-      <Cursor1Time time="1001000000000fs"></Cursor1Time>
13
+      <ZoomStartTime time="9750000000fs"></ZoomStartTime>
14
+      <ZoomEndTime time="10289000001fs"></ZoomEndTime>
15
+      <Cursor1Time time="10000000000fs"></Cursor1Time>
16 16
    </zoom_setting>
17 17
    <column_width_setting>
18 18
       <NameColumnWidth column_width="146"></NameColumnWidth>
19 19
       <ValueColumnWidth column_width="71"></ValueColumnWidth>
20 20
    </column_width_setting>
21
-   <WVObjectSize size="11" />
21
+   <WVObjectSize size="12" />
22 22
    <wvobject type="logic" fp_name="/Test_Pipeline/my_CLK">
23 23
       <obj_property name="ElementShortName">my_CLK</obj_property>
24 24
       <obj_property name="ObjectShortName">my_CLK</obj_property>
@@ -163,9 +163,10 @@
163 163
          <obj_property name="ObjectShortName">DATA[7:0]</obj_property>
164 164
       </wvobject>
165 165
    </wvobject>
166
-   <wvobject type="group" fp_name="group57">
166
+   <wvobject type="group" fp_name="group115">
167 167
       <obj_property name="label">Memoire</obj_property>
168 168
       <obj_property name="DisplayName">label</obj_property>
169
+      <obj_property name="isExpanded"></obj_property>
169 170
       <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/MEMORY">
170 171
          <obj_property name="ElementShortName">MEMORY[255:0]</obj_property>
171 172
          <obj_property name="ObjectShortName">MEMORY[255:0]</obj_property>
@@ -174,17 +175,99 @@
174 175
          <obj_property name="ElementShortName">D_OUT[7:0]</obj_property>
175 176
          <obj_property name="ObjectShortName">D_OUT[7:0]</obj_property>
176 177
       </wvobject>
177
-      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_IN">
178
-         <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
179
-         <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
178
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_AddrRet">
179
+         <obj_property name="ElementShortName">OUT_AddrRet[7:0]</obj_property>
180
+         <obj_property name="ObjectShortName">OUT_AddrRet[7:0]</obj_property>
181
+      </wvobject>
182
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/OUT_EBP">
183
+         <obj_property name="ElementShortName">OUT_EBP[7:0]</obj_property>
184
+         <obj_property name="ObjectShortName">OUT_EBP[7:0]</obj_property>
185
+      </wvobject>
186
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_AddrRet">
187
+         <obj_property name="ElementShortName">IN_AddrRet[7:0]</obj_property>
188
+         <obj_property name="ObjectShortName">IN_AddrRet[7:0]</obj_property>
189
+      </wvobject>
190
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/IN_EBP">
191
+         <obj_property name="ElementShortName">IN_EBP[7:0]</obj_property>
192
+         <obj_property name="ObjectShortName">IN_EBP[7:0]</obj_property>
193
+      </wvobject>
194
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/CALL">
195
+         <obj_property name="ElementShortName">CALL</obj_property>
196
+         <obj_property name="ObjectShortName">CALL</obj_property>
197
+      </wvobject>
198
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RET">
199
+         <obj_property name="ElementShortName">RET</obj_property>
200
+         <obj_property name="ObjectShortName">RET</obj_property>
180 201
       </wvobject>
181 202
       <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/Addr">
182 203
          <obj_property name="ElementShortName">Addr[4:0]</obj_property>
183 204
          <obj_property name="ObjectShortName">Addr[4:0]</obj_property>
184 205
       </wvobject>
206
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/D_IN">
207
+         <obj_property name="ElementShortName">D_IN[7:0]</obj_property>
208
+         <obj_property name="ObjectShortName">D_IN[7:0]</obj_property>
209
+      </wvobject>
185 210
       <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage4/instance_MemoireDonnees/RW">
186 211
          <obj_property name="ElementShortName">RW</obj_property>
187 212
          <obj_property name="ObjectShortName">RW</obj_property>
188 213
       </wvobject>
214
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Last_EBP">
215
+         <obj_property name="ElementShortName">Last_EBP[7:0]</obj_property>
216
+         <obj_property name="ObjectShortName">Last_EBP[7:0]</obj_property>
217
+      </wvobject>
218
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/EBP">
219
+         <obj_property name="ElementShortName">EBP[4:0]</obj_property>
220
+         <obj_property name="ObjectShortName">EBP[4:0]</obj_property>
221
+      </wvobject>
222
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees">
223
+         <obj_property name="ElementShortName">Addr_MemoireDonnees[4:0]</obj_property>
224
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees[4:0]</obj_property>
225
+      </wvobject>
226
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/IN_Addr_MemoireDonnees">
227
+         <obj_property name="ElementShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
228
+         <obj_property name="ObjectShortName">IN_Addr_MemoireDonnees[4:0]</obj_property>
229
+      </wvobject>
230
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage4/Addr_MemoireDonnees_EBP">
231
+         <obj_property name="ElementShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
232
+         <obj_property name="ObjectShortName">Addr_MemoireDonnees_EBP[4:0]</obj_property>
233
+      </wvobject>
234
+   </wvobject>
235
+   <wvobject type="group" fp_name="group121">
236
+      <obj_property name="label">Instructions</obj_property>
237
+      <obj_property name="DisplayName">label</obj_property>
238
+      <wvobject type="logic" fp_name="/Test_Pipeline/instance/instance_Etage1/Z">
239
+         <obj_property name="ElementShortName">Z</obj_property>
240
+         <obj_property name="ObjectShortName">Z</obj_property>
241
+      </wvobject>
242
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Addr_Retour">
243
+         <obj_property name="ElementShortName">Addr_Retour[7:0]</obj_property>
244
+         <obj_property name="ObjectShortName">Addr_Retour[7:0]</obj_property>
245
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
246
+      </wvobject>
247
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Pointeur_instruction">
248
+         <obj_property name="ElementShortName">Pointeur_instruction[7:0]</obj_property>
249
+         <obj_property name="ObjectShortName">Pointeur_instruction[7:0]</obj_property>
250
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
251
+      </wvobject>
252
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Instruction_courante">
253
+         <obj_property name="ElementShortName">Instruction_courante[28:0]</obj_property>
254
+         <obj_property name="ObjectShortName">Instruction_courante[28:0]</obj_property>
255
+      </wvobject>
256
+      <wvobject type="array" fp_name="/Test_Pipeline/instance/instance_Etage1/Tableau">
257
+         <obj_property name="ElementShortName">Tableau[1:3]</obj_property>
258
+         <obj_property name="ObjectShortName">Tableau[1:3]</obj_property>
259
+      </wvobject>
260
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/bulles">
261
+         <obj_property name="ElementShortName">bulles</obj_property>
262
+         <obj_property name="ObjectShortName">bulles</obj_property>
263
+      </wvobject>
264
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/compteur">
265
+         <obj_property name="ElementShortName">compteur</obj_property>
266
+         <obj_property name="ObjectShortName">compteur</obj_property>
267
+      </wvobject>
268
+      <wvobject type="other" fp_name="/Test_Pipeline/instance/instance_Etage1/locked">
269
+         <obj_property name="ElementShortName">locked</obj_property>
270
+         <obj_property name="ObjectShortName">locked</obj_property>
271
+      </wvobject>
189 272
    </wvobject>
190 273
 </wave_config>

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