Processeur/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.04.2021 13:37:04
-- Design Name: 
-- Module Name: Test_Etage4_Memoire - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Test_Etage4_Memoire is
--  Port ( );
end Test_Etage4_Memoire;

architecture Behavioral of Test_Etage4_Memoire is
    component Etage4_Memoire is
    Generic ( Nb_bits : Natural; -- Taille d'un mot binaire
              Mem_size : Natural; -- Taille de la mémoire de donnees (nombre de mots binaires stockables)
              Adresse_mem_size : Natural; -- Nombre de bits pour adresser la mémoire de donnees
              Instruction_bus_size : Natural; -- Nombre de bits du bus d'instruction (Taille d'un code instruction)
              Mem_EBP_size : Natural; -- Taille de la mémoire du contexte (profondeur d'appel maximale)
              Adresse_size_mem_EBP : Natural; -- Nombre de bits pour adresser la mémoire de contexte
              Bits_Controle_LC : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le Link Controler (cf LC.vhd)
              Bits_Controle_MUX_IN : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant A ou B comme adresse (cf MUX.vhd)
              Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer selectionnant si on doit ajouter ou non EBP à l'adresse (cf MUX.vhd)
              Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR; -- Vecteur de bit controlant le multiplexer de sortie (cf MUX.vhd)
              Code_Instruction_CALL : STD_LOGIC_VECTOR; -- Numéro de l'instruction CALL
              Code_Instruction_RET : STD_LOGIC_VECTOR); -- Numéro de l'instruction RET
    Port ( CLK : in STD_LOGIC; -- Clock
           RST : in STD_LOGIC; -- Reset
           IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande A
           IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Entrée de l'opérande B
           IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0); -- Entrée de l'instruction
           OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande A
           OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); -- Sortie de l'opérande B
           OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0)); -- Sortie de l'instruction
    end component;
    
    signal my_CLK : STD_LOGIC := '0';
    signal my_RST : STD_LOGIC := '1';
    signal my_IN_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_IN_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
    signal my_OUT_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_OUT_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal my_OUT_Instruction : STD_LOGIC_VECTOR (4 downto 0) := (others => '0');
    
    constant Bits_Controle_LC : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111001011111111111";
    constant Bits_Controle_MUX_IN : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111110101111111111";
    constant Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "1111111011001111111111";
    constant Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR (31 downto 0) := "1111111111" & "0000000001010000000000";
    
    constant Code_Instruction_CALL : STD_LOGIC_VECTOR (4 downto 0) := "10011";
    constant Code_Instruction_RET : STD_LOGIC_VECTOR (4 downto 0) := "10100";
    
    constant CLK_period : time := 10 ns;
    
begin

    instance : Etage4_Memoire
    generic map( Nb_bits => 8,
                 Mem_size => 16,
                 Adresse_mem_size => 4,
                 Instruction_bus_size => 5,
                 Mem_EBP_size => 8,
                 Adresse_size_mem_EBP => 3,
                 Bits_Controle_LC => Bits_Controle_LC,
                 Bits_Controle_MUX_IN => Bits_Controle_MUX_IN,
                 Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_IN_EBP,
                 Bits_Controle_MUX_OUT => Bits_Controle_MUX_OUT,
                 Code_Instruction_CALL => Code_Instruction_CALL,
                 Code_Instruction_RET => Code_Instruction_RET)
    port map(    CLK => my_CLK,
                 RST => my_RST,
                 IN_A => my_IN_A,
                 IN_B => my_IN_B,
                 IN_Instruction => my_IN_Instruction,
                 OUT_A => my_OUT_A,
                 OUT_B => my_OUT_B,
                 OUT_Instruction => my_OUT_Instruction,
                 OUT_AddrRetour => my_OUT_AddrRetour);
    
    CLK_process :process
    begin
        my_CLK <= '0';
        wait for CLK_period/2;
        my_CLK <= '1';
        wait for CLK_period/2;
    end process;
    
    process 
    begin     
        my_IN_A <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
        my_IN_B <= "00000000" after 0 ns, "00000001" after 4 ns, "00000010" after 14 ns;
        my_IN_Instruction <= "00000" after 0 ns, "01011" after 4 ns, "01011" after 14 ns;
        my_RST <= '0' after 125 ns;
        wait;
    end process;    
end Behavioral;