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MemoireDonnees.vhd 3.5KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company: INSA-Toulouse
  3. -- Engineer: Paul Faure
  4. --
  5. -- Create Date: 16.04.2021 14:35:04
  6. -- Module Name: MemoireDonnees - Behavioral
  7. -- Project Name: Processeur sécurisé
  8. -- Target Devices: Basys 3 ARTIX7
  9. -- Tool Versions: Vivado 2016.4
  10. -- Description: Memoire des donnees utilisateur
  11. --
  12. -- Dependencies: None
  13. ----------------------------------------------------------------------------------
  14. library IEEE;
  15. use IEEE.STD_LOGIC_1164.ALL;
  16. use IEEE.NUMERIC_STD.ALL;
  17. entity MemoireDonnees is
  18. Generic (Nb_bits : Natural; -- Taille d'un mot en mémoire
  19. Addr_size : Natural; -- Nombre de bits nécessaires a l'adressage de la mémoire
  20. Mem_size : Natural); -- Nombre de mot stockables
  21. Port ( Addr : in STD_LOGIC_VECTOR (Addr_size-1 downto 0); -- L'adresse a laquelle il faut agir
  22. RW : in STD_LOGIC; -- Ce qu'il faut faire ('1' -> Read, '0' -> Write)
  23. D_IN : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Data a ecrire (si RW = 0)
  24. CALL : in STD_LOGIC; -- '1' -> CALL en cours
  25. IN_EBP : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'EBP à stocker en cas de CALL
  26. IN_AddrRet : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0); -- Valeur d'@ de retour à stocker en cas de CALL
  27. RET : in STD_LOGIC; -- '1' -> RET en cours
  28. OUT_EBP : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'EBP à renvoyer en cas de RET
  29. OUT_AddrRet : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0'); -- Valeur d'@ de retour à renvoyer en cas de RET
  30. RST : in STD_LOGIC; -- Reset
  31. CLK : in STD_LOGIC; -- Clock
  32. D_OUT : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0) := (others => '0')); -- Sortie de la mémoire
  33. end MemoireDonnees;
  34. architecture Behavioral of MemoireDonnees is
  35. signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := (others => '0'); -- Buffer pour la mémoire
  36. begin
  37. process
  38. begin
  39. wait until CLK'event and CLK = '1';
  40. if (RST = '0') then
  41. MEMORY <= (others => '0');
  42. else
  43. if (CALL = '1') then
  44. MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= IN_EBP;
  45. MEMORY (((to_integer(unsigned(Addr)) + 2) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) + 1)) <= IN_AddrRet;
  46. elsif (RET = '1') then
  47. MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto ((to_integer(unsigned(Addr)) - 2) * Nb_bits)) <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr)));
  48. elsif (RW = '0') then
  49. MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
  50. end if;
  51. end if;
  52. end process;
  53. -- Lecture assynchrone et en permanence
  54. D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
  55. -- Sortie lors du ret en assynchrone
  56. OUT_EBP <= MEMORY (((to_integer(unsigned(Addr)) - 1) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 2)) when (RET = '1') else
  57. (others => '0');
  58. OUT_AddrRet <= MEMORY ((to_integer(unsigned(Addr)) * Nb_bits - 1) downto Nb_bits * (to_integer(unsigned(Addr)) - 1)) when (RET = '1') else
  59. (others => '0');
  60. end Behavioral;