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Test_Pipeline.vhd 2.6KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 19.04.2021 17:35:57
  6. -- Design Name:
  7. -- Module Name: Test_Pipeline - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity Test_Pipeline is
  30. -- Port ( );
  31. end Test_Pipeline;
  32. architecture Behavioral of Test_Pipeline is
  33. component Pipeline is
  34. Generic (Nb_bits : Natural := 8;
  35. Instruction_En_Memoire_Size : Natural := 29;
  36. Addr_Memoire_Instruction_Size : Natural := 3;
  37. Memoire_Instruction_Size : Natural := 8;
  38. Instruction_Bus_Size : Natural := 5;
  39. Nb_Instructions : Natural := 32;
  40. Nb_Registres : Natural := 16;
  41. Memoire_Size : Natural := 32);
  42. Port (CLK : STD_LOGIC;
  43. RST : STD_LOGIC;
  44. STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  45. STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
  46. end component;
  47. signal my_CLK : STD_LOGIC := '0';
  48. signal my_RST : STD_LOGIC := '1';
  49. signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
  50. signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
  51. constant CLK_period : time := 10 ns;
  52. begin
  53. instance : Pipeline
  54. generic map (Addr_Memoire_Instruction_Size => 8,
  55. Memoire_Instruction_Size => 256)
  56. port map (CLK => my_CLK,
  57. RST => my_RST,
  58. STD_IN => my_STD_IN,
  59. STD_OUT => my_STD_OUT);
  60. CLK_process :process
  61. begin
  62. my_CLK <= '1';
  63. wait for CLK_period/2;
  64. my_CLK <= '0';
  65. wait for CLK_period/2;
  66. end process;
  67. process
  68. begin
  69. my_STD_IN <= "00000001" after 2600 ns, "00000010" after 5600 ns, "00000011" after 8600 ns, "00000100" after 11600 ns, "00000101" after 14600 ns, "00000110" after 17600 ns, "00000111" after 20600 ns, "00001000" after 23600 ns, "00001001" after 26600 ns, "00000000" after 29600 ns;
  70. wait;
  71. end process;
  72. end Behavioral;