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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 19.04.2021 17:35:57
- -- Design Name:
- -- Module Name: Test_Pipeline - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
-
-
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
-
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
-
- entity Test_Pipeline is
- -- Port ( );
- end Test_Pipeline;
-
- architecture Behavioral of Test_Pipeline is
-
- component Pipeline is
- Generic (Nb_bits : Natural := 8;
- Instruction_En_Memoire_Size : Natural := 29;
- Addr_Memoire_Instruction_Size : Natural := 3;
- Memoire_Instruction_Size : Natural := 8;
- Instruction_Bus_Size : Natural := 5;
- Nb_Instructions : Natural := 32;
- Nb_Registres : Natural := 16;
- Memoire_Size : Natural := 32);
- Port (CLK : STD_LOGIC;
- RST : STD_LOGIC;
- STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
- STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
- end component;
-
- signal my_CLK : STD_LOGIC := '0';
- signal my_RST : STD_LOGIC := '1';
- signal my_STD_IN : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
- signal my_STD_OUT : STD_LOGIC_VECTOR (8 - 1 downto 0) := (others => '0');
-
- constant CLK_period : time := 10 ns;
-
- begin
- instance : Pipeline
- generic map (Addr_Memoire_Instruction_Size => 8,
- Memoire_Instruction_Size => 256)
- port map (CLK => my_CLK,
- RST => my_RST,
- STD_IN => my_STD_IN,
- STD_OUT => my_STD_OUT);
-
- CLK_process :process
- begin
- my_CLK <= '1';
- wait for CLK_period/2;
- my_CLK <= '0';
- wait for CLK_period/2;
- end process;
-
- process
- begin
- my_STD_IN <= "00000001" after 2600 ns, "00000010" after 5600 ns, "00000011" after 8600 ns, "00000100" after 11600 ns, "00000101" after 14600 ns, "00000110" after 17600 ns, "00000111" after 20600 ns, "00001000" after 23600 ns, "00001001" after 26600 ns, "00000000" after 29600 ns;
- wait;
- end process;
- end Behavioral;
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