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Nettoyage

Paul Faure 5 months ago
parent
commit
792c78c136
92 changed files with 1 additions and 10311 deletions
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@@ -3,3 +3,4 @@ Compteur8BitsBasys3.cache/*
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-<!--The data in this file is primarily intended for consumption by Xilinx tools.
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-This means code written to parse this file will need to be revisited each subsequent release.-->
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-<application name="pa" timeStamp="Fri Apr 09 23:28:53 2021">
7
-<section name="Project Information" visible="false">
8
-<property name="ProjectID" value="f5d1f37f0c514482aeb99b8a58e27639" type="ProjectID"/>
9
-<property name="ProjectIteration" value="3" type="ProjectIteration"/>
10
-</section>
11
-<section name="PlanAhead Usage" visible="true">
12
-<item name="Project Data">
13
-<property name="SrcSetCount" value="1" type="SrcSetCount"/>
14
-<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
15
-<property name="DesignMode" value="RTL" type="DesignMode"/>
16
-<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
17
-<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
18
-</item>
19
-<item name="Java Command Handlers">
20
-<property name="AutoConnectTarget" value="1" type="JavaHandler"/>
21
-<property name="LaunchProgramFpga" value="1" type="JavaHandler"/>
22
-<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
23
-<property name="RunBitgen" value="1" type="JavaHandler"/>
24
-<property name="RunImplementation" value="1" type="JavaHandler"/>
25
-<property name="RunSynthesis" value="1" type="JavaHandler"/>
26
-<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
27
-</item>
28
-<item name="Gui Resources Info">
29
-<property name="BaseDialog_OK" value="6" type="GuiResourceData"/>
30
-<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiResourceData"/>
31
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiResourceData"/>
32
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="2" type="GuiResourceData"/>
33
-<property name="PACommandNames_AUTO_CONNECT_TARGET" value="1" type="GuiResourceData"/>
34
-<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiResourceData"/>
35
-<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiResourceData"/>
36
-<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiResourceData"/>
37
-<property name="ProgramDebugTab_PROGRAM_DEVICE" value="1" type="GuiResourceData"/>
38
-<property name="ProgramFpgaDialog_PROGRAM" value="1" type="GuiResourceData"/>
39
-<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiResourceData"/>
40
-</item>
41
-<item name="Other">
42
-<property name="GuiMode" value="4" type="GuiMode"/>
43
-<property name="BatchMode" value="0" type="BatchMode"/>
44
-<property name="TclMode" value="3" type="TclMode"/>
45
-</item>
46
-</section>
47
-</application>
48
-</document>

+ 0
- 8
proj/GPIO.hw/GPIO.lpr View File

@@ -1,8 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
3
-<!--                                                              -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
5
-
6
-<labtools version="1" minor="0">
7
-  <HWSession Dir="hw_1" File="hw.xml"/>
8
-</labtools>

+ 0
- 15
proj/GPIO.hw/hw_1/hw.xml View File

@@ -1,15 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)                     -->
3
-<!--                                                              -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.        -->
5
-
6
-<hwsession version="1" minor="2">
7
-  <device name="xc7a35t_0" gui_info=""/>
8
-  <ObjectList object_type="hw_device" gui_info="">
9
-    <Object name="xc7a35t_0" gui_info="">
10
-      <Properties Property="PROBES.FILE" value=""/>
11
-      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name__demo.bit"/>
12
-    </Object>
13
-  </ObjectList>
14
-  <probeset name="hw project" active="false"/>
15
-</hwsession>

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_1.xml View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="synth_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
4
-</Runs>
5
-

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_2.xml View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
4
-</Runs>
5
-

+ 0
- 5
proj/GPIO.runs/.jobs/vrs_config_3.xml View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<Runs Version="1" Minor="0">
3
-	<Run Id="impl_1" LaunchDir="C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
4
-</Runs>
5
-

+ 0
- 0
proj/GPIO.runs/impl_1/.Vivado_Implementation.queue.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.init_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.init_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.opt_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.opt_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.place_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.place_design.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.route_design.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="960">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.route_design.end.rst View File


+ 0
- 10
proj/GPIO.runs/impl_1/.vivado.begin.rst View File

@@ -1,10 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="2772">
4
-    </Process>
5
-</ProcessHandle>
6
-<?xml version="1.0"?>
7
-<ProcessHandle Version="1" Minor="0">
8
-    <Process Command="vivado.bat" Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="12740">
9
-    </Process>
10
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.vivado.end.rst View File


+ 0
- 5
proj/GPIO.runs/impl_1/.write_bitstream.begin.rst View File

@@ -1,5 +0,0 @@
1
-<?xml version="1.0"?>
2
-<ProcessHandle Version="1" Minor="0">
3
-    <Process Command=".planAhead." Owner="Hp" Host="DESKTOP-GN6T5R2" Pid="1988">
4
-    </Process>
5
-</ProcessHandle>

+ 0
- 0
proj/GPIO.runs/impl_1/.write_bitstream.end.rst View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo.bit View File


+ 0
- 67
proj/GPIO.runs/impl_1/GPIO_demo.tcl View File

@@ -1,67 +0,0 @@
1
-proc start_step { step } {
2
-  set stopFile ".stop.rst"
3
-  if {[file isfile .stop.rst]} {
4
-    puts ""
5
-    puts "*** Halting run - EA reset detected ***"
6
-    puts ""
7
-    puts ""
8
-    return -code error
9
-  }
10
-  set beginFile ".$step.begin.rst"
11
-  set platform "$::tcl_platform(platform)"
12
-  set user "$::tcl_platform(user)"
13
-  set pid [pid]
14
-  set host ""
15
-  if { [string equal $platform unix] } {
16
-    if { [info exist ::env(HOSTNAME)] } {
17
-      set host $::env(HOSTNAME)
18
-    }
19
-  } else {
20
-    if { [info exist ::env(COMPUTERNAME)] } {
21
-      set host $::env(COMPUTERNAME)
22
-    }
23
-  }
24
-  set ch [open $beginFile w]
25
-  puts $ch "<?xml version=\"1.0\"?>"
26
-  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
27
-  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
28
-  puts $ch "    </Process>"
29
-  puts $ch "</ProcessHandle>"
30
-  close $ch
31
-}
32
-
33
-proc end_step { step } {
34
-  set endFile ".$step.end.rst"
35
-  set ch [open $endFile w]
36
-  close $ch
37
-}
38
-
39
-proc step_failed { step } {
40
-  set endFile ".$step.error.rst"
41
-  set ch [open $endFile w]
42
-  close $ch
43
-}
44
-
45
-set_msg_config -id {HDL 9-1061} -limit 100000
46
-set_msg_config -id {HDL 9-1654} -limit 100000
47
-
48
-start_step write_bitstream
49
-set ACTIVE_STEP write_bitstream
50
-set rc [catch {
51
-  create_msg_db write_bitstream.pb
52
-  open_checkpoint GPIO_demo_routed.dcp
53
-  set_property webtalk.parent_dir C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.cache/wt [current_project]
54
-  catch { write_mem_info -force GPIO_demo.mmi }
55
-  write_bitstream -force -no_partial_bitfile GPIO_demo.bit 
56
-  catch { write_sysdef -hwdef GPIO_demo.hwdef -bitfile GPIO_demo.bit -meminfo GPIO_demo.mmi -file GPIO_demo.sysdef }
57
-  catch {write_debug_probes -quiet -force debug_nets}
58
-  close_msg_db -file write_bitstream.pb
59
-} RESULT]
60
-if {$rc} {
61
-  step_failed write_bitstream
62
-  return -code error $RESULT
63
-} else {
64
-  end_step write_bitstream
65
-  unset ACTIVE_STEP 
66
-}
67
-

+ 0
- 475
proj/GPIO.runs/impl_1/GPIO_demo.vdi View File

@@ -1,475 +0,0 @@
1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Design is defaulting to srcset: sources_1
14
-Design is defaulting to constrset: constrs_1
15
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
16
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
17
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
18
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
19
-INFO: [Project 1-570] Preparing netlist for logic optimization
20
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
22
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
23
-INFO: [Project 1-111] Unisim Transformation Summary:
24
-  A total of 2 instances were transformed.
25
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
26
-
27
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
28
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
29
-Command: opt_design -directive RuntimeOptimized
30
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
31
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
32
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
33
-Running DRC as a precondition to command opt_design
34
-
35
-Starting DRC Task
36
-INFO: [DRC 23-27] Running DRC with 2 threads
37
-INFO: [Project 1-461] DRC finished with 0 Errors
38
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
39
-
40
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
41
-
42
-Starting Logic Optimization Task
43
-Implement Debug Cores | Checksum: 11fc7498c
44
-INFO: [Timing 38-35] Done setting XDC timing constraints.
45
-INFO: [Timing 38-2] Deriving generated clocks
46
-
47
-Phase 1 Retarget
48
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
49
-INFO: [Opt 31-49] Retargeted 0 cell(s).
50
-Phase 1 Retarget | Checksum: 16f269fca
51
-
52
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
53
-
54
-Phase 2 Constant propagation
55
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
56
-INFO: [Opt 31-10] Eliminated 6 cells.
57
-Phase 2 Constant propagation | Checksum: 233a26f9e
58
-
59
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
60
-
61
-Phase 3 Sweep
62
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
63
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
64
-Phase 3 Sweep | Checksum: 1bb596469
65
-
66
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
67
-
68
-Phase 4 BUFG optimization
69
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
70
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
71
-Phase 4 BUFG optimization | Checksum: 1bb596469
72
-
73
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
74
-
75
-Starting Connectivity Check Task
76
-
77
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
78
-Ending Logic Optimization Task | Checksum: 1bb596469
79
-
80
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
81
-INFO: [Common 17-83] Releasing license: Implementation
82
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
83
-opt_design completed successfully
84
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
85
-Writing placer database...
86
-Writing XDEF routing.
87
-Writing XDEF routing logical nets.
88
-Writing XDEF routing special nets.
89
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
90
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
91
-INFO: [DRC 23-27] Running DRC with 2 threads
92
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
93
-INFO: [Chipscope 16-241] No debug cores found in the current design.
94
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
95
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
96
-Command: place_design -directive RuntimeOptimized
97
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
99
-INFO: [DRC 23-27] Running DRC with 2 threads
100
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
101
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
102
-Running DRC as a precondition to command place_design
103
-INFO: [DRC 23-27] Running DRC with 2 threads
104
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
105
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
106
-
107
-Starting Placer Task
108
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
109
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
110
-
111
-Phase 1 Placer Initialization
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
114
-
115
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
116
-INFO: [Timing 38-35] Done setting XDC timing constraints.
117
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
118
-
119
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
120
-
121
-Phase 1.2 Build Placer Netlist Model
122
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
123
-
124
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
125
-
126
-Phase 1.3 Constrain Clocks/Macros
127
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
128
-
129
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
130
-Phase 1 Placer Initialization | Checksum: f331096b
131
-
132
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
133
-
134
-Phase 2 Global Placement
135
-Phase 2 Global Placement | Checksum: 7e244a0f
136
-
137
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
138
-
139
-Phase 3 Detail Placement
140
-
141
-Phase 3.1 Commit Multi Column Macros
142
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
143
-
144
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
145
-
146
-Phase 3.2 Commit Most Macros & LUTRAMs
147
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
148
-
149
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
150
-
151
-Phase 3.3 Area Swap Optimization
152
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
153
-
154
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
155
-
156
-Phase 3.4 Pipeline Register Optimization
157
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
158
-
159
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
160
-
161
-Phase 3.5 Timing Path Optimizer
162
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
163
-
164
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
165
-
166
-Phase 3.6 Small Shape Detail Placement
167
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
168
-
169
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
170
-
171
-Phase 3.7 Re-assign LUT pins
172
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
173
-
174
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
175
-
176
-Phase 3.8 Pipeline Register Optimization
177
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
178
-
179
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
180
-Phase 3 Detail Placement | Checksum: 1c30709cd
181
-
182
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
183
-
184
-Phase 4 Post Placement Optimization and Clean-Up
185
-
186
-Phase 4.1 Post Commit Optimization
187
-INFO: [Timing 38-35] Done setting XDC timing constraints.
188
-
189
-Phase 4.1.1 Post Placement Optimization
190
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
191
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
192
-
193
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
194
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
195
-
196
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
197
-
198
-Phase 4.2 Post Placement Cleanup
199
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
200
-
201
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
202
-
203
-Phase 4.3 Placer Reporting
204
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
205
-
206
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
207
-
208
-Phase 4.4 Final Placement Cleanup
209
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
210
-
211
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
212
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
213
-
214
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
215
-Ending Placer Task | Checksum: dd20239e
216
-
217
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
218
-INFO: [Common 17-83] Releasing license: Implementation
219
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
220
-place_design completed successfully
221
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
222
-Writing placer database...
223
-Writing XDEF routing.
224
-Writing XDEF routing logical nets.
225
-Writing XDEF routing special nets.
226
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
227
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
228
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
231
-Command: route_design -directive RuntimeOptimized
232
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
233
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
234
-Running DRC as a precondition to command route_design
235
-INFO: [DRC 23-27] Running DRC with 2 threads
236
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
237
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
238
-
239
-
240
-Starting Routing Task
241
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
242
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
243
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
244
-
245
-Phase 1 Build RT Design
246
-Phase 1 Build RT Design | Checksum: be9a9a9a
247
-
248
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
249
-
250
-Phase 2 Router Initialization
251
-
252
-Phase 2.1 Create Timer
253
-Phase 2.1 Create Timer | Checksum: be9a9a9a
254
-
255
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
256
-
257
-Phase 2.2 Fix Topology Constraints
258
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
259
-
260
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
261
-
262
-Phase 2.3 Pre Route Cleanup
263
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
264
-
265
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
266
- Number of Nodes with overlaps = 0
267
-
268
-Phase 2.4 Update Timing
269
-Phase 2.4 Update Timing | Checksum: 111c71c3e
270
-
271
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
272
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
273
-
274
-Phase 2 Router Initialization | Checksum: 1ee683561
275
-
276
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
277
-
278
-Phase 3 Initial Routing
279
-Phase 3 Initial Routing | Checksum: 10e02a291
280
-
281
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
282
-
283
-Phase 4 Rip-up And Reroute
284
-
285
-Phase 4.1 Global Iteration 0
286
- Number of Nodes with overlaps = 107
287
- Number of Nodes with overlaps = 0
288
-
289
-Phase 4.1.1 Update Timing
290
-Phase 4.1.1 Update Timing | Checksum: da308246
291
-
292
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
293
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
294
-
295
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
296
-
297
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
298
-
299
-Phase 4.2 Global Iteration 1
300
- Number of Nodes with overlaps = 1
301
- Number of Nodes with overlaps = 0
302
-
303
-Phase 4.2.1 Update Timing
304
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
305
-
306
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
307
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
308
-
309
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
310
-
311
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
312
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
313
-
314
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
315
-
316
-Phase 5 Delay and Skew Optimization
317
-
318
-Phase 5.1 Delay CleanUp
319
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
320
-
321
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
322
-
323
-Phase 5.2 Clock Skew Optimization
324
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
325
-
326
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
327
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
328
-
329
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
330
-
331
-Phase 6 Post Hold Fix
332
-
333
-Phase 6.1 Hold Fix Iter
334
-
335
-Phase 6.1.1 Update Timing
336
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
337
-
338
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
339
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
340
-
341
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
342
-
343
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
344
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
345
-
346
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
347
-
348
-Phase 7 Route finalize
349
-
350
-Router Utilization Summary
351
-  Global Vertical Routing Utilization    = 0.234075 %
352
-  Global Horizontal Routing Utilization  = 0.228267 %
353
-  Routable Net Status*
354
-  *Does not include unroutable nets such as driverless and loadless.
355
-  Run report_route_status for detailed report.
356
-  Number of Failed Nets               = 0
357
-  Number of Unrouted Nets             = 0
358
-  Number of Partially Routed Nets     = 0
359
-  Number of Node Overlaps             = 0
360
-
361
-Phase 7 Route finalize | Checksum: 1af3f3601
362
-
363
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
364
-
365
-Phase 8 Verifying routed nets
366
-
367
- Verification completed successfully
368
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
369
-
370
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
371
-
372
-Phase 9 Depositing Routes
373
-Phase 9 Depositing Routes | Checksum: 15d59118d
374
-
375
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
376
-
377
-Phase 10 Post Router Timing
378
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
379
-
380
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
381
-Phase 10 Post Router Timing | Checksum: 15d59118d
382
-
383
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
384
-INFO: [Route 35-16] Router Completed Successfully
385
-
386
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
387
-
388
-Routing Is Done.
389
-INFO: [Common 17-83] Releasing license: Implementation
390
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
391
-route_design completed successfully
392
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
393
-Writing placer database...
394
-Writing XDEF routing.
395
-Writing XDEF routing logical nets.
396
-Writing XDEF routing special nets.
397
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
398
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
399
-INFO: [DRC 23-27] Running DRC with 2 threads
400
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
401
-INFO: [Timing 38-35] Done setting XDC timing constraints.
402
-INFO: [DRC 23-133] Running Methodology with 2 threads
403
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
404
-INFO: [Timing 38-35] Done setting XDC timing constraints.
405
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
406
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
407
-INFO: [Timing 38-35] Done setting XDC timing constraints.
408
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
409
-Running Vector-less Activity Propagation...
410
-
411
-Finished Running Vector-less Activity Propagation
412
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
413
-report_power completed successfully
414
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...
415
-#-----------------------------------------------------------
416
-# Vivado v2016.4 (64-bit)
417
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
418
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
419
-# Start of session at: Fri Apr 09 23:19:20 2021
420
-# Process ID: 1988
421
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
422
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
423
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
424
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
425
-#-----------------------------------------------------------
426
-source GPIO_demo.tcl -notrace
427
-Command: open_checkpoint GPIO_demo_routed.dcp
428
-
429
-Starting open_checkpoint Task
430
-
431
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 215.074 ; gain = 0.000
432
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
433
-INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
434
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
435
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
436
-INFO: [Project 1-570] Preparing netlist for logic optimization
437
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
438
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo_early.xdc]
439
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
440
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/.Xil/Vivado-1988-DESKTOP-GN6T5R2/dcp/GPIO_demo.xdc]
441
-Reading XDEF placement.
442
-Reading placer database...
443
-Reading XDEF routing.
444
-Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
445
-Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
446
-Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 528.973 ; gain = 0.000
447
-INFO: [Project 1-111] Unisim Transformation Summary:
448
-  A total of 2 instances were transformed.
449
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
450
-
451
-INFO: [Project 1-604] Checkpoint was created with Vivado v2016.4 (64-bit) build 1756540
452
-open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 528.973 ; gain = 318.734
453
-Command: write_bitstream -force -no_partial_bitfile GPIO_demo.bit
454
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
455
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
456
-Running DRC as a precondition to command write_bitstream
457
-INFO: [DRC 23-27] Running DRC with 2 threads
458
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
459
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
460
-Loading data files...
461
-Loading site data...
462
-Loading route data...
463
-Processing options...
464
-Creating bitmap...
465
-Creating bitstream...
466
-Bitstream compression saved 13383552 bits.
467
-Writing bitstream ./GPIO_demo.bit...
468
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
469
-INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
470
-INFO: [Common 17-83] Releasing license: Implementation
471
-14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
472
-write_bitstream completed successfully
473
-write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 965.129 ; gain = 436.156
474
-INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file GPIO_demo.hwdef
475
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:19:56 2021...

+ 0
- 414
proj/GPIO.runs/impl_1/GPIO_demo_960.backup.vdi View File

@@ -1,414 +0,0 @@
1
-#-----------------------------------------------------------
2
-# Vivado v2016.4 (64-bit)
3
-# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4
-# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Fri Apr 09 23:15:32 2021
6
-# Process ID: 960
7
-# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1
8
-# Command line: vivado.exe -log GPIO_demo.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source GPIO_demo.tcl -notrace
9
-# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo.vdi
10
-# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1\vivado.jou
11
-#-----------------------------------------------------------
12
-source GPIO_demo.tcl -notrace
13
-Design is defaulting to srcset: sources_1
14
-Design is defaulting to constrset: constrs_1
15
-INFO: [Netlist 29-17] Analyzing 156 Unisim elements for replacement
16
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
17
-INFO: [Project 1-479] Netlist was created with Vivado 2016.4
18
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
19
-INFO: [Project 1-570] Preparing netlist for logic optimization
20
-Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
21
-Finished Parsing XDC File [C:/Users/Hp/Documents/Compteur8BitsBasys3/src/constraints/Basys3_Master.xdc]
22
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
23
-INFO: [Project 1-111] Unisim Transformation Summary:
24
-  A total of 2 instances were transformed.
25
-  IOBUF => IOBUF (IBUF, OBUFT): 2 instances
26
-
27
-link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 528.871 ; gain = 255.074
28
-INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
29
-Command: opt_design -directive RuntimeOptimized
30
-INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
31
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
32
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
33
-Running DRC as a precondition to command opt_design
34
-
35
-Starting DRC Task
36
-INFO: [DRC 23-27] Running DRC with 2 threads
37
-INFO: [Project 1-461] DRC finished with 0 Errors
38
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
39
-
40
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 539.426 ; gain = 10.555
41
-
42
-Starting Logic Optimization Task
43
-Implement Debug Cores | Checksum: 11fc7498c
44
-INFO: [Timing 38-35] Done setting XDC timing constraints.
45
-INFO: [Timing 38-2] Deriving generated clocks
46
-
47
-Phase 1 Retarget
48
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
49
-INFO: [Opt 31-49] Retargeted 0 cell(s).
50
-Phase 1 Retarget | Checksum: 16f269fca
51
-
52
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
53
-
54
-Phase 2 Constant propagation
55
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
56
-INFO: [Opt 31-10] Eliminated 6 cells.
57
-Phase 2 Constant propagation | Checksum: 233a26f9e
58
-
59
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
60
-
61
-Phase 3 Sweep
62
-INFO: [Opt 31-12] Eliminated 363 unconnected nets.
63
-INFO: [Opt 31-11] Eliminated 2 unconnected cells.
64
-Phase 3 Sweep | Checksum: 1bb596469
65
-
66
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
67
-
68
-Phase 4 BUFG optimization
69
-INFO: [Opt 31-12] Eliminated 0 unconnected nets.
70
-INFO: [Opt 31-11] Eliminated 0 unconnected cells.
71
-Phase 4 BUFG optimization | Checksum: 1bb596469
72
-
73
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
74
-
75
-Starting Connectivity Check Task
76
-
77
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1040.055 ; gain = 0.000
78
-Ending Logic Optimization Task | Checksum: 1bb596469
79
-
80
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1040.055 ; gain = 500.629
81
-INFO: [Common 17-83] Releasing license: Implementation
82
-24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
83
-opt_design completed successfully
84
-opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1040.055 ; gain = 511.184
85
-Writing placer database...
86
-Writing XDEF routing.
87
-Writing XDEF routing logical nets.
88
-Writing XDEF routing special nets.
89
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1040.055 ; gain = 0.000
90
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp' has been generated.
91
-INFO: [DRC 23-27] Running DRC with 2 threads
92
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt.
93
-INFO: [Chipscope 16-241] No debug cores found in the current design.
94
-Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
95
-or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
96
-Command: place_design -directive RuntimeOptimized
97
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
98
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
99
-INFO: [DRC 23-27] Running DRC with 2 threads
100
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
101
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
102
-Running DRC as a precondition to command place_design
103
-INFO: [DRC 23-27] Running DRC with 2 threads
104
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
105
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
106
-
107
-Starting Placer Task
108
-INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive.
109
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
110
-
111
-Phase 1 Placer Initialization
112
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1040.055 ; gain = 0.000
113
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1040.055 ; gain = 0.000
114
-
115
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device
116
-INFO: [Timing 38-35] Done setting XDC timing constraints.
117
-Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6c035595
118
-
119
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
120
-
121
-Phase 1.2 Build Placer Netlist Model
122
-Phase 1.2 Build Placer Netlist Model | Checksum: f331096b
123
-
124
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
125
-
126
-Phase 1.3 Constrain Clocks/Macros
127
-Phase 1.3 Constrain Clocks/Macros | Checksum: f331096b
128
-
129
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
130
-Phase 1 Placer Initialization | Checksum: f331096b
131
-
132
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1066.777 ; gain = 26.723
133
-
134
-Phase 2 Global Placement
135
-Phase 2 Global Placement | Checksum: 7e244a0f
136
-
137
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
138
-
139
-Phase 3 Detail Placement
140
-
141
-Phase 3.1 Commit Multi Column Macros
142
-Phase 3.1 Commit Multi Column Macros | Checksum: 7e244a0f
143
-
144
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
145
-
146
-Phase 3.2 Commit Most Macros & LUTRAMs
147
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b64b4a8a
148
-
149
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
150
-
151
-Phase 3.3 Area Swap Optimization
152
-Phase 3.3 Area Swap Optimization | Checksum: 2008e72ab
153
-
154
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
155
-
156
-Phase 3.4 Pipeline Register Optimization
157
-Phase 3.4 Pipeline Register Optimization | Checksum: 2008e72ab
158
-
159
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1066.777 ; gain = 26.723
160
-
161
-Phase 3.5 Timing Path Optimizer
162
-Phase 3.5 Timing Path Optimizer | Checksum: 1b836a822
163
-
164
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
165
-
166
-Phase 3.6 Small Shape Detail Placement
167
-Phase 3.6 Small Shape Detail Placement | Checksum: 1158460e2
168
-
169
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
170
-
171
-Phase 3.7 Re-assign LUT pins
172
-Phase 3.7 Re-assign LUT pins | Checksum: 1c30709cd
173
-
174
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
175
-
176
-Phase 3.8 Pipeline Register Optimization
177
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c30709cd
178
-
179
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
180
-Phase 3 Detail Placement | Checksum: 1c30709cd
181
-
182
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
183
-
184
-Phase 4 Post Placement Optimization and Clean-Up
185
-
186
-Phase 4.1 Post Commit Optimization
187
-INFO: [Timing 38-35] Done setting XDC timing constraints.
188
-
189
-Phase 4.1.1 Post Placement Optimization
190
-INFO: [Place 30-746] Post Placement Timing Summary WNS=4.240. For the most accurate timing information please run report_timing.
191
-Phase 4.1.1 Post Placement Optimization | Checksum: 1ae2aa603
192
-
193
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
194
-Phase 4.1 Post Commit Optimization | Checksum: 1ae2aa603
195
-
196
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
197
-
198
-Phase 4.2 Post Placement Cleanup
199
-Phase 4.2 Post Placement Cleanup | Checksum: 1ae2aa603
200
-
201
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
202
-
203
-Phase 4.3 Placer Reporting
204
-Phase 4.3 Placer Reporting | Checksum: 1ae2aa603
205
-
206
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
207
-
208
-Phase 4.4 Final Placement Cleanup
209
-Phase 4.4 Final Placement Cleanup | Checksum: 1591ee552
210
-
211
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
212
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1591ee552
213
-
214
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1066.777 ; gain = 26.723
215
-Ending Placer Task | Checksum: dd20239e
216
-
217
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1066.777 ; gain = 26.723
218
-INFO: [Common 17-83] Releasing license: Implementation
219
-41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
220
-place_design completed successfully
221
-place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 1066.777 ; gain = 26.723
222
-Writing placer database...
223
-Writing XDEF routing.
224
-Writing XDEF routing logical nets.
225
-Writing XDEF routing special nets.
226
-Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.216 . Memory (MB): peak = 1066.777 ; gain = 0.000
227
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp' has been generated.
228
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1066.777 ; gain = 0.000
229
-report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1066.777 ; gain = 0.000
230
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1066.777 ; gain = 0.000
231
-Command: route_design -directive RuntimeOptimized
232
-Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
233
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
234
-Running DRC as a precondition to command route_design
235
-INFO: [DRC 23-27] Running DRC with 2 threads
236
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
237
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
238
-
239
-
240
-Starting Routing Task
241
-INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'.
242
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
243
-Checksum: PlaceDB: cf46d93b ConstDB: 0 ShapeSum: dd94a63 RouteDB: 0
244
-
245
-Phase 1 Build RT Design
246
-Phase 1 Build RT Design | Checksum: be9a9a9a
247
-
248
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
249
-
250
-Phase 2 Router Initialization
251
-
252
-Phase 2.1 Create Timer
253
-Phase 2.1 Create Timer | Checksum: be9a9a9a
254
-
255
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
256
-
257
-Phase 2.2 Fix Topology Constraints
258
-Phase 2.2 Fix Topology Constraints | Checksum: be9a9a9a
259
-
260
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
261
-
262
-Phase 2.3 Pre Route Cleanup
263
-Phase 2.3 Pre Route Cleanup | Checksum: be9a9a9a
264
-
265
-Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1178.578 ; gain = 111.801
266
- Number of Nodes with overlaps = 0
267
-
268
-Phase 2.4 Update Timing
269
-Phase 2.4 Update Timing | Checksum: 111c71c3e
270
-
271
-Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
272
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.198  | TNS=0.000  | WHS=-0.144 | THS=-6.171 |
273
-
274
-Phase 2 Router Initialization | Checksum: 1ee683561
275
-
276
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
277
-
278
-Phase 3 Initial Routing
279
-Phase 3 Initial Routing | Checksum: 10e02a291
280
-
281
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
282
-
283
-Phase 4 Rip-up And Reroute
284
-
285
-Phase 4.1 Global Iteration 0
286
- Number of Nodes with overlaps = 107
287
- Number of Nodes with overlaps = 0
288
-
289
-Phase 4.1.1 Update Timing
290
-Phase 4.1.1 Update Timing | Checksum: da308246
291
-
292
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
293
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
294
-
295
-Phase 4.1 Global Iteration 0 | Checksum: 1a9ed9d3a
296
-
297
-Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
298
-
299
-Phase 4.2 Global Iteration 1
300
- Number of Nodes with overlaps = 1
301
- Number of Nodes with overlaps = 0
302
-
303
-Phase 4.2.1 Update Timing
304
-Phase 4.2.1 Update Timing | Checksum: 1185cfc05
305
-
306
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
307
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.625  | TNS=0.000  | WHS=N/A    | THS=N/A    |
308
-
309
-Phase 4.2 Global Iteration 1 | Checksum: 18260d5a4
310
-
311
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
312
-Phase 4 Rip-up And Reroute | Checksum: 18260d5a4
313
-
314
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
315
-
316
-Phase 5 Delay and Skew Optimization
317
-
318
-Phase 5.1 Delay CleanUp
319
-Phase 5.1 Delay CleanUp | Checksum: 18260d5a4
320
-
321
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
322
-
323
-Phase 5.2 Clock Skew Optimization
324
-Phase 5.2 Clock Skew Optimization | Checksum: 18260d5a4
325
-
326
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
327
-Phase 5 Delay and Skew Optimization | Checksum: 18260d5a4
328
-
329
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
330
-
331
-Phase 6 Post Hold Fix
332
-
333
-Phase 6.1 Hold Fix Iter
334
-
335
-Phase 6.1.1 Update Timing
336
-Phase 6.1.1 Update Timing | Checksum: 16251cbd9
337
-
338
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
339
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
340
-
341
-Phase 6.1 Hold Fix Iter | Checksum: 12245b0d3
342
-
343
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
344
-Phase 6 Post Hold Fix | Checksum: 12245b0d3
345
-
346
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
347
-
348
-Phase 7 Route finalize
349
-
350
-Router Utilization Summary
351
-  Global Vertical Routing Utilization    = 0.234075 %
352
-  Global Horizontal Routing Utilization  = 0.228267 %
353
-  Routable Net Status*
354
-  *Does not include unroutable nets such as driverless and loadless.
355
-  Run report_route_status for detailed report.
356
-  Number of Failed Nets               = 0
357
-  Number of Unrouted Nets             = 0
358
-  Number of Partially Routed Nets     = 0
359
-  Number of Node Overlaps             = 0
360
-
361
-Phase 7 Route finalize | Checksum: 1af3f3601
362
-
363
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
364
-
365
-Phase 8 Verifying routed nets
366
-
367
- Verification completed successfully
368
-Phase 8 Verifying routed nets | Checksum: 1af3f3601
369
-
370
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1178.578 ; gain = 111.801
371
-
372
-Phase 9 Depositing Routes
373
-Phase 9 Depositing Routes | Checksum: 15d59118d
374
-
375
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
376
-
377
-Phase 10 Post Router Timing
378
-INFO: [Route 35-57] Estimated Timing Summary | WNS=3.717  | TNS=0.000  | WHS=0.062  | THS=0.000  |
379
-
380
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
381
-Phase 10 Post Router Timing | Checksum: 15d59118d
382
-
383
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
384
-INFO: [Route 35-16] Router Completed Successfully
385
-
386
-Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1178.578 ; gain = 111.801
387
-
388
-Routing Is Done.
389
-INFO: [Common 17-83] Releasing license: Implementation
390
-56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
391
-route_design completed successfully
392
-route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1178.578 ; gain = 111.801
393
-Writing placer database...
394
-Writing XDEF routing.
395
-Writing XDEF routing logical nets.
396
-Writing XDEF routing special nets.
397
-Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1178.578 ; gain = 0.000
398
-INFO: [Common 17-1381] The checkpoint 'C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_routed.dcp' has been generated.
399
-INFO: [DRC 23-27] Running DRC with 2 threads
400
-INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt.
401
-INFO: [Timing 38-35] Done setting XDC timing constraints.
402
-INFO: [DRC 23-133] Running Methodology with 2 threads
403
-INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Hp/Documents/Compteur8BitsBasys3/proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt.
404
-INFO: [Timing 38-35] Done setting XDC timing constraints.
405
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
406
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
407
-INFO: [Timing 38-35] Done setting XDC timing constraints.
408
-Command: report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
409
-Running Vector-less Activity Propagation...
410
-
411
-Finished Running Vector-less Activity Propagation
412
-66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
413
-report_power completed successfully
414
-INFO: [Common 17-206] Exiting Vivado at Fri Apr 09 23:16:39 2021...

+ 0
- 235
proj/GPIO.runs/impl_1/GPIO_demo_clock_utilization_routed.rpt View File

@@ -1,235 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:39 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_clock_utilization -file GPIO_demo_clock_utilization_routed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : 7a35t-cpg236
9
-| Speed File   : -1  PRODUCTION 1.16 2016-11-09
10
----------------------------------------------------------------------------------------
11
-
12
-Clock Utilization Report
13
-
14
-Table of Contents
15
------------------
16
-1. Clock Primitive Utilization
17
-2. Global Clock Resources
18
-3. Global Clock Source Details
19
-4. Clock Regions: Key Resource Utilization
20
-5. Clock Regions : Global Clock Summary
21
-6. Cell Type Counts per Global Clock: Region X0Y0
22
-7. Cell Type Counts per Global Clock: Region X1Y0
23
-8. Cell Type Counts per Global Clock: Region X0Y1
24
-9. Load Cell Placement Summary for Global Clock g0
25
-10. Load Cell Placement Summary for Global Clock g1
26
-11. Load Cell Placement Summary for Global Clock g2
27
-
28
-1. Clock Primitive Utilization
29
-------------------------------
30
-
31
-+----------+------+-----------+-----+--------------+--------+
32
-| Type     | Used | Available | LOC | Clock Region | Pblock |
33
-+----------+------+-----------+-----+--------------+--------+
34
-| BUFGCTRL |    3 |        32 |   0 |            0 |      0 |
35
-| BUFH     |    0 |        72 |   0 |            0 |      0 |
36
-| BUFIO    |    0 |        20 |   0 |            0 |      0 |
37
-| BUFMR    |    0 |        10 |   0 |            0 |      0 |
38
-| BUFR     |    0 |        20 |   0 |            0 |      0 |
39
-| MMCM     |    1 |         5 |   0 |            0 |      0 |
40
-| PLL      |    0 |         5 |   0 |            0 |      0 |
41
-+----------+------+-----------+-----+--------------+--------+
42
-
43
-
44
-2. Global Clock Resources
45
--------------------------
46
-
47
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
48
-| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock              | Driver Pin                                    | Net                                                    |
49
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
50
-| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |      |                   |                 2 |         336 |               0 |        9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf/O | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1               |
51
-| g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |      |                   |                 2 |         243 |               0 |       10.000 | sys_clk_pin        | CLK_IBUF_BUFG_inst/O                          | CLK_IBUF_BUFG                                          |
52
-| g2        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y2 | n/a          |      |                   |                 1 |           1 |               0 |       10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf/O    | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
53
-+-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+--------------------+-----------------------------------------------+--------------------------------------------------------+
54
-* Clock Loads column represents the clock pin loads (pin count)
55
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
56
-
57
-
58
-3. Global Clock Source Details
59
-------------------------------
60
-
61
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
62
-| Source Id | Global Id | Driver Type/Pin     | Constraint | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock       | Driver Pin                                             | Net                                                |
63
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
64
-| src0      | g0        | MMCME2_ADV/CLKOUT0  | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |               9.259 | clk_out1_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKOUT0  | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1_clk_wiz_0 |
65
-| src0      | g2        | MMCME2_ADV/CLKFBOUT | None       | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |              10.000 | clkfbout_clk_wiz_0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst/CLKFBOUT | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_clk_wiz_0 |
66
-| src1      | g1        | IBUF/O              | IOB_X1Y26  | IOB_X1Y26       | X1Y0         |           1 |               0 |              10.000 | sys_clk_pin        | CLK_IBUF_inst/O                                        | CLK_IBUF                                           |
67
-+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------------------------------+----------------------------------------------------+
68
-* Clock Loads column represents the clock pin loads (pin count)
69
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
70
-
71
-
72
-4. Clock Regions: Key Resource Utilization
73
-------------------------------------------
74
-
75
-+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
76
-|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
77
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
78
-| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
79
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
80
-| X0Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  484 |  1200 |  206 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
81
-| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   31 |  1500 |    2 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
82
-| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   63 |  1200 |   21 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
83
-| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
84
-| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
85
-| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
86
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
87
-* Global Clock column represents track count; while other columns represents cell counts
88
-
89
-
90
-5. Clock Regions : Global Clock Summary
91
----------------------------------------
92
-
93
-+----+----+----+
94
-|    | X0 | X1 |
95
-+----+----+----+
96
-| Y2 |  0 |  0 |
97
-| Y1 |  1 |  0 |
98
-| Y0 |  2 |  2 |
99
-+----+----+----+
100
-
101
-
102
-6. Cell Type Counts per Global Clock: Region X0Y0
103
--------------------------------------------------
104
-
105
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
106
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
107
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
108
-| g0        | n/a   | BUFG/O          | None       |         273 |               0 | 273 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
109
-| g1        | n/a   | BUFG/O          | None       |         211 |               0 | 211 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | CLK_IBUF_BUFG                            |
110
-+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------------------------+
111
-* Clock Loads column represents the clock pin loads (pin count)
112
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
113
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
114
-
115
-
116
-7. Cell Type Counts per Global Clock: Region X1Y0
117
--------------------------------------------------
118
-
119
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
120
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                                    |
121
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
122
-| g1        | n/a   | BUFG/O          | None       |          32 |               0 | 31 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | CLK_IBUF_BUFG                                          |
123
-| g2        | n/a   | BUFG/O          | None       |           1 |               0 |  0 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
124
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------------------------------+
125
-* Clock Loads column represents the clock pin loads (pin count)
126
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
127
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
128
-
129
-
130
-8. Cell Type Counts per Global Clock: Region X0Y1
131
--------------------------------------------------
132
-
133
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
134
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                      |
135
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
136
-| g0        | n/a   | BUFG/O          | None       |          63 |               0 | 63 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
137
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------+
138
-* Clock Loads column represents the clock pin loads (pin count)
139
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
140
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
141
-
142
-
143
-9. Load Cell Placement Summary for Global Clock g0
144
---------------------------------------------------
145
-
146
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
147
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                      |
148
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
149
-| g0        | BUFG/O          | n/a               | clk_out1_clk_wiz_0 |       9.259 | {0.000 4.630} |          |         336 |        0 |              0 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |
150
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------+
151
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
152
-** IO Loads column represents load cell count of IO types
153
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
154
-**** GT Loads column represents load cell count of GT types
155
-
156
-
157
-+----+------+----+
158
-|    | X0   | X1 |
159
-+----+------+----+
160
-| Y2 |    0 |  0 |
161
-| Y1 |   63 |  0 |
162
-| Y0 |  273 |  0 |
163
-+----+------+----+
164
-
165
-
166
-10. Load Cell Placement Summary for Global Clock g1
167
----------------------------------------------------
168
-
169
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
170
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
171
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
172
-| g1        | BUFG/O          | n/a               | sys_clk_pin |      10.000 | {0.000 5.000} |          |         242 |        0 |              1 |        0 | CLK_IBUF_BUFG |
173
-+-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------+
174
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
175
-** IO Loads column represents load cell count of IO types
176
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
177
-**** GT Loads column represents load cell count of GT types
178
-
179
-
180
-+----+------+-----+
181
-|    | X0   | X1  |
182
-+----+------+-----+
183
-| Y2 |    0 |   0 |
184
-| Y1 |    0 |   0 |
185
-| Y0 |  211 |  32 |
186
-+----+------+-----+
187
-
188
-
189
-11. Load Cell Placement Summary for Global Clock g2
190
----------------------------------------------------
191
-
192
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
193
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock              | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                                    |
194
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
195
-| g2        | BUFG/O          | n/a               | clkfbout_clk_wiz_0 |      10.000 | {0.000 5.000} |          |           0 |        0 |              1 |        0 | Inst_vga_ctrl/clk_wiz_0_inst/U0/clkfbout_buf_clk_wiz_0 |
196
-+-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------+
197
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
198
-** IO Loads column represents load cell count of IO types
199
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
200
-**** GT Loads column represents load cell count of GT types
201
-
202
-
203
-+----+----+----+
204
-|    | X0 | X1 |
205
-+----+----+----+
206
-| Y2 |  0 |  0 |
207
-| Y1 |  0 |  0 |
208
-| Y0 |  0 |  1 |
209
-+----+----+----+
210
-
211
-
212
-
213
-# Location of BUFG Primitives 
214
-set_property LOC BUFGCTRL_X0Y2 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkf_buf]
215
-set_property LOC BUFGCTRL_X0Y0 [get_cells Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf]
216
-set_property LOC BUFGCTRL_X0Y1 [get_cells CLK_IBUF_BUFG_inst]
217
-
218
-# Location of IO Primitives which is load of clock spine
219
-
220
-# Location of clock ports
221
-set_property LOC IOB_X1Y26 [get_ports CLK]
222
-
223
-# Clock net "Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1" driven by instance "Inst_vga_ctrl/clk_wiz_0_inst/U0/clkout1_buf" located at site "BUFGCTRL_X0Y0"
224
-#startgroup
225
-create_pblock {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}
226
-add_cells_to_pblock [get_pblocks  {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1"}]]]
227
-resize_pblock [get_pblocks {CLKAG_Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
228
-#endgroup
229
-
230
-# Clock net "CLK_IBUF_BUFG" driven by instance "CLK_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1"
231
-#startgroup
232
-create_pblock {CLKAG_CLK_IBUF_BUFG}
233
-add_cells_to_pblock [get_pblocks  {CLKAG_CLK_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=Inst_vga_ctrl/clk_wiz_0_inst/U0/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLK_IBUF_BUFG"}]]]
234
-resize_pblock [get_pblocks {CLKAG_CLK_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
235
-#endgroup

+ 0
- 104
proj/GPIO.runs/impl_1/GPIO_demo_control_sets_placed.rpt View File

@@ -1,104 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
---------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_control_sets -verbose -file GPIO_demo_control_sets_placed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35t
9
---------------------------------------------------------------------------------------
10
-
11
-Control Set Information
12
-
13
-Table of Contents
14
------------------
15
-1. Summary
16
-2. Flip-Flop Distribution
17
-3. Detailed Control Set Information
18
-
19
-1. Summary
20
-----------
21
-
22
-+----------------------------------------------------------+-------+
23
-|                          Status                          | Count |
24
-+----------------------------------------------------------+-------+
25
-| Number of unique control sets                            |    36 |
26
-| Unused register locations in slices containing registers |    94 |
27
-+----------------------------------------------------------+-------+
28
-
29
-
30
-2. Flip-Flop Distribution
31
--------------------------
32
-
33
-+--------------+-----------------------+------------------------+-----------------+--------------+
34
-| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
35
-+--------------+-----------------------+------------------------+-----------------+--------------+
36
-| No           | No                    | No                     |             132 |           57 |
37
-| No           | No                    | Yes                    |               0 |            0 |
38
-| No           | Yes                   | No                     |             226 |           57 |
39
-| Yes          | No                    | No                     |             105 |           40 |
40
-| Yes          | No                    | Yes                    |               0 |            0 |
41
-| Yes          | Yes                   | No                     |             115 |           32 |
42
-+--------------+-----------------------+------------------------+-----------------+--------------+
43
-
44
-
45
-3. Detailed Control Set Information
46
------------------------------------
47
-
48
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
49
-|                Clock Signal               |                                Enable Signal                               |                              Set/Reset Signal                              | Slice Load Count | Bel Load Count |
50
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
51
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/clk_inter0                   |                1 |              4 |
52
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/data_inter0                  |                1 |              4 |
53
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_overflow_i_1_n_0                             |                                                                            |                2 |              4 |
54
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/shift_frame                  | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/reset_bit_count              |                1 |              4 |
55
-|  CLK_IBUF_BUFG                            | eqOp2_in                                                                   | tmrVal[3]_i_1_n_0                                                          |                2 |              4 |
56
-|  CLK_IBUF_BUFG                            |                                                                            | sendStr[3][0]                                                              |                1 |              5 |
57
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_63clk_count[6]_i_1_n_0 |                2 |              7 |
58
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/g0_b0_n_0                                      |                                                                            |                2 |              7 |
59
-|  CLK_IBUF_BUFG                            | uartSend                                                                   |                                                                            |                2 |              7 |
60
-|  CLK_IBUF_BUFG                            | uartData                                                                   |                                                                            |                6 |              7 |
61
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/load_rx_data_reg_n_0         |                                                                            |                2 |              8 |
62
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_inc[7]_i_1_n_0                               |                                                                            |                3 |              8 |
63
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_inc[7]_i_1_n_0                               |                                                                            |                4 |              8 |
64
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/frame[9]_i_1_n_0             |                                                                            |                2 |             10 |
65
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/y_new_reg_n_0                                  |                                                                            |                3 |             11 |
66
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_20us_count[10]_i_1_n_0 |                3 |             11 |
67
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/eqOp4_in                                                     | Inst_vga_ctrl/v_cntr_reg0                                                  |                3 |             12 |
68
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/vga_red_reg[3]_i_1_n_0                                       |                2 |             12 |
69
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/eqOp4_in                                                     |                3 |             12 |
70
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/x_new_reg_n_0                                  |                                                                            |                4 |             12 |
71
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_2_n_0 | Inst_vga_ctrl/Inst_MouseCtl/Inst_Ps2Interface/delay_100us_count[0]_i_1_n_0 |                4 |             14 |
72
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_UART_TX_CTRL/bitTmr[0]_i_1_n_0                                        |                4 |             14 |
73
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[4][0]_i_1_n_0                              |                4 |             16 |
74
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[1][0]_i_1_n_0                              |                4 |             16 |
75
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[2][0]_i_1_n_0                              |                4 |             16 |
76
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[3][0]_i_1_n_0                              |                4 |             16 |
77
-|  CLK_IBUF_BUFG                            |                                                                            | Inst_btn_debounce/sig_cntrs_ary[0][0]_i_1_n_0                              |                4 |             16 |
78
-|  CLK_IBUF_BUFG                            |                                                                            |                                                                            |               10 |             17 |
79
-|  CLK_IBUF_BUFG                            |                                                                            | reset_cntr0                                                                |                5 |             18 |
80
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 | Inst_vga_ctrl/v_sync_reg                                                   |                                                                            |               10 |             23 |
81
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_timeout_cnt_reg_n_0                      |                7 |             24 |
82
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            | Inst_vga_ctrl/Inst_MouseCtl/reset_periodic_check_cnt                       |                6 |             26 |
83
-|  CLK_IBUF_BUFG                            |                                                                            | tmrCntr0                                                                   |                7 |             27 |
84
-|  CLK_IBUF_BUFG                            | uartData                                                                   | strIndex0                                                                  |                8 |             31 |
85
-|  CLK_IBUF_BUFG                            | Inst_UART_TX_CTRL/txBit_i_1_n_0                                            | Inst_UART_TX_CTRL/READY                                                    |                9 |             32 |
86
-|  Inst_vga_ctrl/clk_wiz_0_inst/U0/clk_out1 |                                                                            |                                                                            |               47 |            115 |
87
-+-------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+----------------+
88
-
89
-
90
-+--------+-----------------------+
91
-| Fanout | Number of ControlSets |
92
-+--------+-----------------------+
93
-| 4      |                     5 |
94
-| 5      |                     1 |
95
-| 7      |                     4 |
96
-| 8      |                     3 |
97
-| 10     |                     1 |
98
-| 11     |                     2 |
99
-| 12     |                     4 |
100
-| 14     |                     2 |
101
-| 16+    |                    14 |
102
-+--------+-----------------------+
103
-
104
-

+ 0
- 35
proj/GPIO.runs/impl_1/GPIO_demo_drc_opted.rpt View File

@@ -1,35 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
-------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:01 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_drc -file GPIO_demo_drc_opted.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Synthesized
11
-------------------------------------------------------------------------------------
12
-
13
-Report DRC
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-           Ruledeck: default
26
-             Max violations: <unlimited>
27
-             Violations found: 0
28
-+------+----------+-------------+------------+
29
-| Rule | Severity | Description | Violations |
30
-+------+----------+-------------+------------+
31
-+------+----------+-------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.pb View File


+ 0
- 35
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpt View File

@@ -1,35 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
----------------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:37 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_drc -file GPIO_demo_drc_routed.rpt -pb GPIO_demo_drc_routed.pb -rpx GPIO_demo_drc_routed.rpx
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Routed
11
----------------------------------------------------------------------------------------------------------------------
12
-
13
-Report DRC
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-           Ruledeck: default
26
-             Max violations: <unlimited>
27
-             Violations found: 0
28
-+------+----------+-------------+------------+
29
-| Rule | Severity | Description | Violations |
30
-+------+----------+-------------+------------+
31
-+------+----------+-------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_drc_routed.rpx View File


+ 0
- 277
proj/GPIO.runs/impl_1/GPIO_demo_io_placed.rpt View File

@@ -1,277 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
-------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:08 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_io -file GPIO_demo_io_placed.rpt
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35t
9
-| Speed File   : -1
10
-| Package      : cpg236
11
-------------------------------------------------------------------------------------
12
-
13
-IO Information
14
-
15
-Table of Contents
16
------------------
17
-1. Summary
18
-2. IO Assignments by Package Pin
19
-
20
-1. Summary
21
-----------
22
-
23
-+---------------+
24
-| Total User IO |
25
-+---------------+
26
-|            67 |
27
-+---------------+
28
-
29
-
30
-2. IO Assignments by Package Pin
31
---------------------------------
32
-
33
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
34
-| Pin Number | Signal Name  | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity |
35
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
36
-| A1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
37
-| A2         |              |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
38
-| A3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
39
-| A4         |              |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
40
-| A5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
41
-| A6         |              |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
42
-| A7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
43
-| A8         |              |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
44
-| A9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
45
-| A10        |              |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
46
-| A11        |              | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
47
-| A12        |              | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
48
-| A13        |              | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
49
-| A14        |              | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
50
-| A15        |              | High Range | IO_L6N_T0_VREF_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
51
-| A16        |              | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
52
-| A17        |              | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
53
-| A18        | UART_TXD     | High Range | IO_L19N_T3_VREF_16           | OUTPUT        | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
54
-| A19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
55
-| B1         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
56
-| B2         |              |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
57
-| B3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
58
-| B4         |              |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
59
-| B5         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
60
-| B6         |              |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
61
-| B7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
62
-| B8         |              |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
63
-| B9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
64
-| B10        |              |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
65
-| B11        |              | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
66
-| B12        |              | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
67
-| B13        |              | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
68
-| B14        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
69
-| B15        |              | High Range | IO_L11N_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
70
-| B16        |              | High Range | IO_L13N_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
71
-| B17        | PS2_DATA     | High Range | IO_L14N_T2_SRCC_16           | BIDIR         | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      | PULLUP    |          |      | NONE             |
72
-| B18        |              | High Range | IO_L19P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
73
-| B19        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
74
-| C1         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
75
-| C2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
76
-| C3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
77
-| C4         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
78
-| C5         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
79
-| C6         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
80
-| C7         |              |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
81
-| C8         |              | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
82
-| C9         |              | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
83
-| C10        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
84
-| C11        |              | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
85
-| C12        |              | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
86
-| C13        |              | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
87
-| C14        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
88
-| C15        |              | High Range | IO_L11P_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
89
-| C16        |              | High Range | IO_L13P_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |
90
-| C17        | PS2_CLK      | High Range | IO_L14P_T2_SRCC_16           | BIDIR         | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      | PULLUP    |          |      | NONE             |
91
-| C18        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
92
-| C19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
93
-| D1         |              |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
94
-| D2         |              |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
95
-| D3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
96
-| D17        | VGA_GREEN[3] | High Range | IO_0_14                      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
97
-| D18        |              | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
98
-| D19        |              | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
99
-| E1         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
100
-| E2         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
101
-| E3         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
102
-| E17        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
103
-| E18        |              | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
104
-| E19        | LED[1]       | High Range | IO_L3N_T0_DQS_EMCCLK_14      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
105
-| F1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
106
-| F2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
107
-| F3         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
108
-| F17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
109
-| F18        |              | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
110
-| F19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
111
-| G1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
112
-| G2         |              | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
113
-| G3         |              | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
114
-| G7         |              |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
115
-| G8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
116
-| G9         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
117
-| G10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
118
-| G11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
119
-| G12        |              | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
120
-| G13        |              | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
121
-| G17        | VGA_GREEN[2] | High Range | IO_L5N_T0_D07_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
122
-| G18        |              | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
123
-| G19        | VGA_RED[0]   | High Range | IO_L4N_T0_D05_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
124
-| H1         |              | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
125
-| H2         |              | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
126
-| H3         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
127
-| H7         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
128
-| H8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
129
-| H9         |              |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |
130
-| H10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
131
-| H11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
132
-| H12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
133
-| H13        |              |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |
134
-| H17        | VGA_GREEN[1] | High Range | IO_L5P_T0_D06_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
135
-| H18        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
136
-| H19        | VGA_RED[1]   | High Range | IO_L4P_T0_D04_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
137
-| J1         |              | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
138
-| J2         |              | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
139
-| J3         |              | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
140
-| J7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
141
-| J8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
142
-| J9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
143
-| J10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
144
-| J11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
145
-| J12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
146
-| J13        |              |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |
147
-| J17        | VGA_GREEN[0] | High Range | IO_L7P_T1_D09_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
148
-| J18        | VGA_BLUE[3]  | High Range | IO_L7N_T1_D10_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
149
-| J19        | VGA_RED[2]   | High Range | IO_L6N_T0_D08_VREF_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
150
-| K1         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
151
-| K2         |              | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
152
-| K3         |              | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
153
-| K7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
154
-| K8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
155
-| K12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
156
-| K13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
157
-| K17        |              | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
158
-| K18        | VGA_BLUE[2]  | High Range | IO_L8N_T1_D12_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
159
-| K19        |              | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
160
-| L1         | LED[15]      | High Range | IO_L6N_T0_VREF_35            | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
161
-| L2         |              | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
162
-| L3         |              | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
163
-| L7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
164
-| L8         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
165
-| L9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
166
-| L10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
167
-| L11        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
168
-| L12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
169
-| L13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
170
-| L17        |              | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
171
-| L18        | VGA_BLUE[1]  | High Range | IO_L8P_T1_D11_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
172
-| L19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
173
-| M1         |              | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
174
-| M2         |              | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
175
-| M3         |              | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
176
-| M7         |              | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
177
-| M8         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
178
-| M9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
179
-| M10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
180
-| M11        |              |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
181
-| M12        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
182
-| M13        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
183
-| M17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
184
-| M18        |              | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
185
-| M19        |              | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
186
-| N1         |              | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
187
-| N2         |              | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |
188
-| N3         | LED[13]      | High Range | IO_L12P_T1_MRCC_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
189
-| N7         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
190
-| N8         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
191
-| N9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
192
-| N10        |              |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |
193
-| N11        |              |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |
194
-| N12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
195
-| N13        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
196
-| N17        |              | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
197
-| N18        | VGA_BLUE[0]  | High Range | IO_L9P_T1_DQS_14             | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
198
-| N19        | VGA_RED[3]   | High Range | IO_L9N_T1_DQS_D13_14         | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
199
-| P1         | LED[14]      | High Range | IO_L19N_T3_VREF_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
200
-| P2         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
201
-| P3         | LED[12]      | High Range | IO_L12N_T1_MRCC_35           | OUTPUT        | LVCMOS33    |      35 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
202
-| P17        |              | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
203
-| P18        |              | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
204
-| P19        | VGA_HS       | High Range | IO_L10P_T1_D14_14            | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
205
-| R1         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
206
-| R2         | SW[15]       | High Range | IO_L1P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
207
-| R3         | SW[11]       | High Range | IO_L2P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
208
-| R17        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
209
-| R18        |              | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |
210
-| R19        | VGA_VS       | High Range | IO_L10N_T1_D15_14            | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
211
-| T1         | SW[14]       | High Range | IO_L3P_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
212
-| T2         | SW[10]       | High Range | IO_L1N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
213
-| T3         | SW[9]        | High Range | IO_L2N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
214
-| T17        | BTN[2]       | High Range | IO_L17P_T2_A14_D30_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
215
-| T18        | BTN[0]       | High Range | IO_L17N_T2_A13_D29_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
216
-| T19        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
217
-| U1         | SW[13]       | High Range | IO_L3N_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
218
-| U2         | SSEG_AN[0]   | High Range | IO_L9N_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
219
-| U3         | LED[11]      | High Range | IO_L9P_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
220
-| U4         | SSEG_AN[1]   | High Range | IO_L11P_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
221
-| U5         | SSEG_CA[4]   | High Range | IO_L16P_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
222
-| U6         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
223
-| U7         | SSEG_CA[6]   | High Range | IO_L19P_T3_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
224
-| U8         | SSEG_CA[2]   | High Range | IO_L14P_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
225
-| U9         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
226
-| U10        |              | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
227
-| U11        |              | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
228
-| U12        |              | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
229
-| U13        |              | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
230
-| U14        | LED[6]       | High Range | IO_25_14                     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
231
-| U15        | LED[5]       | High Range | IO_L23P_T3_A03_D19_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
232
-| U16        | LED[0]       | High Range | IO_L23N_T3_A02_D18_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
233
-| U17        | BTN[3]       | High Range | IO_L18P_T2_A12_D28_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
234
-| U18        | BTN[4]       | High Range | IO_L18N_T2_A11_D27_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
235
-| U19        | LED[2]       | High Range | IO_L15P_T2_DQS_RDWR_B_14     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
236
-| V1         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
237
-| V2         | SW[8]        | High Range | IO_L5P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
238
-| V3         | LED[9]       | High Range | IO_L6P_T0_34                 | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
239
-| V4         | SSEG_AN[2]   | High Range | IO_L11N_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
240
-| V5         | SSEG_CA[5]   | High Range | IO_L16N_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
241
-| V6         |              | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
242
-| V7         | SSEG_CA[7]   | High Range | IO_L19N_T3_VREF_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
243
-| V8         | SSEG_CA[3]   | High Range | IO_L14N_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
244
-| V9         |              | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
245
-| V10        |              | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
246
-| V11        |              | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |
247
-| V12        |              | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
248
-| V13        | LED[8]       | High Range | IO_L24P_T3_A01_D17_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
249
-| V14        | LED[7]       | High Range | IO_L24N_T3_A00_D16_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
250
-| V15        | SW[5]        | High Range | IO_L21P_T3_DQS_14            | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
251
-| V16        | SW[1]        | High Range | IO_L19P_T3_A10_D26_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
252
-| V17        | SW[0]        | High Range | IO_L19N_T3_A09_D25_VREF_14   | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
253
-| V18        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
254
-| V19        | LED[3]       | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
255
-| W1         |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
256
-| W2         | SW[12]       | High Range | IO_L5N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
257
-| W3         | LED[10]      | High Range | IO_L6N_T0_VREF_34            | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
258
-| W4         | SSEG_AN[3]   | High Range | IO_L12N_T1_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
259
-| W5         | CLK          | High Range | IO_L12P_T1_MRCC_34           | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
260
-| W6         | SSEG_CA[1]   | High Range | IO_L13N_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
261
-| W7         | SSEG_CA[0]   | High Range | IO_L13P_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
262
-| W8         |              | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
263
-| W9         |              | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
264
-| W10        |              | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
265
-| W11        |              | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |
266
-| W12        |              |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |
267
-| W13        | SW[7]        | High Range | IO_L22P_T3_A05_D21_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
268
-| W14        | SW[6]        | High Range | IO_L22N_T3_A04_D20_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
269
-| W15        | SW[4]        | High Range | IO_L21N_T3_DQS_A06_D22_14    | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
270
-| W16        | SW[2]        | High Range | IO_L20P_T3_A08_D24_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
271
-| W17        | SW[3]        | High Range | IO_L20N_T3_A07_D23_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
272
-| W18        | LED[4]       | High Range | IO_L16P_T2_CSI_B_14          | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |
273
-| W19        | BTN[1]       | High Range | IO_L16N_T2_A15_D31_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |
274
-+------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+
275
-* Default value
276
-
277
-

+ 0
- 205
proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpt View File

@@ -1,205 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
--------------------------------------------------------------------------------------------------------------------------
3
-| Tool Version : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date         : Fri Apr 09 23:16:38 2021
5
-| Host         : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command      : report_methodology -file GPIO_demo_methodology_drc_routed.rpt -rpx GPIO_demo_methodology_drc_routed.rpx
7
-| Design       : GPIO_demo
8
-| Device       : xc7a35tcpg236-1
9
-| Speed File   : -1
10
-| Design State : Routed
11
--------------------------------------------------------------------------------------------------------------------------
12
-
13
-Report Methodology
14
-
15
-Table of Contents
16
------------------
17
-1. REPORT SUMMARY
18
-2. REPORT DETAILS
19
-
20
-1. REPORT SUMMARY
21
------------------
22
-            Netlist: netlist
23
-          Floorplan: design_1
24
-      Design limits: <entire design considered>
25
-             Max violations: <unlimited>
26
-             Violations found: 34
27
-+-----------+----------+-------------------------------+------------+
28
-| Rule      | Severity | Description                   | Violations |
29
-+-----------+----------+-------------------------------+------------+
30
-| TIMING-18 | Warning  | Missing input or output delay | 34         |
31
-+-----------+----------+-------------------------------+------------+
32
-
33
-2. REPORT DETAILS
34
------------------
35
-TIMING-18#1 Warning
36
-Missing input or output delay  
37
-An input delay is missing on BTN[0] relative to clock(s) sys_clk_pin 
38
-Related violations: <none>
39
-
40
-TIMING-18#2 Warning
41
-Missing input or output delay  
42
-An input delay is missing on BTN[1] relative to clock(s) sys_clk_pin 
43
-Related violations: <none>
44
-
45
-TIMING-18#3 Warning
46
-Missing input or output delay  
47
-An input delay is missing on BTN[2] relative to clock(s) sys_clk_pin 
48
-Related violations: <none>
49
-
50
-TIMING-18#4 Warning
51
-Missing input or output delay  
52
-An input delay is missing on BTN[3] relative to clock(s) sys_clk_pin 
53
-Related violations: <none>
54
-
55
-TIMING-18#5 Warning
56
-Missing input or output delay  
57
-An input delay is missing on BTN[4] relative to clock(s) sys_clk_pin 
58
-Related violations: <none>
59
-
60
-TIMING-18#6 Warning
61
-Missing input or output delay  
62
-An input delay is missing on PS2_CLK relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
63
-Related violations: <none>
64
-
65
-TIMING-18#7 Warning
66
-Missing input or output delay  
67
-An input delay is missing on PS2_DATA relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
68
-Related violations: <none>
69
-
70
-TIMING-18#8 Warning
71
-Missing input or output delay  
72
-An output delay is missing on SSEG_AN[0] relative to clock(s) sys_clk_pin 
73
-Related violations: <none>
74
-
75
-TIMING-18#9 Warning
76
-Missing input or output delay  
77
-An output delay is missing on SSEG_AN[1] relative to clock(s) sys_clk_pin 
78
-Related violations: <none>
79
-
80
-TIMING-18#10 Warning
81
-Missing input or output delay  
82
-An output delay is missing on SSEG_AN[2] relative to clock(s) sys_clk_pin 
83
-Related violations: <none>
84
-
85
-TIMING-18#11 Warning
86
-Missing input or output delay  
87
-An output delay is missing on SSEG_AN[3] relative to clock(s) sys_clk_pin 
88
-Related violations: <none>
89
-
90
-TIMING-18#12 Warning
91
-Missing input or output delay  
92
-An output delay is missing on SSEG_CA[0] relative to clock(s) sys_clk_pin 
93
-Related violations: <none>
94
-
95
-TIMING-18#13 Warning
96
-Missing input or output delay  
97
-An output delay is missing on SSEG_CA[1] relative to clock(s) sys_clk_pin 
98
-Related violations: <none>
99
-
100
-TIMING-18#14 Warning
101
-Missing input or output delay  
102
-An output delay is missing on SSEG_CA[2] relative to clock(s) sys_clk_pin 
103
-Related violations: <none>
104
-
105
-TIMING-18#15 Warning
106
-Missing input or output delay  
107
-An output delay is missing on SSEG_CA[3] relative to clock(s) sys_clk_pin 
108
-Related violations: <none>
109
-
110
-TIMING-18#16 Warning
111
-Missing input or output delay  
112
-An output delay is missing on SSEG_CA[4] relative to clock(s) sys_clk_pin 
113
-Related violations: <none>
114
-
115
-TIMING-18#17 Warning
116
-Missing input or output delay  
117
-An output delay is missing on SSEG_CA[5] relative to clock(s) sys_clk_pin 
118
-Related violations: <none>
119
-
120
-TIMING-18#18 Warning
121
-Missing input or output delay  
122
-An output delay is missing on SSEG_CA[6] relative to clock(s) sys_clk_pin 
123
-Related violations: <none>
124
-
125
-TIMING-18#19 Warning
126
-Missing input or output delay  
127
-An output delay is missing on SSEG_CA[7] relative to clock(s) sys_clk_pin 
128
-Related violations: <none>
129
-
130
-TIMING-18#20 Warning
131
-Missing input or output delay  
132
-An output delay is missing on UART_TXD relative to clock(s) sys_clk_pin 
133
-Related violations: <none>
134
-
135
-TIMING-18#21 Warning
136
-Missing input or output delay  
137
-An output delay is missing on VGA_BLUE[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
138
-Related violations: <none>
139
-
140
-TIMING-18#22 Warning
141
-Missing input or output delay  
142
-An output delay is missing on VGA_BLUE[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
143
-Related violations: <none>
144
-
145
-TIMING-18#23 Warning
146
-Missing input or output delay  
147
-An output delay is missing on VGA_BLUE[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
148
-Related violations: <none>
149
-
150
-TIMING-18#24 Warning
151
-Missing input or output delay  
152
-An output delay is missing on VGA_BLUE[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
153
-Related violations: <none>
154
-
155
-TIMING-18#25 Warning
156
-Missing input or output delay  
157
-An output delay is missing on VGA_GREEN[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
158
-Related violations: <none>
159
-
160
-TIMING-18#26 Warning
161
-Missing input or output delay  
162
-An output delay is missing on VGA_GREEN[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
163
-Related violations: <none>
164
-
165
-TIMING-18#27 Warning
166
-Missing input or output delay  
167
-An output delay is missing on VGA_GREEN[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
168
-Related violations: <none>
169
-
170
-TIMING-18#28 Warning
171
-Missing input or output delay  
172
-An output delay is missing on VGA_GREEN[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
173
-Related violations: <none>
174
-
175
-TIMING-18#29 Warning
176
-Missing input or output delay  
177
-An output delay is missing on VGA_HS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
178
-Related violations: <none>
179
-
180
-TIMING-18#30 Warning
181
-Missing input or output delay  
182
-An output delay is missing on VGA_RED[0] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
183
-Related violations: <none>
184
-
185
-TIMING-18#31 Warning
186
-Missing input or output delay  
187
-An output delay is missing on VGA_RED[1] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
188
-Related violations: <none>
189
-
190
-TIMING-18#32 Warning
191
-Missing input or output delay  
192
-An output delay is missing on VGA_RED[2] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
193
-Related violations: <none>
194
-
195
-TIMING-18#33 Warning
196
-Missing input or output delay  
197
-An output delay is missing on VGA_RED[3] relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
198
-Related violations: <none>
199
-
200
-TIMING-18#34 Warning
201
-Missing input or output delay  
202
-An output delay is missing on VGA_VS relative to clock(s) VIRTUAL_clk_out1_clk_wiz_0 
203
-Related violations: <none>
204
-
205
-

BIN
proj/GPIO.runs/impl_1/GPIO_demo_methodology_drc_routed.rpx View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_opt.dcp View File


BIN
proj/GPIO.runs/impl_1/GPIO_demo_placed.dcp View File


+ 0
- 157
proj/GPIO.runs/impl_1/GPIO_demo_power_routed.rpt View File

@@ -1,157 +0,0 @@
1
-Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
2
--------------------------------------------------------------------------------------------------------------------------------------------------
3
-| Tool Version     : Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
4
-| Date             : Fri Apr 09 23:16:38 2021
5
-| Host             : DESKTOP-GN6T5R2 running 64-bit major release  (build 9200)
6
-| Command          : report_power -file GPIO_demo_power_routed.rpt -pb GPIO_demo_power_summary_routed.pb -rpx GPIO_demo_power_routed.rpx
7
-| Design           : GPIO_demo
8
-| Device           : xc7a35tcpg236-1
9
-| Design State     : routed
10
-| Grade            : commercial
11
-| Process          : typical
12
-| Characterization : Production
13
--------------------------------------------------------------------------------------------------------------------------------------------------
14
-
15
-Power Report
16
-
17
-Table of Contents
18
------------------
19
-1. Summary
20
-1.1 On-Chip Components
21
-1.2 Power Supply Summary
22
-1.3 Confidence Level
23
-2. Settings
24
-2.1 Environment
25
-2.2 Clock Constraints
26
-3. Detailed Reports
27
-3.1 By Hierarchy
28
-
29
-1. Summary
30
-----------
31
-
32
-+--------------------------+-------+
33
-| Total On-Chip Power (W)  | 0.223 |
34
-| Dynamic (W)              | 0.151 |
35
-| Device Static (W)        | 0.072 |
36
-| Effective TJA (C/W)      | 5.0   |
37
-| Max Ambient (C)          | 83.9  |
38
-| Junction Temperature (C) | 26.1  |
39
-| Confidence Level         | Low   |
40
-| Setting File             | ---   |
41
-| Simulation Activity File | ---   |
42
-| Design Nets Matched      | NA    |
43
-+--------------------------+-------+
44
-
45
-
46
-1.1 On-Chip Components
47
-----------------------
48
-
49
-+----------------+-----------+----------+-----------+-----------------+
50
-| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
51
-+----------------+-----------+----------+-----------+-----------------+
52
-| Clocks         |     0.005 |        5 |       --- |             --- |
53
-| Slice Logic    |     0.003 |     1426 |       --- |             --- |
54
-|   LUT as Logic |     0.002 |      564 |     20800 |            2.71 |
55
-|   CARRY4       |    <0.001 |      132 |      8150 |            1.62 |
56
-|   Register     |    <0.001 |      578 |     41600 |            1.39 |
57
-|   F7/F8 Muxes  |    <0.001 |        3 |     32600 |           <0.01 |
58
-|   Others       |     0.000 |       18 |       --- |             --- |
59
-| Signals        |     0.002 |     1137 |       --- |             --- |
60
-| MMCM           |     0.123 |        1 |         5 |           20.00 |
61
-| I/O            |     0.018 |       67 |       106 |           63.21 |
62
-| Static Power   |     0.072 |          |           |                 |
63
-| Total          |     0.223 |          |           |                 |
64
-+----------------+-----------+----------+-----------+-----------------+
65
-
66
-
67
-1.2 Power Supply Summary
68
-------------------------
69
-
70
-+-----------+-------------+-----------+-------------+------------+
71
-| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
72
-+-----------+-------------+-----------+-------------+------------+
73
-| Vccint    |       1.000 |     0.020 |       0.010 |      0.010 |
74
-| Vccaux    |       1.800 |     0.081 |       0.069 |      0.013 |
75
-| Vcco33    |       3.300 |     0.006 |       0.005 |      0.001 |
76
-| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
77
-| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
78
-| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
79
-| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
80
-| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
81
-| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
82
-| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |
83
-| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |